[binutils.git] / gdb / i386-tdep.h

/* Target-dependent code for the i386.

   Copyright (C) 2001, 2002, 2003, 2004, 2006, 2007, 2008, 2009, 2010, 2011
   Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef I386_TDEP_H
#define I386_TDEP_H

struct frame_info;
struct gdbarch;
struct reggroup;
struct regset;
struct regcache;

/* GDB's i386 target supports both the 32-bit Intel Architecture
   (IA-32) and the 64-bit AMD x86-64 architecture.  Internally it uses
   a similar register layout for both.

   - General purpose registers
   - FPU data registers
   - FPU control registers
   - SSE data registers
   - SSE control register

   The general purpose registers for the x86-64 architecture are quite
   different from IA-32.  Therefore, gdbarch_fp0_regnum
   determines the register number at which the FPU data registers
   start.  The number of FPU data and control registers is the same
   for both architectures.  The number of SSE registers however,
   differs and is determined by the num_xmm_regs member of `struct
   gdbarch_tdep'.  */

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Register classes as defined in the AMD x86-64 psABI.  */

enum amd64_reg_class
{
  AMD64_INTEGER,
  AMD64_SSE,
  AMD64_SSEUP,
  AMD64_X87,
  AMD64_X87UP,
  AMD64_COMPLEX_X87,
  AMD64_NO_CLASS,
  AMD64_MEMORY
};

/* i386 architecture specific information.  */
struct gdbarch_tdep
{
  /* General-purpose registers.  */
  struct regset *gregset;
  int *gregset_reg_offset;
  int gregset_num_regs;
  size_t sizeof_gregset;

  /* The general-purpose registers used to pass integers when making
     function calls.  This only applies to amd64, as all parameters
     are passed through the stack on x86.  */
  int call_dummy_num_integer_regs;
  int *call_dummy_integer_regs;

  /* Used on amd64 only.  Classify TYPE according to calling conventions,
     and store the result in CLASS.  */
  void (*classify) (struct type *type, enum amd64_reg_class class[2]);

  /* Used on amd64 only.  Non-zero if the first few MEMORY arguments
     should be passed by pointer.

     More precisely, MEMORY arguments are passed through the stack.
     But certain architectures require that their address be passed
     by register as well, if there are still some integer registers
     available for argument passing.  */
  int memory_args_by_pointer;

  /* Used on amd64 only.

     If non-zero, then the callers of a function are expected to reserve
     some space in the stack just before the area where the PC is saved
     so that the callee may save the integer-parameter registers there.
     The amount of space is dependent on the list of registers used for
     integer parameter passing (see component call_dummy_num_integer_regs
     above).  */
  int integer_param_regs_saved_in_caller_frame;

  /* Floating-point registers.  */
  struct regset *fpregset;
  size_t sizeof_fpregset;

  /* XSAVE extended state.  */
  struct regset *xstateregset;

  /* Register number for %st(0).  The register numbers for the other
     registers follow from this one.  Set this to -1 to indicate the
     absence of an FPU.  */
  int st0_regnum;

  /* Number of MMX registers.  */
  int num_mmx_regs;

  /* Register number for %mm0.  Set this to -1 to indicate the absence
     of MMX support.  */
  int mm0_regnum;

  /* Number of pseudo YMM registers.  */
  int num_ymm_regs;

  /* Register number for %ymm0.  Set this to -1 to indicate the absence
     of pseudo YMM register support.  */
  int ymm0_regnum;

  /* Number of byte registers.  */
  int num_byte_regs;

  /* Register pseudo number for %al.  */
  int al_regnum;

  /* Number of pseudo word registers.  */
  int num_word_regs;

  /* Register number for %ax.  */
  int ax_regnum;

  /* Number of pseudo dword registers.  */
  int num_dword_regs;

  /* Register number for %eax.  Set this to -1 to indicate the absence
     of pseudo dword register support.  */
  int eax_regnum;

  /* Number of core registers.  */
  int num_core_regs;

  /* Number of SSE registers.  */
  int num_xmm_regs;

  /* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
     register), excluding the x87 bit, which are supported by this GDB.  */

  uint64_t xcr0;

  /* Offset of XCR0 in XSAVE extended state.  */
  int xsave_xcr0_offset;

  /* Register names.  */
  const char **register_names;

  /* Register number for %ymm0h.  Set this to -1 to indicate the absence
     of upper YMM register support.  */
  int ymm0h_regnum;

  /* Upper YMM register names.  Only used for tdesc_numbered_register.  */
  const char **ymmh_register_names;

  /* Target description.  */
  const struct target_desc *tdesc;

  /* Register group function.  */
  const void *register_reggroup_p;

  /* Offset of saved PC in jmp_buf.  */
  int jb_pc_offset;

  /* Convention for returning structures.  */
  enum struct_return struct_return;

  /* Address range where sigtramp lives.  */
  CORE_ADDR sigtramp_start;
  CORE_ADDR sigtramp_end;

  /* Detect sigtramp.  */
  int (*sigtramp_p) (struct frame_info *);

  /* Get address of sigcontext for sigtramp.  */
  CORE_ADDR (*sigcontext_addr) (struct frame_info *);

  /* Offset of registers in `struct sigcontext'.  */
  int *sc_reg_offset;
  int sc_num_regs;

  /* Offset of saved PC and SP in `struct sigcontext'.  Usage of these
     is deprecated, please use `sc_reg_offset' instead.  */
  int sc_pc_offset;
  int sc_sp_offset;

  /* ISA-specific data types.  */
  struct type *i386_mmx_type;
  struct type *i386_ymm_type;
  struct type *i387_ext_type;

  /* Process record/replay target.  */
  /* The map for registers because the AMD64's registers order
     in GDB is not same as I386 instructions.  */
  const int *record_regmap;
  /* Parse intx80 args.  */
  int (*i386_intx80_record) (struct regcache *regcache);
  /* Parse sysenter args.  */
  int (*i386_sysenter_record) (struct regcache *regcache);
  /* Parse syscall args.  */
  int (*i386_syscall_record) (struct regcache *regcache);
};

/* Floating-point registers.  */

/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
   (at most) in the FPU, but are zero-extended to 32 bits in GDB's
   register cache.  */

/* Return non-zero if REGNUM matches the FP register and the FP
   register set is active.  */
extern int i386_fp_regnum_p (struct gdbarch *, int);
extern int i386_fpc_regnum_p (struct gdbarch *, int);

/* Register numbers of various important registers.  */

enum i386_regnum
{
  I386_EAX_REGNUM,		/* %eax */
  I386_ECX_REGNUM,		/* %ecx */
  I386_EDX_REGNUM,		/* %edx */
  I386_EBX_REGNUM,		/* %ebx */
  I386_ESP_REGNUM,		/* %esp */
  I386_EBP_REGNUM,		/* %ebp */
  I386_ESI_REGNUM,		/* %esi */
  I386_EDI_REGNUM,		/* %edi */
  I386_EIP_REGNUM,		/* %eip */
  I386_EFLAGS_REGNUM,		/* %eflags */
  I386_CS_REGNUM,		/* %cs */
  I386_SS_REGNUM,		/* %ss */
  I386_DS_REGNUM,		/* %ds */
  I386_ES_REGNUM,		/* %es */
  I386_FS_REGNUM,		/* %fs */
  I386_GS_REGNUM,		/* %gs */
  I386_ST0_REGNUM,		/* %st(0) */
  I386_MXCSR_REGNUM = 40,	/* %mxcsr */ 
  I386_YMM0H_REGNUM,		/* %ymm0h */
  I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7
};

/* Register numbers of RECORD_REGMAP.  */

enum record_i386_regnum
{
  X86_RECORD_REAX_REGNUM,
  X86_RECORD_RECX_REGNUM,
  X86_RECORD_REDX_REGNUM,
  X86_RECORD_REBX_REGNUM,
  X86_RECORD_RESP_REGNUM,
  X86_RECORD_REBP_REGNUM,
  X86_RECORD_RESI_REGNUM,
  X86_RECORD_REDI_REGNUM,
  X86_RECORD_R8_REGNUM,
  X86_RECORD_R9_REGNUM,
  X86_RECORD_R10_REGNUM,
  X86_RECORD_R11_REGNUM,
  X86_RECORD_R12_REGNUM,
  X86_RECORD_R13_REGNUM,
  X86_RECORD_R14_REGNUM,
  X86_RECORD_R15_REGNUM,
  X86_RECORD_REIP_REGNUM,
  X86_RECORD_EFLAGS_REGNUM,
  X86_RECORD_CS_REGNUM,
  X86_RECORD_SS_REGNUM,
  X86_RECORD_DS_REGNUM,
  X86_RECORD_ES_REGNUM,
  X86_RECORD_FS_REGNUM,
  X86_RECORD_GS_REGNUM,
};

#define I386_NUM_GREGS	16
#define I386_NUM_XREGS  9

#define I386_SSE_NUM_REGS	(I386_MXCSR_REGNUM + 1)
#define I386_AVX_NUM_REGS	(I386_YMM7H_REGNUM + 1)

/* Size of the largest register.  */
#define I386_MAX_REGISTER_SIZE	16

/* Types for i386-specific registers.  */
extern struct type *i387_ext_type (struct gdbarch *gdbarch);

/* Checks of different pseudo-registers.  */
extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);

extern const char *i386_pseudo_register_name (struct gdbarch *gdbarch,
					      int regnum);

extern void i386_pseudo_register_read (struct gdbarch *gdbarch,
				       struct regcache *regcache,
				       int regnum, gdb_byte *buf);
extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
					struct regcache *regcache,
					int regnum, const gdb_byte *buf);

/* Segment selectors.  */
#define I386_SEL_RPL	0x0003  /* Requester's Privilege Level mask.  */
#define I386_SEL_UPL	0x0003	/* User Privilige Level.  */
#define I386_SEL_KPL	0x0000	/* Kernel Privilige Level.  */

/* The length of the longest i386 instruction (according to
   include/asm-i386/kprobes.h in Linux 2.6.  */
#define I386_MAX_INSN_LEN (16)

/* Functions exported from i386-tdep.c.  */
extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
					       CORE_ADDR pc, char *name);
extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
					  CORE_ADDR pc);

/* Return whether the THIS_FRAME corresponds to a sigtramp routine.  */
extern int i386_sigtramp_p (struct frame_info *this_frame);

/* Return non-zero if REGNUM is a member of the specified group.  */
extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
				     struct reggroup *group);

/* Supply register REGNUM from the general-purpose register set REGSET
   to register cache REGCACHE.  If REGNUM is -1, do this for all
   registers in REGSET.  */
extern void i386_supply_gregset (const struct regset *regset,
				 struct regcache *regcache, int regnum,
				 const void *gregs, size_t len);

/* Collect register REGNUM from the register cache REGCACHE and store
   it in the buffer specified by GREGS and LEN as described by the
   general-purpose register set REGSET.  If REGNUM is -1, do this for
   all registers in REGSET.  */
extern void i386_collect_gregset (const struct regset *regset,
				  const struct regcache *regcache,
				  int regnum, void *gregs, size_t len);

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */
extern const struct regset *
  i386_regset_from_core_section (struct gdbarch *gdbarch,
				 const char *sect_name, size_t sect_size);


extern struct displaced_step_closure *i386_displaced_step_copy_insn
  (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
   struct regcache *regs);
extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
				       struct displaced_step_closure *closure,
				       CORE_ADDR from, CORE_ADDR to,
				       struct regcache *regs);

/* Initialize a basic ELF architecture variant.  */
extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);

/* Initialize a SVR4 architecture variant.  */
extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);

extern int i386_process_record (struct gdbarch *gdbarch,
                                struct regcache *regcache, CORE_ADDR addr);
\f

/* Functions and variables exported from i386bsd-tdep.c.  */

extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
extern CORE_ADDR i386fbsd_sigtramp_start_addr;
extern CORE_ADDR i386fbsd_sigtramp_end_addr;
extern CORE_ADDR i386obsd_sigtramp_start_addr;
extern CORE_ADDR i386obsd_sigtramp_end_addr;
extern int i386fbsd4_sc_reg_offset[];
extern int i386fbsd_sc_reg_offset[];
extern int i386nbsd_sc_reg_offset[];
extern int i386obsd_sc_reg_offset[];
extern int i386bsd_sc_reg_offset[];

#endif /* i386-tdep.h */
Commit	Line	Data
5716833c MK	1	/* Target-dependent code for the i386.
5716833c MK	2
7b6bb8da	3	Copyright (C) 2001, 2002, 2003, 2004, 2006, 2007, 2008, 2009, 2010, 2011
5ae96ec1	4	Free Software Foundation, Inc.
9a82579f JS	5
	6	This file is part of GDB.
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
a9762ec7	10	the Free Software Foundation; either version 3 of the License, or
9a82579f JS	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
	17
	18	You should have received a copy of the GNU General Public License
a9762ec7	19	along with this program. If not, see <http://www.gnu.org/licenses/>. */
9a82579f JS	20
	21	#ifndef I386_TDEP_H
	22	#define I386_TDEP_H
	23
da3331ec	24	struct frame_info;
5716833c MK	25	struct gdbarch;
5716833c MK	26	struct reggroup;
c783cbd6	27	struct regset;
5439edaa	28	struct regcache;
da3331ec	29
96297dab MK	30	/* GDB's i386 target supports both the 32-bit Intel Architecture
	31	(IA-32) and the 64-bit AMD x86-64 architecture. Internally it uses
	32	a similar register layout for both.
	33
	34	- General purpose registers
	35	- FPU data registers
	36	- FPU control registers
	37	- SSE data registers
	38	- SSE control register
	39
	40	The general purpose registers for the x86-64 architecture are quite
3e8c568d	41	different from IA-32. Therefore, gdbarch_fp0_regnum
96297dab MK	42	determines the register number at which the FPU data registers
	43	start. The number of FPU data and control registers is the same
	44	for both architectures. The number of SSE registers however,
	45	differs and is determined by the num_xmm_regs member of `struct
	46	gdbarch_tdep'. */
	47
8201327c	48	/* Convention for returning structures. */
3ce1502b	49
8201327c MK	50	enum struct_return
	51	{
	52	pcc_struct_return, /* Return "short" structures in memory. */
	53	reg_struct_return /* Return "short" structures in registers. */
3ce1502b MK	54	};
3ce1502b MK	55
ba581dc1 JB	56	/* Register classes as defined in the AMD x86-64 psABI. */
	57
	58	enum amd64_reg_class
	59	{
	60	AMD64_INTEGER,
	61	AMD64_SSE,
	62	AMD64_SSEUP,
	63	AMD64_X87,
	64	AMD64_X87UP,
	65	AMD64_COMPLEX_X87,
	66	AMD64_NO_CLASS,
	67	AMD64_MEMORY
	68	};
	69
96297dab MK	70	/* i386 architecture specific information. */
	71	struct gdbarch_tdep
	72	{
473f17b0 MK	73	/* General-purpose registers. */
	74	struct regset *gregset;
	75	int *gregset_reg_offset;
	76	int gregset_num_regs;
	77	size_t sizeof_gregset;
	78
ba581dc1 JB	79	/* The general-purpose registers used to pass integers when making
	80	function calls. This only applies to amd64, as all parameters
	81	are passed through the stack on x86. */
	82	int call_dummy_num_integer_regs;
	83	int *call_dummy_integer_regs;
	84
3af6ddfe JB	85	/* Used on amd64 only. Classify TYPE according to calling conventions,
3af6ddfe JB	86	and store the result in CLASS. */
ba581dc1 JB	87	void (classify) (struct type type, enum amd64_reg_class class[2]);
ba581dc1 JB	88
3af6ddfe JB	89	/* Used on amd64 only. Non-zero if the first few MEMORY arguments
3af6ddfe JB	90	should be passed by pointer.
80d19a06 JB	91
	92	More precisely, MEMORY arguments are passed through the stack.
	93	But certain architectures require that their address be passed
	94	by register as well, if there are still some integer registers
	95	available for argument passing. */
	96	int memory_args_by_pointer;
	97
3af6ddfe JB	98	/* Used on amd64 only.
	99
	100	If non-zero, then the callers of a function are expected to reserve
	101	some space in the stack just before the area where the PC is saved
	102	so that the callee may save the integer-parameter registers there.
	103	The amount of space is dependent on the list of registers used for
	104	integer parameter passing (see component call_dummy_num_integer_regs
	105	above). */
	106	int integer_param_regs_saved_in_caller_frame;
	107
473f17b0 MK	108	/* Floating-point registers. */
	109	struct regset *fpregset;
	110	size_t sizeof_fpregset;
	111
c131fcee L	112	/* XSAVE extended state. */
	113	struct regset *xstateregset;
	114
5716833c MK	115	/* Register number for %st(0). The register numbers for the other
	116	registers follow from this one. Set this to -1 to indicate the
	117	absence of an FPU. */
	118	int st0_regnum;
	119
1ba53b71 L	120	/* Number of MMX registers. */
	121	int num_mmx_regs;
	122
5716833c MK	123	/* Register number for %mm0. Set this to -1 to indicate the absence
	124	of MMX support. */
	125	int mm0_regnum;
	126
c131fcee L	127	/* Number of pseudo YMM registers. */
	128	int num_ymm_regs;
	129
	130	/* Register number for %ymm0. Set this to -1 to indicate the absence
	131	of pseudo YMM register support. */
	132	int ymm0_regnum;
	133
1ba53b71 L	134	/* Number of byte registers. */
	135	int num_byte_regs;
	136
	137	/* Register pseudo number for %al. */
	138	int al_regnum;
	139
	140	/* Number of pseudo word registers. */
	141	int num_word_regs;
	142
	143	/* Register number for %ax. */
	144	int ax_regnum;
	145
	146	/* Number of pseudo dword registers. */
	147	int num_dword_regs;
	148
	149	/* Register number for %eax. Set this to -1 to indicate the absence
	150	of pseudo dword register support. */
	151	int eax_regnum;
	152
90884b2b L	153	/* Number of core registers. */
	154	int num_core_regs;
	155
96297dab MK	156	/* Number of SSE registers. */
96297dab MK	157	int num_xmm_regs;
8201327c	158
c131fcee	159	/* Bits of the extended control register 0 (the XFEATURE_ENABLED_MASK
1777feb0 MS	160	register), excluding the x87 bit, which are supported by this GDB. */
1777feb0 MS	161
c131fcee L	162	uint64_t xcr0;
	163
	164	/* Offset of XCR0 in XSAVE extended state. */
	165	int xsave_xcr0_offset;
	166
90884b2b L	167	/* Register names. */
	168	const char **register_names;
	169
c131fcee L	170	/* Register number for %ymm0h. Set this to -1 to indicate the absence
	171	of upper YMM register support. */
	172	int ymm0h_regnum;
	173
	174	/* Upper YMM register names. Only used for tdesc_numbered_register. */
	175	const char **ymmh_register_names;
	176
90884b2b L	177	/* Target description. */
	178	const struct target_desc *tdesc;
	179
	180	/* Register group function. */
	181	const void *register_reggroup_p;
	182
8201327c MK	183	/* Offset of saved PC in jmp_buf. */
	184	int jb_pc_offset;
	185
	186	/* Convention for returning structures. */
	187	enum struct_return struct_return;
	188
8201327c MK	189	/* Address range where sigtramp lives. */
	190	CORE_ADDR sigtramp_start;
	191	CORE_ADDR sigtramp_end;
	192
911bc6ee MK	193	/* Detect sigtramp. */
	194	int (sigtramp_p) (struct frame_info );
	195
21d0e8a4 MK	196	/* Get address of sigcontext for sigtramp. */
	197	CORE_ADDR (sigcontext_addr) (struct frame_info );
	198
a3386186 MK	199	/* Offset of registers in `struct sigcontext'. */
	200	int *sc_reg_offset;
	201	int sc_num_regs;
	202
	203	/* Offset of saved PC and SP in `struct sigcontext'. Usage of these
	204	is deprecated, please use `sc_reg_offset' instead. */
8201327c	205	int sc_pc_offset;
21d0e8a4	206	int sc_sp_offset;
794ac428 UW	207
	208	/* ISA-specific data types. */
	209	struct type *i386_mmx_type;
c131fcee	210	struct type *i386_ymm_type;
27067745	211	struct type *i387_ext_type;
7ad10968 HZ	212
7ad10968 HZ	213	/* Process record/replay target. */
cf648174 HZ	214	/* The map for registers because the AMD64's registers order
	215	in GDB is not same as I386 instructions. */
	216	const int *record_regmap;
7ad10968 HZ	217	/* Parse intx80 args. */
	218	int (i386_intx80_record) (struct regcache regcache);
	219	/* Parse sysenter args. */
	220	int (i386_sysenter_record) (struct regcache regcache);
cf648174 HZ	221	/* Parse syscall args. */
cf648174 HZ	222	int (i386_syscall_record) (struct regcache regcache);
96297dab MK	223	};
	224
	225	/* Floating-point registers. */
	226
96297dab MK	227	/* All FPU control regusters (except for FIOFF and FOOFF) are 16-bit
	228	(at most) in the FPU, but are zero-extended to 32 bits in GDB's
	229	register cache. */
	230
23a34459 AC	231	/* Return non-zero if REGNUM matches the FP register and the FP
23a34459 AC	232	register set is active. */
20a6ec49 MD	233	extern int i386_fp_regnum_p (struct gdbarch *, int);
20a6ec49 MD	234	extern int i386_fpc_regnum_p (struct gdbarch *, int);
96297dab	235
a3386186 MK	236	/* Register numbers of various important registers. */
a3386186 MK	237
bcf48cc7 MK	238	enum i386_regnum
	239	{
	240	I386_EAX_REGNUM, /* %eax */
	241	I386_ECX_REGNUM, /* %ecx */
	242	I386_EDX_REGNUM, /* %edx */
	243	I386_EBX_REGNUM, /* %ebx */
	244	I386_ESP_REGNUM, /* %esp */
	245	I386_EBP_REGNUM, /* %ebp */
	246	I386_ESI_REGNUM, /* %esi */
	247	I386_EDI_REGNUM, /* %edi */
	248	I386_EIP_REGNUM, /* %eip */
	249	I386_EFLAGS_REGNUM, /* %eflags */
2666fb59 MK	250	I386_CS_REGNUM, /* %cs */
2666fb59 MK	251	I386_SS_REGNUM, /* %ss */
e9ff708b AC	252	I386_DS_REGNUM, /* %ds */
	253	I386_ES_REGNUM, /* %es */
	254	I386_FS_REGNUM, /* %fs */
	255	I386_GS_REGNUM, /* %gs */
90884b2b	256	I386_ST0_REGNUM, /* %st(0) */
c131fcee L	257	I386_MXCSR_REGNUM = 40, /* %mxcsr */
	258	I386_YMM0H_REGNUM, /* %ymm0h */
	259	I386_YMM7H_REGNUM = I386_YMM0H_REGNUM + 7
bcf48cc7	260	};
a3386186	261
cf648174 HZ	262	/* Register numbers of RECORD_REGMAP. */
	263
	264	enum record_i386_regnum
	265	{
	266	X86_RECORD_REAX_REGNUM,
	267	X86_RECORD_RECX_REGNUM,
	268	X86_RECORD_REDX_REGNUM,
	269	X86_RECORD_REBX_REGNUM,
	270	X86_RECORD_RESP_REGNUM,
	271	X86_RECORD_REBP_REGNUM,
	272	X86_RECORD_RESI_REGNUM,
	273	X86_RECORD_REDI_REGNUM,
	274	X86_RECORD_R8_REGNUM,
	275	X86_RECORD_R9_REGNUM,
	276	X86_RECORD_R10_REGNUM,
	277	X86_RECORD_R11_REGNUM,
	278	X86_RECORD_R12_REGNUM,
	279	X86_RECORD_R13_REGNUM,
	280	X86_RECORD_R14_REGNUM,
	281	X86_RECORD_R15_REGNUM,
	282	X86_RECORD_REIP_REGNUM,
	283	X86_RECORD_EFLAGS_REGNUM,
	284	X86_RECORD_CS_REGNUM,
	285	X86_RECORD_SS_REGNUM,
	286	X86_RECORD_DS_REGNUM,
	287	X86_RECORD_ES_REGNUM,
	288	X86_RECORD_FS_REGNUM,
	289	X86_RECORD_GS_REGNUM,
	290	};
	291
8201327c	292	#define I386_NUM_GREGS 16
8201327c MK	293	#define I386_NUM_XREGS 9
8201327c MK	294
90884b2b	295	#define I386_SSE_NUM_REGS (I386_MXCSR_REGNUM + 1)
c131fcee	296	#define I386_AVX_NUM_REGS (I386_YMM7H_REGNUM + 1)
8201327c	297
00f8375e MK	298	/* Size of the largest register. */
	299	#define I386_MAX_REGISTER_SIZE 16
	300
5ae96ec1	301	/* Types for i386-specific registers. */
27067745	302	extern struct type i387_ext_type (struct gdbarch gdbarch);
794ac428	303
1ba53b71 L	304	/* Checks of different pseudo-registers. */
	305	extern int i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum);
	306	extern int i386_word_regnum_p (struct gdbarch *gdbarch, int regnum);
	307	extern int i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee L	308	extern int i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum);
c131fcee L	309	extern int i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum);
1ba53b71 L	310
	311	extern const char i386_pseudo_register_name (struct gdbarch gdbarch,
	312	int regnum);
	313
	314	extern void i386_pseudo_register_read (struct gdbarch *gdbarch,
	315	struct regcache *regcache,
	316	int regnum, gdb_byte *buf);
	317	extern void i386_pseudo_register_write (struct gdbarch *gdbarch,
	318	struct regcache *regcache,
	319	int regnum, const gdb_byte *buf);
	320
508fbfea MK	321	/* Segment selectors. */
508fbfea MK	322	#define I386_SEL_RPL 0x0003 /* Requester's Privilege Level mask. */
1777feb0 MS	323	#define I386_SEL_UPL 0x0003 /* User Privilige Level. */
1777feb0 MS	324	#define I386_SEL_KPL 0x0000 /* Kernel Privilige Level. */
508fbfea	325
237fc4c9 PA	326	/* The length of the longest i386 instruction (according to
	327	include/asm-i386/kprobes.h in Linux 2.6. */
	328	#define I386_MAX_INSN_LEN (16)
	329
1cce71eb	330	/* Functions exported from i386-tdep.c. */
e17a4113 UW	331	extern CORE_ADDR i386_pe_skip_trampoline_code (struct frame_info *frame,
e17a4113 UW	332	CORE_ADDR pc, char *name);
1777feb0 MS	333	extern CORE_ADDR i386_skip_main_prologue (struct gdbarch *gdbarch,
1777feb0 MS	334	CORE_ADDR pc);
1cce71eb	335
4bd207ef TG	336	/* Return whether the THIS_FRAME corresponds to a sigtramp routine. */
	337	extern int i386_sigtramp_p (struct frame_info *this_frame);
	338
38c968cf AC	339	/* Return non-zero if REGNUM is a member of the specified group. */
	340	extern int i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
	341	struct reggroup *group);
	342
20187ed5 MK	343	/* Supply register REGNUM from the general-purpose register set REGSET
	344	to register cache REGCACHE. If REGNUM is -1, do this for all
	345	registers in REGSET. */
	346	extern void i386_supply_gregset (const struct regset *regset,
	347	struct regcache *regcache, int regnum,
	348	const void *gregs, size_t len);
3d171c85 MK	349
	350	/* Collect register REGNUM from the register cache REGCACHE and store
	351	it in the buffer specified by GREGS and LEN as described by the
	352	general-purpose register set REGSET. If REGNUM is -1, do this for
	353	all registers in REGSET. */
	354	extern void i386_collect_gregset (const struct regset *regset,
	355	const struct regcache *regcache,
	356	int regnum, void *gregs, size_t len);
20187ed5	357
8446b36a MK	358	/* Return the appropriate register set for the core section identified
	359	by SECT_NAME and SECT_SIZE. */
	360	extern const struct regset *
	361	i386_regset_from_core_section (struct gdbarch *gdbarch,
	362	const char *sect_name, size_t sect_size);
	363
237fc4c9	364
b55078be DE	365	extern struct displaced_step_closure *i386_displaced_step_copy_insn
	366	(struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to,
	367	struct regcache *regs);
237fc4c9 PA	368	extern void i386_displaced_step_fixup (struct gdbarch *gdbarch,
	369	struct displaced_step_closure *closure,
	370	CORE_ADDR from, CORE_ADDR to,
	371	struct regcache *regs);
	372
8201327c MK	373	/* Initialize a basic ELF architecture variant. */
	374	extern void i386_elf_init_abi (struct gdbarch_info, struct gdbarch *);
	375
	376	/* Initialize a SVR4 architecture variant. */
	377	extern void i386_svr4_init_abi (struct gdbarch_info, struct gdbarch *);
a6b808b4 HZ	378
	379	extern int i386_process_record (struct gdbarch *gdbarch,
	380	struct regcache *regcache, CORE_ADDR addr);
de0b6abb	381	\f
8201327c	382
de0b6abb	383	/* Functions and variables exported from i386bsd-tdep.c. */
8201327c	384
3cac699e	385	extern void i386bsd_init_abi (struct gdbarch_info, struct gdbarch *);
5d93ae8c MK	386	extern CORE_ADDR i386fbsd_sigtramp_start_addr;
	387	extern CORE_ADDR i386fbsd_sigtramp_end_addr;
	388	extern CORE_ADDR i386obsd_sigtramp_start_addr;
	389	extern CORE_ADDR i386obsd_sigtramp_end_addr;
de0b6abb MK	390	extern int i386fbsd4_sc_reg_offset[];
	391	extern int i386fbsd_sc_reg_offset[];
	392	extern int i386nbsd_sc_reg_offset[];
	393	extern int i386obsd_sc_reg_offset[];
	394	extern int i386bsd_sc_reg_offset[];
3ce1502b	395
96297dab	396	#endif /* i386-tdep.h */