Disable all level shifters before enabling
the PS-to-PL level shifters as it would
be good to disable all level shifters before
enabling the PS-to-PL in order to ensure that
it is in proper state
We are about to change the location for ps7_init files, breaking the
current work-flows. It is good time to drop the legacy ps7_init.c/h
support.
Going forward, please use ps7_init_gpl.c/h all the time.
If you are still using old Xilinx tools that are only able to
generate ps7_init.c/h, rename them into ps7_init_gpl.c/h.
The PicoZed is a System-on-Module board which is marketed as part of
the ZedBoard/MicroZed/etc. collection. It includes a Zynq-7000
processor.
This patch adds support that covers all the variants of the PicoZed
including the SKUs with Z7010/Z7020 and Z7015/Z7030 Zynq chips. This
patch set however only covers support for the System-on-Module and does
not cover any extra components that are available on carrier boards
(except those that are fanned out of the module itself).
More information on this board, its variants and available carrier
boards is available at: http://zedboard.org/product/picozed
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
=> sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe00000
=> sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Bin Meng [Fri, 24 Apr 2015 11:51:10 +0000 (19:51 +0800)]
dm: sf: Make SST flash write op work again
With SPI flash moving to driver model, commit fbb0991 "dm: Convert
spi_flash_probe() and 'sf probe' to use driver model" ignored the
SST flash-specific write op (byte program & word program), which
actually broke the SST flash from wroking.
This commit makes SST flash work again under driver model, by adding
SST flash-specific handling in the spi_flash_std_write().
MIPS: implement device-tree handover to Linux kernel
Add device-tree handover to Linux kernel conforming with MIPS UHI [1].
Register $a0 will be set to the reserved value -2. The address of
the device-tree blob will be stored as KSEG0 address in $a1. $a2 and
$a3 are set to zero.
Hans de Goede [Mon, 20 Apr 2015 09:13:37 +0000 (11:13 +0200)]
fdt: Fix handling of paths with options in them
After syncing the sunxi dts files with the upstream kernel dm/fdt sunxi
builds would no longer boot.
The problem is that stdout-path is now set like this in the upstream dts
files: stdout-path = "serial0:115200n8". The use of options in of-paths,
either after an alias name, or after a full path, e.g. stdout-path =
"/soc@01c00000/serial@01c28000:115200", is standard of usage, but something
which the u-boot dts code so far did not handle.
This commit fixes this, adding support for both path formats.
Scott Wood [Tue, 24 Mar 2015 20:25:03 +0000 (13:25 -0700)]
armv8/ls2085ardb: Enable NAND SPL support
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.
Jaiprakash Singh [Sat, 21 Mar 2015 02:28:27 +0000 (19:28 -0700)]
driver/ifc: Add 64KB page support
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic functionality.
RUNTIME registers are defined in PAGE1 and controls NAND and
GPCM funcinality.
FCM and RUNTIME structures defination is common for IFC
version 1.4 and 2.0.
ARM: vf610: Initial integration for Colibri VF50/VF61
This adds initial support for Colibri VF50/VF61 based on Freescale
Vybrid SoC.
- CPU clocked at 396/500 MHz
- DDR3 at 396MHz
- for VF50, use PLL2 as memory clock (synchronous mode)
- for VF61, use PLL1 as memory clock (asynchronous mode)
- Console on UART0 (Colibri UART_A)
- Ethernet on FEC1
- PLL5 based RMII clocking (E.g. No external crystal)
- UART_A and UART_C I/O muxing
- Boot from NAND by default
Tested on Colibri VF50/VF61 booting using serial loader over UART.
Vybrid product family consists of several rather similar SoC which
can be determined by softare during boot time. This allows use of
variable ${soc} for Linux device tree files. Detect VF5xx CPU's by
reading the CPU count register. We can determine the second number
of the CPU type (VF6x0) which indicates the presence of a L2 cache.
ARM: vf610: Move DDR3 initialization to imx-common
In order to avoid code duplication, move the DDR3 initialization to the
common place under imx-common. Currently ROW_DIFF and COL_DIFF can be
chosen from the board file. The JEDEC timings are specified using a
common ddr3_jedec_timings structure.
Marek Vasut [Thu, 9 Apr 2015 23:11:54 +0000 (01:11 +0200)]
rtc: Set valid date after reset
Some RTC chips tend to set garbage date after reset.
This patch sets the date to 2000-01-01 00:00 immediatelly
after the RTC chip reset is issued using the "date reset"
command.
Dileep Katta [Fri, 27 Mar 2015 17:36:57 +0000 (23:06 +0530)]
fastboot: ARM: OMAP5: Enable reboot-bootloader
Implemented fb_set_reboot_flag() for OMAP5 to set
an environment variable 'dofastboot' when reboot-bootloader called.
This environment variable will be checked in boot command and fastboot
will be called if the variable is set.
If the bootcmd env variable of OMAP5 common is overwritten with board-specific
command, then these changes will not apply.
This was originally intended for DRA7 platform, but now applies to all OMAP5.
patman: check git format.subjectprefix setting when generate patches prefix
For the local project, we may specified format.subjectprefix setting.
Then the patch will be formated as [Project_prefix][PATCH].
But patman will not check this setting. It will remove the
format.subjectprefix.
So This patch will let patman check this setting and add it as a
project prefix.
Dileep Katta [Tue, 24 Mar 2015 22:34:50 +0000 (04:04 +0530)]
ARM: DRA7XX: Enable Fastboot
- Fastboot is enable by default for DRA7XX
- This is based on following patch modified accordingly
http://git.omapzoom.org/?p=repo/u-boot.git;a=commit;h=b2e04f92b5d91c708b6fd6b79d2266966ac51f4b
Xiang Wang [Mon, 23 Mar 2015 22:56:58 +0000 (17:56 -0500)]
gpio: mvmfp: support newer MFP bit definitions
1. The bits 11..10 for mfp driver strength is only valid for
aspen and old xscale family, for newer Marvell chip, this range
has been moved to 12..11.
2. add sleep bit support
Peter Howard [Sun, 22 Mar 2015 22:19:56 +0000 (09:19 +1100)]
davinci: add support for omapl138-lcdk board
Signed-off-by: Peter Howard <[email protected]>
[trini: Add config file, update for ..._ether_addr() -> ..._ethaddr() rename] Signed-off-by: Tom Rini <[email protected]>
driver/ldpaa: Add support of WRIOP static data structure
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.
Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.
Shaohui Xie [Sat, 21 Mar 2015 02:28:19 +0000 (19:28 -0700)]
net/memac_phy: reuse driver for little endian SoCs
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoCs, if the CONFIG_SYS_MEMAC_LITTLE_ENDIAN is defined, the I/O access
is little endian, if not, the I/O access is big endian. Move fsl_memac.h
out of powerpc include.
J. German Rivera [Sat, 21 Mar 2015 02:28:18 +0000 (19:28 -0700)]
drivers/fsl-mc: Changed MC firmware loading for new boot architecture
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
flib functions.
Minghuan Lian [Sat, 21 Mar 2015 02:28:16 +0000 (19:28 -0700)]
armv8: Add SerDes framework for Layerscape Architecture
Add support of SerDes framework for Layerscape Architecture.
- Add support of 2 SerDes block
- Add SerDes protocol parsing and detection
- Create table of SerDes protocol supported by LS2085A
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
net_dev->state is set as ETH_STATE_INIT So take care net_dev->state as
ETH_STATE_INIT in ldpaa_eth_stop.
Undef CONFIG_PHYLIB temorarily because ldpaa_eth driver currently does
not support PHYLIB.
Instead of clearing pull descriptor one time, clear it before issuing any
volatile dequeue command.
Volatile command does not return frame immidiately, wait till a frame
is available in DQRR. This frame can be valid or expired.
Flush buffer before releasing to BMan ensure the core does not have any
cachelines that the WRIOP will DMA to.
York Sun [Sat, 21 Mar 2015 02:28:11 +0000 (19:28 -0700)]
armv8/fsl-lsch3: Update early MMU table
During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.
Cache was enabled for entire IFC space before. Actually the first two
entries are big enough (4MB) to cover the boot code and environmental
variables. Remove extra entries. Move OCRAM entry out of ifdef.
York Sun [Sat, 21 Mar 2015 02:28:08 +0000 (19:28 -0700)]
armv8/ls2085a: Fix generic timer clock source
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
ls2085a_common.h contains hard-coded information for NOR/NAND flash,
I2C, DDR, etc. These are platform specific. Move them out of common
header file and placed into respective board header files.
Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector
size.
Enable command auto complete. Update prompt symbol. Set fdt_high to
0xa0000000 because Linux requires that the fdt be 8-byte aligned
and below 512 MiB. Besides ensuring compliance with the 512 MiB
limit, this avoids problems with the dtb being misaligned within
the FIT image.
Change the MC FW, MC DPL and Debug server NOR addresses in compliance
with the NOR flash layouts for 128MB flash.
Add PCIe macros. Enable "loadb" command. Disable debug server.
Enable workaround for erratum A008511.
Stop reset on panic for postmortem debugging.
York Sun [Thu, 19 Mar 2015 16:30:29 +0000 (09:30 -0700)]
driver/ddr/fsl: Add workaround for DDR erratum A008511
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.
York Sun [Thu, 19 Mar 2015 16:30:28 +0000 (09:30 -0700)]
driver/ddr/fsl: Add built-in memory test for DDR4 driver
Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.
York Sun [Thu, 19 Mar 2015 16:30:27 +0000 (09:30 -0700)]
driver/ddr/fsl: Fix driver to support empty first slot
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.
York Sun [Thu, 19 Mar 2015 16:30:26 +0000 (09:30 -0700)]
drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.
York Sun [Fri, 20 Mar 2015 17:20:40 +0000 (10:20 -0700)]
driver/i2c/mxc: Enable I2C bus 3 and 4
Some SoCs have more than two I2C busses. Instead of adding ifdef
to the driver, macros are put into board header file where
CONFIG_SYS_I2C_MXC is defined.
driver/fsl_ifc: Add support to finalize CS1, CS3 address binding
For fsl-lsch3, IFC is binded with address within 32-bit at fist.
After u-boot relocates to DDR, CS1, CS3 can be binded to higher
address to support large space.
Simon Glass [Sat, 28 Feb 2015 05:06:38 +0000 (22:06 -0700)]
fdt: Add an option to disable device tree in SPL
Some boards cannot support device tree due to lack of memory. Add an option
to allow these boards to continue to work (and even use driver model).
This is a 'negative' option since most boards are expected to support device
tree in SPL.
Simon Glass [Sat, 28 Feb 2015 05:06:33 +0000 (22:06 -0700)]
dm: core: Drop device removal error path when not supported
When CONFIG_DM_DEVICE_REMOVE is not enabled, such as in SPL, we cannot
remove or unbind devices and do not expect to get errors when binding
and probing devices. So drop the error path to reduce code size.
Simon Glass [Sat, 28 Feb 2015 05:06:32 +0000 (22:06 -0700)]
dm: Add a panic_str() function to reduce code size
The printf() in panic() adds about 1.5KB of code size to SPL when compiled
with Thumb-2. Provide a smaller version that does not support printf()-style
arguments and use it in two commonly compiled places.
Simon Glass [Sat, 28 Feb 2015 05:06:31 +0000 (22:06 -0700)]
dm: core: Remove unbind operations when not required
The CONFIG_DM_DEVICE_REMOVE option takes out code related to removing
devices. It should also remove the 'unbind' code since if we cannot
remove we probably don't need to unbind.
Simon Glass [Sat, 28 Feb 2015 05:06:30 +0000 (22:06 -0700)]
dm: core: Allow sequence alias support to be removed for SPL
In many cases SPL only uses a single serial port and there is no need for
alias sequence support. We will just use the serial port pointed to by
stdout-path in the /chosen node.
Stefan Roese [Wed, 11 Mar 2015 08:51:39 +0000 (09:51 +0100)]
cmd_led: Extend led command to support blinking and more leds
This patch extends the U-Boot "led" command to support automatic blinking
by setting a blink frequency in milliseconds. Additionally the number of
supported LEDs is increased to 6 (0...5).
This assignment conflicts with code that add flags with
gd->flags |= FOO prior to the execution of this function.
Seems like a historical artifact and creates bugs with
early alloc().
ARM: integrator: move board select into mach-integrator/Kconfig
The board/SoC select menu in arch/arm/Kconfig is still cluttered.
Add ARCH_INTEGRATOR into arch/arm/Kconfig and move the board select
under arch/arm/mach-integrator.
These is a growing trend to license DT files dual GPL and X11
especially in the Linux community. It allows easier reuse of
device trees for other software projects.
This commit prepares for doing so in U-Boot too, since DT files are
often copied from the kernel to U-Boot.
Commit d8bafe1310487ba0e0785997726b4792072178d3
"ARMv8: enable DM in vexpress64 board" only enabled DM
for the simulated vexpress64 board (FVP) with the
hardcoded clock value for the simulated board, causing
a console regression on the Juno board which was using
a different clock setting.
Fix this by enabling DM for all vexpress64 boards,
defining the clock frequency per-board, deleting the
static array of PL01x ports from the config file and
relying solely on the port defined in the boardfile
using platform data.
projects / J-u-boot.git / log