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armv7: stronger barrier for cache-maintenance operations
authorAneesh V <[email protected]>
Thu, 11 Aug 2011 04:35:44 +0000 (04:35 +0000)
committerAlbert ARIBAUD <[email protected]>
Sun, 4 Sep 2011 09:36:16 +0000 (11:36 +0200)
commit882f80b993f3719cce5bfa7f1bca9b1b23062b5f
treeba83eab86729a1871261d10512178ccc1d2c9a65tree | snapshot
parent13d4f9bd7477b3b409f3e267b3b3d6fed5bd3e30commit | diff
armv7: stronger barrier for cache-maintenance operations

set-way operations need a DSB after them to ensure the
operation is complete. DMB may not be enough. Use DSB
after all operations instead of DMB.

Signed-off-by: Aneesh V <[email protected]>
arch/arm/cpu/armv7/cache_v7.c diff | blob | blame | history
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