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riscv: cpu: check U-Mode before counteren write
authorNikita Shubin <[email protected]>
Wed, 14 Dec 2022 05:58:43 +0000 (08:58 +0300)
committerLeo Yu-Chi Liang <[email protected]>
Wed, 1 Feb 2023 08:17:13 +0000 (16:17 +0800)
commit81b56a55c21cf3de3e8faa4de3830a9036bf3e5c
tree71fa3178e46d5e00e95163f4409cbdca4ee093b8tree | snapshot
parent73a3f5139182a0389d505bf29b0ad4bc29424cf8commit | diff
riscv: cpu: check U-Mode before counteren write

The Priv ISA states:
"In systems without U-mode, the mcounteren register should
not exist."

Check U-Mode is present in MISA before writing to counteren, otherwise
we endup with Illegal Instruction exception on systems without U-Mode.

Also make checking MISA default for M-Mode.

Signed-off-by: Nikita Shubin <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
arch/riscv/cpu/cpu.c diff | blob | blame | history
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