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pcie: designware: mvebu: fix reset release polarity
authorBaruch Siach <[email protected]>
Sun, 3 Feb 2019 13:15:39 +0000 (15:15 +0200)
committerStefan Roese <[email protected]>
Mon, 11 Feb 2019 08:39:12 +0000 (09:39 +0100)
commit6664a0e5f3694592966c92ec4a0547ad77b84a9a
treebd87330a44eaac35afa15e14906d6bfc0f1d016atree | snapshot
parentf301ba55c877707e15378401247cc828740ba00ecommit | diff
pcie: designware: mvebu: fix reset release polarity

The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.

Reported-by: Sven Auhagen <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
drivers/pci/pcie_dw_mvebu.c diff | blob | blame | history
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