X-Git-Url: https://repo.jachan.dev/J-u-boot.git/blobdiff_plain/efb5dab7ba8a9a6f89e44c4e60b0adb768c77e84..f9147d636ce26eec8719ce8167887736c321ef94:/include/configs/ls1046ardb.h diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 4a657533ef8..f6ff6903292 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -9,48 +9,21 @@ #include "ls1046a_common.h" -#define CONFIG_SYS_CLK_FREQ 100000000 - #define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 #define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg -#ifdef CONFIG_EMMC_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg -#endif -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg +#if defined(CONFIG_QSPI_BOOT) #define CONFIG_SYS_UBOOT_BASE 0x40100000 #define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 #endif -#ifndef SPL_NO_IFC -/* IFC */ -#define CONFIG_FSL_IFC -/* - * NAND Flash Definitions - */ -#define CONFIG_NAND_FSL_IFC -#endif - #define CONFIG_SYS_NAND_BASE 0x7e800000 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE @@ -68,8 +41,6 @@ | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ FTIM0_NAND_TWP(0x18) | \ FTIM0_NAND_TWCHT(0x7) | \ @@ -87,8 +58,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - /* * CPLD */ @@ -139,10 +108,6 @@ #define I2C_RETIMER_ADDR 0x18 /* PMIC */ -#define CONFIG_POWER -#ifdef CONFIG_POWER -#define CONFIG_POWER_I2C -#endif /* * Environment @@ -169,20 +134,11 @@ #endif #ifndef SPL_NO_MISC -#undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt;;" #define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ "env exists secureboot && esbc_halt;" -#else -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;;" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#endif #endif #endif