X-Git-Url: https://repo.jachan.dev/J-u-boot.git/blobdiff_plain/2cce2d32318e66e5b72b78ff99e0ccdffa12277b..b7b3b8c6a0bfc87047cb18a7abfa06fb6e9d0331:/include/configs/microblaze-generic.h diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index e20eb0849ce..bb070600021 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -3,23 +3,7 @@ * * Michal SIMEK * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -28,17 +12,24 @@ #include "../board/xilinx/microblaze-generic/xparameters.h" /* MicroBlaze CPU */ -#define CONFIG_MICROBLAZE 1 #define MICROBLAZE_V5 1 -/* linear flash memory */ +/* linear and spi flash memory */ #ifdef XILINX_FLASH_START #define FLASH +#undef SPIFLASH +#undef RAMENV /* hold environment in flash */ +#else +#ifdef XILINX_SPI_FLASH_BASEADDR +#undef FLASH +#define SPIFLASH #undef RAMENV /* hold environment in flash */ #else #undef FLASH +#undef SPIFLASH #define RAMENV /* hold environment in RAM */ #endif +#endif /* uart */ #ifdef XILINX_UARTLITE_BASEADDR @@ -74,7 +65,7 @@ /* ethernet */ #undef CONFIG_SYS_ENET -#if defined(XILINX_EMACLITE_BASEADDR) +#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL) # define CONFIG_XILINX_EMACLITE 1 # define CONFIG_SYS_ENET #endif @@ -91,34 +82,29 @@ /* gpio */ #ifdef XILINX_GPIO_BASEADDR -# define CONFIG_SYS_GPIO_0 1 +# define CONFIG_XILINX_GPIO # define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR #endif /* interrupt controller */ #ifdef XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0 1 # define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR # define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS #endif /* timer */ -#ifdef XILINX_TIMER_BASEADDR -# if (XILINX_TIMER_IRQ != -1) -# define CONFIG_SYS_TIMER_0 1 +#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) # define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -# define FREQUENCE XILINX_CLOCK_FREQ -# define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -# endif -#elif XILINX_CLOCK_FREQ -# define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ -#else -# error BAD CLOCK FREQ #endif -/* FSL */ -/* #define CONFIG_SYS_FSL_2 */ -/* #define FSL_INTR_2 1 */ + +/* watchdog */ +#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) +# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR +# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ +# define CONFIG_HW_WATCHDOG +# define CONFIG_XILINX_TB_WATCHDOG +#endif /* * memory layout - Example @@ -208,26 +194,58 @@ # define CONFIG_SYS_MAX_FLASH_SECT 512 /* hardware flash protection */ # define CONFIG_SYS_FLASH_PROTECTION - +/* use buffered writes (20x faster) */ +# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 # ifdef RAMENV # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) -# else /* !RAMENV */ +# else /* FLASH && !RAMENV */ # define CONFIG_ENV_IS_IN_FLASH 1 /* 128K(one sector) for env */ # define CONFIG_ENV_SECT_SIZE 0x20000 # define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) # define CONFIG_ENV_SIZE 0x20000 -# endif /* !RAMBOOT */ +# endif /* FLASH && !RAMBOOT */ #else /* !FLASH */ + +#ifdef SPIFLASH +# define CONFIG_SYS_NO_FLASH 1 +# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR +# define CONFIG_XILINX_SPI 1 +# define CONFIG_SPI 1 +# define CONFIG_SPI_FLASH 1 +# define CONFIG_SPI_FLASH_STMICRO 1 +# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 +# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ +# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS + +# ifdef RAMENV +# define CONFIG_ENV_IS_NOWHERE 1 +# define CONFIG_ENV_SIZE 0x1000 +# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) + +# else /* SPIFLASH && !RAMENV */ +# define CONFIG_ENV_IS_IN_SPI_FLASH 1 +# define CONFIG_ENV_SPI_MODE SPI_MODE_3 +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +/* 128K(two sectors) for env */ +# define CONFIG_ENV_SECT_SIZE 0x10000 +# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) +/* Warning: adjust the offset in respect of other flash content and size */ +# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ +# endif /* SPIFLASH && !RAMBOOT */ +#else /* !SPIFLASH */ + /* ENV in RAM */ # define CONFIG_SYS_NO_FLASH 1 # define CONFIG_ENV_IS_NOWHERE 1 # define CONFIG_ENV_SIZE 0x1000 # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) +#endif /* !SPIFLASH */ #endif /* !FLASH */ /* system ace */ @@ -252,6 +270,10 @@ # undef CONFIG_DCACHE #endif +#ifndef XILINX_DCACHE_BYTE_SIZE +#define XILINX_DCACHE_BYTE_SIZE 32768 +#endif + /* * BOOTP options */ @@ -269,6 +291,7 @@ #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL #define CONFIG_CMD_ECHO +#define CONFIG_CMD_GPIO #if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) # define CONFIG_CMD_CACHE @@ -298,6 +321,15 @@ # define CONFIG_CMD_UBI # undef CONFIG_CMD_UBIFS +# if !defined(RAMENV) +# define CONFIG_CMD_SAVEENV +# define CONFIG_CMD_SAVES +# endif + +#else +#if defined(SPIFLASH) +# define CONFIG_CMD_SF + # if !defined(RAMENV) # define CONFIG_CMD_SAVEENV # define CONFIG_CMD_SAVES @@ -309,6 +341,7 @@ # undef CONFIG_CMD_UBI # undef CONFIG_CMD_UBIFS #endif +#endif #if defined(CONFIG_CMD_JFFS2) # define CONFIG_MTD_PARTITIONS @@ -361,7 +394,6 @@ /* architecture dependent code */ #define CONFIG_SYS_USR_EXCEP /* user exception */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" @@ -369,10 +401,17 @@ "nor0=flash-0\0"\ "mtdparts=mtdparts=flash-0:"\ "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0" + "1m(romfs),1m(cramfs),-(jffs2)\0"\ + "nc=setenv stdout nc;"\ + "setenv stdin nc\0" \ + "serial=setenv stdout serial;"\ + "setenv stdin serial\0" #define CONFIG_CMDLINE_EDITING +#define CONFIG_NETCONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER @@ -402,4 +441,63 @@ # undef CONFIG_PHYLIB #endif +/* SPL part */ +#define CONFIG_CMD_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_BOARD_INIT + +#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds" + +#define CONFIG_SPL_RAM_DEVICE +#define CONFIG_SPL_NOR_SUPPORT + +/* for booting directly linux */ +#define CONFIG_SPL_OS_BOOT + +#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x60000) +#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ + 0x40000) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ + 0x1000000) + +/* SP location before relocation, must use scratch RAM */ +/* BRAM start */ +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +/* BRAM size - will be generated */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 +/* Stack pointer prior relocation, must situated at on-chip RAM */ +#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100 + +/* + * The main reason to do it in this way is that MALLOC_START + * can't be defined - common/spl/spl.c + */ +#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0) +# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \ + CONFIG_SYS_SPL_MALLOC_SIZE) +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START +#else +# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END +#endif + +/* Just for sure that there is a space for stack */ +#define CONFIG_SPL_STACK_SIZE 0x100 + +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_INIT_RAM_ADDR - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE - \ + CONFIG_SPL_STACK_SIZE) + #endif /* __CONFIG_H */