----------------------------------------------
NOR boot
- !defined(CONFIG_SYS_RAMBOOT)
+ !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
NOR boot Secure
- !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+ !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
RAMBOOT(SD, SPI & NAND boot)
defined(CONFIG_SYS_RAMBOOT)
RAMBOOT Secure (SD, SPI & NAND)
- defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
+ defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
NAND SPL BOOT
defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
1) TLB entry to overcome e500 v1/v2 debug restriction
- Location : Label "_start_e500"
+ Location : Label "_start"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
Properties : 256K, AS0, I, IPROT
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
- EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+ EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
- EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+ EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) Invalidate unproctected TLB Entries
8) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
- EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+ EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT
B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
1) TLB entry to overcome e500 v1/v2 debug restriction
- Location : Label "_start_e500"
+ Location : Label "_start"
TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
-#if defined(CONFIG_SECURE_BOOT)
- EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+#if defined(CONFIG_NXP_ESBC)
+ EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
2) TLB entry for working in AS1
Location : Label "create_init_ram_area"
TLB Entry : 15
-#if defined(CONFIG_SECURE_BOOT)
- EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW
+#if defined(CONFIG_NXP_ESBC)
+ EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Properties : 1M, AS1, I, G, IPROT
#else
EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
3) TLB entry for the stack during AS1
Location : Lable "create_init_ram_area"
TLB Entry : 14
- EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR
+ EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Properties : 16K, AS1, IPROT
4) TLB entry for CCSRBAR during AS1 execution
Location : cpu_init_early_f
TLB Entry : 13
- EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR
+ EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Properties : 1M, AS1, I, G
5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Disable : 15, 14
11) Create DDR's TLB entriy
- Location : Board_init_f -> init_func_ram -> initdram
+ Location : Board_init_f -> dram_init
TLB entry : Search free TLB entry
12) Update Flash's TLB entry
Location : Board_init_r
TLB entry : Search from TLB entries
- EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS
+ EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Properties : Board specific size, AS0, I, G, IPROT