Git Repo - J-u-boot.git/blob - include/configs/P2041RDB.h

1 /* SPDX-License-Identifier: GPL-2.0+ */

2 /*

5 */

7 /*

8 * P2041 RDB board configuration file

9 * Also supports P2040 RDB

10 */

11 #ifndef __CONFIG_H

12 #define __CONFIG_H

14 #ifdef CONFIG_RAMBOOT_PBL

15 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc

16 #endif

18 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE

19 /* Set 1M boot space */

20 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)

21 #define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \

22 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)

23 #define CFG_RESET_VECTOR_ADDRESS 0xfffffffc

24 #endif

26 /* High Level Configuration Options */

28 #ifndef CFG_RESET_VECTOR_ADDRESS

29 #define CFG_RESET_VECTOR_ADDRESS 0xeffffffc

30 #endif

32 #define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS

34 #ifndef __ASSEMBLY__

35 #include <linux/stringify.h>

36 #endif

38 /*

39 * These can be toggled for performance analysis, otherwise use default.

40 */

41 #define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E

43 #define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */

45 /*

46 * Config the L3 Cache as L3 SRAM

47 */

48 #define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE

49 #ifdef CONFIG_PHYS_64BIT

50 #define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE)

51 #else

52 #define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR

53 #endif

55 #ifdef CONFIG_PHYS_64BIT

56 #define CFG_SYS_DCSRBAR 0xf0000000

57 #define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull

58 #endif

60 /*

61 * DDR Setup

62 */

63 #define CFG_SYS_DDR_SDRAM_BASE 0x00000000

64 #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE

66 #define SPD_EEPROM_ADDRESS 0x52

67 #define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */

69 /*

70 * Local Bus Definitions

71 */

73 /* Set the local bus clock 1/8 of platform clock */

74 #define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8

76 /*

77 * This board doesn't have a promjet connector.

78 * However, it uses commone corenet board LAW and TLB.

79 * It is necessary to use the same start address with proper offset.

80 */

81 #define CFG_SYS_FLASH_BASE 0xe0000000

82 #ifdef CONFIG_PHYS_64BIT

83 #define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull

84 #else

85 #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE

86 #endif

88 #define CPLD_BASE 0xffdf0000 /* CPLD registers */

89 #ifdef CONFIG_PHYS_64BIT

90 #define CPLD_BASE_PHYS 0xfffdf0000ull

91 #else

92 #define CPLD_BASE_PHYS CPLD_BASE

93 #endif

95 #define PIXIS_LBMAP_SWITCH 7

96 #define PIXIS_LBMAP_MASK 0xf0

97 #define PIXIS_LBMAP_SHIFT 4

98 #define PIXIS_LBMAP_ALTBANK 0x40

100 /* Nand Flash */

101 #ifdef CONFIG_NAND_FSL_ELBC

102 #define CFG_SYS_NAND_BASE 0xffa00000

103 #ifdef CONFIG_PHYS_64BIT

104 #define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull

105 #else

106 #define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE

107 #endif

108

109 #define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}

110

111 /* NAND flash config */

112 #define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \

113 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \

114 | BR_PS_8 /* Port Size = 8 bit */ \

115 | BR_MS_FCM /* MSEL = FCM */ \

116 | BR_V) /* valid */

117 #define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \

118 | OR_FCM_PGS /* Large Page*/ \

119 | OR_FCM_CSCT \

120 | OR_FCM_CST \

121 | OR_FCM_CHT \

122 | OR_FCM_SCY_1 \

123 | OR_FCM_TRLX \

124 | OR_FCM_EHTR)

125 #endif /* CONFIG_NAND_FSL_ELBC */

126

127 #define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}

128

129 /* define to use L1 as initial stack */

130 #define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */

131 #ifdef CONFIG_PHYS_64BIT

132 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf

133 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR

134 /* The assembler doesn't like typecast */

135 #define CFG_SYS_INIT_RAM_ADDR_PHYS \

136 ((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \

137 CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)

138 #else

139 #define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR

140 #define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0

141 #define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS

142 #endif

143 #define CFG_SYS_INIT_RAM_SIZE 0x00004000

144

145 #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

146

147 /* Serial Port - controlled on board with jumper J8

148 * open - index 2

149 * shorted - index 1

150 */

151 #define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)

152

153 #define CFG_SYS_BAUDRATE_TABLE \

154 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

155

156 #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)

157 #define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)

158 #define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)

159 #define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)

160

161 /* I2C */

162

163 /*

164 * RapidIO

165 */

166 #define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000

167 #ifdef CONFIG_PHYS_64BIT

168 #define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull

169 #else

170 #define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000

171 #endif

172 #define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */

173

174 #define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000

175 #ifdef CONFIG_PHYS_64BIT

176 #define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull

177 #else

178 #define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000

179 #endif

180 #define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */

181

182 /*

183 * for slave u-boot IMAGE instored in master memory space,

184 * PHYS must be aligned based on the SIZE

185 */

186 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull

187 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull

188 #define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */

189 #define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull

190 /*

191 * for slave UCODE and ENV instored in master memory space,

192 * PHYS must be aligned based on the SIZE

193 */

194 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull

195 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull

196 #define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */

197

198 /* slave core release by master*/

199 #define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4

200 #define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */

201

202 /*

203 * SRIO_PCIE_BOOT - SLAVE

204 */

205 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE

206 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000

207 #define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \

208 (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)

209 #endif

210

211 /*

212 * eSPI - Enhanced SPI

213 */

214

215 /*

216 * General PCI

217 * Memory space is mapped 1-1, but I/O space must start from 0.

218 */

219

220 /* controller 1, direct to uli, tgtid 3, Base address 20000 */

221 #define CFG_SYS_PCIE1_MEM_VIRT 0x80000000

222 #define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull

223 #define CFG_SYS_PCIE1_IO_VIRT 0xf8000000

224 #define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull

225

226 /* controller 2, Slot 2, tgtid 2, Base address 201000 */

227 #define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000

228 #define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull

229 #define CFG_SYS_PCIE2_IO_VIRT 0xf8010000

230 #define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull

231

232 /* controller 3, Slot 1, tgtid 1, Base address 202000 */

233 #define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000

234 #define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull

235

236 /* Qman/Bman */

237 #define CFG_SYS_BMAN_NUM_PORTALS 10

238 #define CFG_SYS_BMAN_MEM_BASE 0xf4000000

239 #ifdef CONFIG_PHYS_64BIT

240 #define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull

241 #else

242 #define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE

243 #endif

244 #define CFG_SYS_BMAN_MEM_SIZE 0x00200000

245 #define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000

246 #define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000

247 #define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE

248 #define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)

249 #define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \

250 CFG_SYS_BMAN_CENA_SIZE)

251 #define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)

252 #define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08

253 #define CFG_SYS_QMAN_NUM_PORTALS 10

254 #define CFG_SYS_QMAN_MEM_BASE 0xf4200000

255 #ifdef CONFIG_PHYS_64BIT

256 #define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull

257 #else

258 #define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE

259 #endif

260 #define CFG_SYS_QMAN_MEM_SIZE 0x00200000

261 #define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000

262 #define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)

263 #define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \

264 CFG_SYS_QMAN_CENA_SIZE)

265 #define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)

266 #define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08

267

268 #ifdef CONFIG_FMAN_ENET

269 #define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2

270 #define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3

271 #define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4

272 #define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1

273 #define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0

274

275 #define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c

276 #define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d

277 #define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e

278 #define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f

279

280 #define CFG_SYS_FM1_10GEC1_PHY_ADDR 0

281

282 #define CFG_SYS_TBIPA_VALUE 8

283 #endif

284

285 #ifdef CONFIG_MMC

286 #define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR

287 #endif

288

289 /*

290 * Miscellaneous configurable options

291 */

292

293 /*

294 * For booting Linux, the board info and command line data

295 * have to be in the first 64 MB of memory, since this is

296 * the maximum mapped by the Linux kernel during initialization.

297 */

298 #define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */

299

300 /*

301 * Environment Configuration

302 */

303

304 #define __USB_PHY_TYPE utmi

305

306 #define CFG_EXTRA_ENV_SETTINGS \

307 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \

308 "bank_intlv=cs0_cs1\0" \

309 "netdev=eth0\0" \

310 "uboot=" CONFIG_UBOOTPATH "\0" \

311 "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \

312 "tftpflash=tftpboot $loadaddr $uboot && " \

313 "protect off $ubootaddr +$filesize && " \

314 "erase $ubootaddr +$filesize && " \

315 "cp.b $loadaddr $ubootaddr $filesize && " \

316 "protect on $ubootaddr +$filesize && " \

317 "cmp.b $loadaddr $ubootaddr $filesize\0" \

318 "consoledev=ttyS0\0" \

319 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \

320 "usb_dr_mode=host\0" \

321 "ramdiskaddr=2000000\0" \

322 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \

323 "fdtaddr=1e00000\0" \

324 "fdtfile=p2041rdb/p2041rdb.dtb\0" \

325 "bdev=sda3\0"

326

327 #include <asm/fsl_secure_boot.h>

328

329 #endif /* __CONFIG_H */