1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018 Intel Corporation <www.intel.com>
10 #include <asm/arch/mailbox_s10.h>
11 #include <asm/arch/smc_api.h>
12 #include <linux/delay.h>
13 #include <linux/intel-smc.h>
15 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS 60000
16 #define RECONFIG_STATUS_INTERVAL_DELAY_US 1000000
18 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
20 #define BITSTREAM_CHUNK_SIZE 0xFFFF0
21 #define RECONFIG_STATUS_POLL_RETRY_MAX 100
24 * Polling the FPGA configuration status.
25 * Return 0 for success, non-zero for error.
27 static int reconfig_status_polling_resp(void)
30 unsigned long start = get_timer(0);
33 ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
37 return 0; /* configuration success */
39 if (ret != INTEL_SIP_SMC_STATUS_BUSY)
42 if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
43 return -ETIMEDOUT; /* time out */
46 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
53 static int send_bitstream(const void *rbf_data, size_t rbf_size)
59 int ret, wr_ret = 0, retry = 0;
60 size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
61 BITSTREAM_CHUNK_SIZE : rbf_size;
63 while (rbf_size || xfer_count) {
64 if (!wr_ret && rbf_size) {
65 args[0] = (u64)rbf_data;
67 wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
70 debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
71 wr_ret, rbf_data, buf_size);
79 if (buf_size >= rbf_size)
86 INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
87 NULL, 0, res_buf, ARRAY_SIZE(res_buf));
89 for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
97 INTEL_SIP_SMC_STATUS_BUSY)
100 return INTEL_SIP_SMC_STATUS_ERROR;
102 if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
114 * This is the interface used by FPGA driver.
115 * Return 0 for success, non-zero for error.
117 int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
122 debug("Invoking FPGA_CONFIG_START...\n");
124 ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
127 puts("Failure in RECONFIG mailbox command!\n");
131 ret = send_bitstream(rbf_data, rbf_size);
133 puts("Error sending bitstream!\n");
137 /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
138 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
140 debug("Polling with MBOX_RECONFIG_STATUS...\n");
141 ret = reconfig_status_polling_resp();
143 puts("FPGA reconfiguration failed!");
147 puts("FPGA reconfiguration OK!\n");
154 static const struct mbox_cfgstat_state {
156 const char *error_name;
157 } mbox_cfgstat_state[] = {
158 {MBOX_CFGSTAT_STATE_IDLE, "FPGA in idle mode."},
159 {MBOX_CFGSTAT_STATE_CONFIG, "FPGA in config mode."},
160 {MBOX_CFGSTAT_STATE_FAILACK, "Acknowledgment failed!"},
161 {MBOX_CFGSTAT_STATE_ERROR_INVALID, "Invalid bitstream!"},
162 {MBOX_CFGSTAT_STATE_ERROR_CORRUPT, "Corrupted bitstream!"},
163 {MBOX_CFGSTAT_STATE_ERROR_AUTH, "Authentication failed!"},
164 {MBOX_CFGSTAT_STATE_ERROR_CORE_IO, "I/O error!"},
165 {MBOX_CFGSTAT_STATE_ERROR_HARDWARE, "Hardware error!"},
166 {MBOX_CFGSTAT_STATE_ERROR_FAKE, "Fake error!"},
167 {MBOX_CFGSTAT_STATE_ERROR_BOOT_INFO, "Error in boot info!"},
168 {MBOX_CFGSTAT_STATE_ERROR_QSPI_ERROR, "Error in QSPI!"},
169 {MBOX_RESP_ERROR, "Mailbox general error!"},
170 {-ETIMEDOUT, "I/O timeout error"},
171 {-1, "Unknown error!"}
174 #define MBOX_CFGSTAT_MAX ARRAY_SIZE(mbox_cfgstat_state)
176 static const char *mbox_cfgstat_to_str(int err)
180 for (i = 0; i < MBOX_CFGSTAT_MAX - 1; i++) {
181 if (mbox_cfgstat_state[i].err_no == err)
182 return mbox_cfgstat_state[i].error_name;
185 return mbox_cfgstat_state[MBOX_CFGSTAT_MAX - 1].error_name;
189 * Add the ongoing transaction's command ID into pending list and return
190 * the command ID for next transfer.
192 static u8 add_transfer(u32 *xfer_pending_list, size_t list_size, u8 id)
196 for (i = 0; i < list_size; i++) {
197 if (xfer_pending_list[i])
199 xfer_pending_list[i] = id;
200 debug("ID(%d) added to transaction pending list\n", id);
202 * Increment command ID for next transaction.
203 * Valid command ID (4 bits) is from 1 to 15.
213 * Check whether response ID match the command ID in the transfer
214 * pending list. If a match is found in the transfer pending list,
215 * it clears the transfer pending list and return the matched
218 static int get_and_clr_transfer(u32 *xfer_pending_list, size_t list_size,
223 for (i = 0; i < list_size; i++) {
224 if (id != xfer_pending_list[i])
226 xfer_pending_list[i] = 0;
234 * Polling the FPGA configuration status.
235 * Return 0 for success, non-zero for error.
237 static int reconfig_status_polling_resp(void)
240 unsigned long start = get_timer(0);
243 ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
245 return 0; /* configuration success */
247 if (ret != MBOX_CFGSTAT_STATE_CONFIG)
250 if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
251 break; /* time out */
254 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
261 static u32 get_resp_hdr(u32 *r_index, u32 *w_index, u32 *resp_count,
262 u32 *resp_buf, u32 buf_size, u32 client_id)
264 u32 buf[MBOX_RESP_BUFFER_SIZE];
270 if (*resp_count < buf_size) {
271 u32 rcv_len_max = buf_size - *resp_count;
273 if (rcv_len_max > MBOX_RESP_BUFFER_SIZE)
274 rcv_len_max = MBOX_RESP_BUFFER_SIZE;
275 resp_len = mbox_rcv_resp(buf, rcv_len_max);
277 for (i = 0; i < resp_len; i++) {
278 resp_buf[(*w_index)++] = buf[i];
279 *w_index %= buf_size;
284 /* No response in buffer */
285 if (*resp_count == 0)
288 mbox_hdr = resp_buf[*r_index];
290 hdr_len = MBOX_RESP_LEN_GET(mbox_hdr);
292 /* Insufficient header length to return a mailbox header */
293 if ((*resp_count - 1) < hdr_len)
296 *r_index += (hdr_len + 1);
297 *r_index %= buf_size;
298 *resp_count -= (hdr_len + 1);
300 /* Make sure response belongs to us */
301 if (MBOX_RESP_CLIENT_GET(mbox_hdr) != client_id)
307 /* Send bit stream data to SDM via RECONFIG_DATA mailbox command */
308 static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
309 u32 xfer_max, u32 buf_size_max)
311 u32 response_buffer[MBOX_RESP_BUFFER_SIZE];
312 u32 xfer_pending[MBOX_RESP_BUFFER_SIZE];
322 debug("SDM xfer_max = %d\n", xfer_max);
323 debug("SDM buf_size_max = %x\n\n", buf_size_max);
325 memset(xfer_pending, 0, sizeof(xfer_pending));
327 while (rbf_size || xfer_count) {
328 if (!resp_err && rbf_size && xfer_count < xfer_max) {
329 args[0] = MBOX_ARG_DESC_COUNT(1);
330 args[1] = (u64)rbf_data;
331 if (rbf_size >= buf_size_max) {
332 args[2] = buf_size_max;
333 rbf_size -= buf_size_max;
334 rbf_data += buf_size_max;
336 args[2] = (u64)rbf_size;
340 resp_err = mbox_send_cmd_only(cmd_id, MBOX_RECONFIG_DATA,
341 MBOX_CMD_INDIRECT, 3, args);
344 cmd_id = add_transfer(xfer_pending,
345 MBOX_RESP_BUFFER_SIZE,
350 u32 resp_hdr = get_resp_hdr(&resp_rindex, &resp_windex,
353 MBOX_RESP_BUFFER_SIZE,
354 MBOX_CLIENT_ID_UBOOT);
357 * If no valid response header found or
358 * non-zero length from RECONFIG_DATA
360 if (!resp_hdr || MBOX_RESP_LEN_GET(resp_hdr))
363 /* Check for response's status */
365 resp_err = MBOX_RESP_ERR_GET(resp_hdr);
366 debug("Response error code: %08x\n", resp_err);
369 ret = get_and_clr_transfer(xfer_pending,
370 MBOX_RESP_BUFFER_SIZE,
371 MBOX_RESP_ID_GET(resp_hdr));
373 /* Claim and reuse the ID */
378 if (resp_err && !xfer_count)
388 * This is the interface used by FPGA driver.
389 * Return 0 for success, non-zero for error.
391 int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
397 debug("Sending MBOX_RECONFIG...\n");
398 ret = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_RECONFIG, MBOX_CMD_DIRECT, 0,
399 NULL, 0, &resp_len, resp_buf);
401 puts("Failure in RECONFIG mailbox command!\n");
405 ret = send_reconfig_data(rbf_data, rbf_size, resp_buf[0], resp_buf[1]);
407 printf("RECONFIG_DATA error: %08x, %s\n", ret,
408 mbox_cfgstat_to_str(ret));
412 /* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
413 udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
415 debug("Polling with MBOX_RECONFIG_STATUS...\n");
416 ret = reconfig_status_polling_resp();
418 printf("RECONFIG_STATUS Error: %08x, %s\n", ret,
419 mbox_cfgstat_to_str(ret));
423 puts("FPGA reconfiguration OK!\n");