2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: BSD-3-Clause
10 #include <linux/errno.h>
11 #include <asm/arch/fpga_manager.h>
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
15 #define FPGA_TIMEOUT_CNT 0x1000000
17 static struct socfpga_fpga_manager *fpgamgr_regs =
18 (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
19 static struct socfpga_system_manager *sysmgr_regs =
20 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
23 static void fpgamgr_set_cd_ratio(unsigned long ratio)
25 clrsetbits_le32(&fpgamgr_regs->ctrl,
26 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
27 (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
30 /* Start the FPGA programming by initialize the FPGA Manager */
31 static int fpgamgr_program_init(void)
33 unsigned long msel, i;
35 /* Get the MSEL value */
36 msel = readl(&fpgamgr_regs->stat);
37 msel &= FPGAMGRREGS_STAT_MSEL_MASK;
38 msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
42 * If MSEL[3] = 1, cfg width = 32 bit
45 setbits_le32(&fpgamgr_regs->ctrl,
46 FPGAMGRREGS_CTRL_CFGWDTH_MASK);
48 /* To determine the CD ratio */
49 /* MSEL[1:0] = 0, CD Ratio = 1 */
50 if ((msel & 0x3) == 0x0)
51 fpgamgr_set_cd_ratio(CDRATIO_x1);
52 /* MSEL[1:0] = 1, CD Ratio = 4 */
53 else if ((msel & 0x3) == 0x1)
54 fpgamgr_set_cd_ratio(CDRATIO_x4);
55 /* MSEL[1:0] = 2, CD Ratio = 8 */
56 else if ((msel & 0x3) == 0x2)
57 fpgamgr_set_cd_ratio(CDRATIO_x8);
59 } else { /* MSEL[3] = 0 */
60 clrbits_le32(&fpgamgr_regs->ctrl,
61 FPGAMGRREGS_CTRL_CFGWDTH_MASK);
63 /* To determine the CD ratio */
64 /* MSEL[1:0] = 0, CD Ratio = 1 */
65 if ((msel & 0x3) == 0x0)
66 fpgamgr_set_cd_ratio(CDRATIO_x1);
67 /* MSEL[1:0] = 1, CD Ratio = 2 */
68 else if ((msel & 0x3) == 0x1)
69 fpgamgr_set_cd_ratio(CDRATIO_x2);
70 /* MSEL[1:0] = 2, CD Ratio = 4 */
71 else if ((msel & 0x3) == 0x2)
72 fpgamgr_set_cd_ratio(CDRATIO_x4);
75 /* To enable FPGA Manager configuration */
76 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
78 /* To enable FPGA Manager drive over configuration line */
79 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
81 /* Put FPGA into reset phase */
82 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
84 /* (1) wait until FPGA enter reset phase */
85 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
86 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
90 /* If not in reset state, return error */
91 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
92 puts("FPGA: Could not reset\n");
96 /* Release FPGA from reset phase */
97 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
99 /* (2) wait until FPGA enter configuration phase */
100 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
101 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
105 /* If not in configuration state, return error */
106 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
107 puts("FPGA: Could not configure\n");
111 /* Clear all interrupts in CB Monitor */
112 writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
114 /* Enable AXI configuration */
115 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
120 /* Ensure the FPGA entering config done */
121 static int fpgamgr_program_poll_cd(void)
123 const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
124 FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
125 unsigned long reg, i;
127 /* (3) wait until full config done */
128 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
129 reg = readl(&fpgamgr_regs->gpio_ext_porta);
133 printf("FPGA: Configuration error.\n");
137 /* Config done without error */
142 /* Timeout happened, return error */
143 if (i == FPGA_TIMEOUT_CNT) {
144 printf("FPGA: Timeout waiting for program.\n");
148 /* Disable AXI configuration */
149 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
154 /* Ensure the FPGA entering init phase */
155 static int fpgamgr_program_poll_initphase(void)
159 /* Additional clocks for the CB to enter initialization phase */
160 if (fpgamgr_dclkcnt_set(0x4))
163 /* (4) wait until FPGA enter init phase or user mode */
164 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
165 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
167 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
171 /* If not in configuration state, return error */
172 if (i == FPGA_TIMEOUT_CNT)
178 /* Ensure the FPGA entering user mode */
179 static int fpgamgr_program_poll_usermode(void)
183 /* Additional clocks for the CB to exit initialization phase */
184 if (fpgamgr_dclkcnt_set(0x5000))
187 /* (5) wait until FPGA enter user mode */
188 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
189 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
192 /* If not in configuration state, return error */
193 if (i == FPGA_TIMEOUT_CNT)
196 /* To release FPGA Manager drive over configuration line */
197 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
203 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
204 * Return 0 for sucess, non-zero for error.
206 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
208 unsigned long status;
210 if ((uint32_t)rbf_data & 0x3) {
211 puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
215 /* Prior programming the FPGA, all bridges need to be shut off */
217 /* Disable all signals from hps peripheral controller to fpga */
218 writel(0, &sysmgr_regs->fpgaintfgrp_module);
220 /* Disable all signals from FPGA to HPS SDRAM */
221 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
222 writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
224 /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
225 socfpga_bridges_reset(1);
227 /* Unmap the bridges from NIC-301 */
228 writel(0x1, SOCFPGA_L3REGS_ADDRESS);
230 /* Initialize the FPGA Manager */
231 status = fpgamgr_program_init();
235 /* Write the RBF data to FPGA Manager */
236 fpgamgr_program_write(rbf_data, rbf_size);
238 /* Ensure the FPGA entering config done */
239 status = fpgamgr_program_poll_cd();
243 /* Ensure the FPGA entering init phase */
244 status = fpgamgr_program_poll_initphase();
248 /* Ensure the FPGA entering user mode */
249 return fpgamgr_program_poll_usermode();