board/xilinx/zynqmp/zynqmp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2014 - 2015 Xilinx, Inc.
   4  * Michal Simek <[email protected]>
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <cpu_func.h>
  10 #include <debug_uart.h>
  11 #include <env.h>
  12 #include <init.h>
  13 #include <log.h>
  14 #include <net.h>
  15 #include <sata.h>
  16 #include <ahci.h>
  17 #include <scsi.h>
  18 #include <malloc.h>
  19 #include <wdt.h>
  20 #include <asm/arch/clk.h>
  21 #include <asm/arch/hardware.h>
  22 #include <asm/arch/sys_proto.h>
  23 #include <asm/arch/psu_init_gpl.h>
  24 #include <asm/cache.h>
  25 #include <asm/io.h>
  26 #include <asm/ptrace.h>
  27 #include <dm/device.h>
  28 #include <dm/uclass.h>
  29 #include <usb.h>
  30 #include <dwc3-uboot.h>
  31 #include <zynqmppl.h>
  32 #include <zynqmp_firmware.h>
  33 #include <g_dnl.h>
  34 #include <linux/bitops.h>
  35 #include <linux/delay.h>
  36 #include <linux/sizes.h>
  37 #include "../common/board.h"
  38
  39 #include "pm_cfg_obj.h"
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
  44     !defined(CONFIG_SPL_BUILD)
  45 static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
  46
  47 static const struct {
  48         u32 id;
  49         u32 ver;
  50         char *name;
  51         bool evexists;
  52 } zynqmp_devices[] = {
  53         {
  54                 .id = 0x10,
  55                 .name = "3eg",
  56         },
  57         {
  58                 .id = 0x10,
  59                 .ver = 0x2c,
  60                 .name = "3cg",
  61         },
  62         {
  63                 .id = 0x11,
  64                 .name = "2eg",
  65         },
  66         {
  67                 .id = 0x11,
  68                 .ver = 0x2c,
  69                 .name = "2cg",
  70         },
  71         {
  72                 .id = 0x20,
  73                 .name = "5ev",
  74                 .evexists = 1,
  75         },
  76         {
  77                 .id = 0x20,
  78                 .ver = 0x100,
  79                 .name = "5eg",
  80                 .evexists = 1,
  81         },
  82         {
  83                 .id = 0x20,
  84                 .ver = 0x12c,
  85                 .name = "5cg",
  86                 .evexists = 1,
  87         },
  88         {
  89                 .id = 0x21,
  90                 .name = "4ev",
  91                 .evexists = 1,
  92         },
  93         {
  94                 .id = 0x21,
  95                 .ver = 0x100,
  96                 .name = "4eg",
  97                 .evexists = 1,
  98         },
  99         {
 100                 .id = 0x21,
 101                 .ver = 0x12c,
 102                 .name = "4cg",
 103                 .evexists = 1,
 104         },
 105         {
 106                 .id = 0x30,
 107                 .name = "7ev",
 108                 .evexists = 1,
 109         },
 110         {
 111                 .id = 0x30,
 112                 .ver = 0x100,
 113                 .name = "7eg",
 114                 .evexists = 1,
 115         },
 116         {
 117                 .id = 0x30,
 118                 .ver = 0x12c,
 119                 .name = "7cg",
 120                 .evexists = 1,
 121         },
 122         {
 123                 .id = 0x38,
 124                 .name = "9eg",
 125         },
 126         {
 127                 .id = 0x38,
 128                 .ver = 0x2c,
 129                 .name = "9cg",
 130         },
 131         {
 132                 .id = 0x39,
 133                 .name = "6eg",
 134         },
 135         {
 136                 .id = 0x39,
 137                 .ver = 0x2c,
 138                 .name = "6cg",
 139         },
 140         {
 141                 .id = 0x40,
 142                 .name = "11eg",
 143         },
 144         { /* For testing purpose only */
 145                 .id = 0x50,
 146                 .ver = 0x2c,
 147                 .name = "15cg",
 148         },
 149         {
 150                 .id = 0x50,
 151                 .name = "15eg",
 152         },
 153         {
 154                 .id = 0x58,
 155                 .name = "19eg",
 156         },
 157         {
 158                 .id = 0x59,
 159                 .name = "17eg",
 160         },
 161         {
 162                 .id = 0x61,
 163                 .name = "21dr",
 164         },
 165         {
 166                 .id = 0x63,
 167                 .name = "23dr",
 168         },
 169         {
 170                 .id = 0x65,
 171                 .name = "25dr",
 172         },
 173         {
 174                 .id = 0x64,
 175                 .name = "27dr",
 176         },
 177         {
 178                 .id = 0x60,
 179                 .name = "28dr",
 180         },
 181         {
 182                 .id = 0x62,
 183                 .name = "29dr",
 184         },
 185         {
 186                 .id = 0x66,
 187                 .name = "39dr",
 188         },
 189         {
 190                 .id = 0x7b,
 191                 .name = "48dr",
 192         },
 193         {
 194                 .id = 0x7e,
 195                 .name = "49dr",
 196         },
 197 };
 198 #endif
 199
 200 int chip_id(unsigned char id)
 201 {
 202         struct pt_regs regs;
 203         int val = -EINVAL;
 204
 205         if (current_el() != 3) {
 206                 regs.regs[0] = ZYNQMP_SIP_SVC_CSU_DMA_CHIPID;
 207                 regs.regs[1] = 0;
 208                 regs.regs[2] = 0;
 209                 regs.regs[3] = 0;
 210
 211                 smc_call(&regs);
 212
 213                 /*
 214                  * SMC returns:
 215                  * regs[0][31:0]  = status of the operation
 216                  * regs[0][63:32] = CSU.IDCODE register
 217                  * regs[1][31:0]  = CSU.version register
 218                  * regs[1][63:32] = CSU.IDCODE2 register
 219                  */
 220                 switch (id) {
 221                 case IDCODE:
 222                         regs.regs[0] = upper_32_bits(regs.regs[0]);
 223                         regs.regs[0] &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 224                                         ZYNQMP_CSU_IDCODE_SVD_MASK;
 225                         regs.regs[0] >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 226                         val = regs.regs[0];
 227                         break;
 228                 case VERSION:
 229                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 230                         regs.regs[1] &= ZYNQMP_CSU_SILICON_VER_MASK;
 231                         val = regs.regs[1];
 232                         break;
 233                 case IDCODE2:
 234                         regs.regs[1] = lower_32_bits(regs.regs[1]);
 235                         regs.regs[1] >>= ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
 236                         val = regs.regs[1];
 237                         break;
 238                 default:
 239                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 240                 }
 241         } else {
 242                 switch (id) {
 243                 case IDCODE:
 244                         val = readl(ZYNQMP_CSU_IDCODE_ADDR);
 245                         val &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
 246                                ZYNQMP_CSU_IDCODE_SVD_MASK;
 247                         val >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT;
 248                         break;
 249                 case VERSION:
 250                         val = readl(ZYNQMP_CSU_VER_ADDR);
 251                         val &= ZYNQMP_CSU_SILICON_VER_MASK;
 252                         break;
 253                 default:
 254                         printf("%s, Invalid Req:0x%x\n", __func__, id);
 255                 }
 256         }
 257
 258         return val;
 259 }
 260
 261 #define ZYNQMP_VERSION_SIZE             9
 262 #define ZYNQMP_PL_STATUS_BIT            9
 263 #define ZYNQMP_IPDIS_VCU_BIT            8
 264 #define ZYNQMP_PL_STATUS_MASK           BIT(ZYNQMP_PL_STATUS_BIT)
 265 #define ZYNQMP_CSU_VERSION_MASK         ~(ZYNQMP_PL_STATUS_MASK)
 266 #define ZYNQMP_CSU_VCUDIS_VER_MASK      ZYNQMP_CSU_VERSION_MASK & \
 267                                         ~BIT(ZYNQMP_IPDIS_VCU_BIT)
 268 #define MAX_VARIANTS_EV                 3
 269
 270 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 271         !defined(CONFIG_SPL_BUILD)
 272 static char *zynqmp_get_silicon_idcode_name(void)
 273 {
 274         u32 i, id, ver, j;
 275         char *buf;
 276         static char name[ZYNQMP_VERSION_SIZE];
 277
 278         id = chip_id(IDCODE);
 279         ver = chip_id(IDCODE2);
 280
 281         for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
 282                 if (zynqmp_devices[i].id == id) {
 283                         if (zynqmp_devices[i].evexists &&
 284                             !(ver & ZYNQMP_PL_STATUS_MASK))
 285                                 break;
 286                         if (zynqmp_devices[i].ver == (ver &
 287                             ZYNQMP_CSU_VERSION_MASK))
 288                                 break;
 289                 }
 290         }
 291
 292         if (i >= ARRAY_SIZE(zynqmp_devices))
 293                 return "unknown";
 294
 295         strncat(name, "zu", 2);
 296         if (!zynqmp_devices[i].evexists ||
 297             (ver & ZYNQMP_PL_STATUS_MASK)) {
 298                 strncat(name, zynqmp_devices[i].name,
 299                         ZYNQMP_VERSION_SIZE - 3);
 300                 return name;
 301         }
 302
 303         /*
 304          * Here we are means, PL not powered up and ev variant
 305          * exists. So, we need to ignore VCU disable bit(8) in
 306          * version and findout if its CG or EG/EV variant.
 307          */
 308         for (j = 0; j < MAX_VARIANTS_EV; j++, i++) {
 309                 if ((zynqmp_devices[i].ver & ~BIT(ZYNQMP_IPDIS_VCU_BIT)) ==
 310                     (ver & ZYNQMP_CSU_VCUDIS_VER_MASK)) {
 311                         strncat(name, zynqmp_devices[i].name,
 312                                 ZYNQMP_VERSION_SIZE - 3);
 313                         break;
 314                 }
 315         }
 316
 317         if (j >= MAX_VARIANTS_EV)
 318                 return "unknown";
 319
 320         if (strstr(name, "eg") || strstr(name, "ev")) {
 321                 buf = strstr(name, "e");
 322                 *buf = '\0';
 323         }
 324
 325         return name;
 326 }
 327 #endif
 328
 329 int board_early_init_f(void)
 330 {
 331 #if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
 332         int ret;
 333
 334         ret = psu_init();
 335         if (ret)
 336                 return ret;
 337
 338         /* Delay is required for clocks to be propagated */
 339         udelay(1000000);
 340 #endif
 341
 342 #ifdef CONFIG_DEBUG_UART
 343         /* Uart debug for sure */
 344         debug_uart_init();
 345         puts("Debug uart enabled\n"); /* or printch() */
 346 #endif
 347
 348         return 0;
 349 }
 350
 351 static int multi_boot(void)
 352 {
 353         u32 multiboot;
 354
 355         multiboot = readl(&csu_base->multi_boot);
 356
 357         printf("Multiboot:\t%x\n", multiboot);
 358
 359         return 0;
 360 }
 361
 362 #define PS_SYSMON_ANALOG_BUS_VAL        0x3210
 363 #define PS_SYSMON_ANALOG_BUS_REG        0xFFA50914
 364
 365 int board_init(void)
 366 {
 367 #if defined(CONFIG_ZYNQMP_FIRMWARE)
 368         struct udevice *dev;
 369
 370         uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
 371         if (!dev)
 372                 panic("PMU Firmware device not found - Enable it");
 373 #endif
 374
 375 #if defined(CONFIG_SPL_BUILD)
 376         /* Check *at build time* if the filename is an non-empty string */
 377         if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
 378                 zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
 379                                                 zynqmp_pm_cfg_obj_size);
 380 #endif
 381
 382         printf("EL Level:\tEL%d\n", current_el());
 383
 384         /* Bug in ROM sets wrong value in this register */
 385         writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
 386
 387 #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \
 388     !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \
 389     defined(CONFIG_SPL_BUILD))
 390         if (current_el() != 3) {
 391                 zynqmppl.name = zynqmp_get_silicon_idcode_name();
 392                 printf("Chip ID:\t%s\n", zynqmppl.name);
 393                 fpga_init();
 394                 fpga_add(fpga_xilinx, &zynqmppl);
 395         }
 396 #endif
 397
 398         if (current_el() == 3)
 399                 multi_boot();
 400
 401         return 0;
 402 }
 403
 404 int board_early_init_r(void)
 405 {
 406         u32 val;
 407
 408         if (current_el() != 3)
 409                 return 0;
 410
 411         val = readl(&crlapb_base->timestamp_ref_ctrl);
 412         val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 413
 414         if (!val) {
 415                 val = readl(&crlapb_base->timestamp_ref_ctrl);
 416                 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
 417                 writel(val, &crlapb_base->timestamp_ref_ctrl);
 418
 419                 /* Program freq register in System counter */
 420                 writel(zynqmp_get_system_timer_freq(),
 421                        &iou_scntr_secure->base_frequency_id_register);
 422                 /* And enable system counter */
 423                 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
 424                        &iou_scntr_secure->counter_control_register);
 425         }
 426         return 0;
 427 }
 428
 429 unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
 430                          char *const argv[])
 431 {
 432         int ret = 0;
 433
 434         if (current_el() > 1) {
 435                 smp_kick_all_cpus();
 436                 dcache_disable();
 437                 armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
 438                                     ES_TO_AARCH64);
 439         } else {
 440                 printf("FAIL: current EL is not above EL1\n");
 441                 ret = EINVAL;
 442         }
 443         return ret;
 444 }
 445
 446 #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
 447 int dram_init_banksize(void)
 448 {
 449         int ret;
 450
 451         ret = fdtdec_setup_memory_banksize();
 452         if (ret)
 453                 return ret;
 454
 455         mem_map_fill();
 456
 457         return 0;
 458 }
 459
 460 int dram_init(void)
 461 {
 462         if (fdtdec_setup_mem_size_base() != 0)
 463                 return -EINVAL;
 464
 465         return 0;
 466 }
 467 #else
 468 int dram_init_banksize(void)
 469 {
 470 #if defined(CONFIG_NR_DRAM_BANKS)
 471         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 472         gd->bd->bi_dram[0].size = get_effective_memsize();
 473 #endif
 474
 475         mem_map_fill();
 476
 477         return 0;
 478 }
 479
 480 int dram_init(void)
 481 {
 482         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 483                                     CONFIG_SYS_SDRAM_SIZE);
 484
 485         return 0;
 486 }
 487 #endif
 488
 489 void reset_cpu(ulong addr)
 490 {
 491 }
 492
 493 #if defined(CONFIG_BOARD_LATE_INIT)
 494 static const struct {
 495         u32 bit;
 496         const char *name;
 497 } reset_reasons[] = {
 498         { RESET_REASON_DEBUG_SYS, "DEBUG" },
 499         { RESET_REASON_SOFT, "SOFT" },
 500         { RESET_REASON_SRST, "SRST" },
 501         { RESET_REASON_PSONLY, "PS-ONLY" },
 502         { RESET_REASON_PMU, "PMU" },
 503         { RESET_REASON_INTERNAL, "INTERNAL" },
 504         { RESET_REASON_EXTERNAL, "EXTERNAL" },
 505         {}
 506 };
 507
 508 static int reset_reason(void)
 509 {
 510         u32 reg;
 511         int i, ret;
 512         const char *reason = NULL;
 513
 514         ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, &reg);
 515         if (ret)
 516                 return -EINVAL;
 517
 518         puts("Reset reason:\t");
 519
 520         for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
 521                 if (reg & reset_reasons[i].bit) {
 522                         reason = reset_reasons[i].name;
 523                         printf("%s ", reset_reasons[i].name);
 524                         break;
 525                 }
 526         }
 527
 528         puts("\n");
 529
 530         env_set("reset_reason", reason);
 531
 532         ret = zynqmp_mmio_write((ulong)&crlapb_base->reset_reason, ~0, ~0);
 533         if (ret)
 534                 return -EINVAL;
 535
 536         return ret;
 537 }
 538
 539 static int set_fdtfile(void)
 540 {
 541         char *compatible, *fdtfile;
 542         const char *suffix = ".dtb";
 543         const char *vendor = "xilinx/";
 544
 545         if (env_get("fdtfile"))
 546                 return 0;
 547
 548         compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible", NULL);
 549         if (compatible) {
 550                 debug("Compatible: %s\n", compatible);
 551
 552                 /* Discard vendor prefix */
 553                 strsep(&compatible, ",");
 554
 555                 fdtfile = calloc(1, strlen(vendor) + strlen(compatible) +
 556                                  strlen(suffix) + 1);
 557                 if (!fdtfile)
 558                         return -ENOMEM;
 559
 560                 sprintf(fdtfile, "%s%s%s", vendor, compatible, suffix);
 561
 562                 env_set("fdtfile", fdtfile);
 563                 free(fdtfile);
 564         }
 565
 566         return 0;
 567 }
 568
 569 static u8 zynqmp_get_bootmode(void)
 570 {
 571         u8 bootmode;
 572         u32 reg = 0;
 573         int ret;
 574
 575         ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg);
 576         if (ret)
 577                 return -EINVAL;
 578
 579         if (reg >> BOOT_MODE_ALT_SHIFT)
 580                 reg >>= BOOT_MODE_ALT_SHIFT;
 581
 582         bootmode = reg & BOOT_MODES_MASK;
 583
 584         return bootmode;
 585 }
 586
 587 int board_late_init(void)
 588 {
 589         u8 bootmode;
 590         struct udevice *dev;
 591         int bootseq = -1;
 592         int bootseq_len = 0;
 593         int env_targets_len = 0;
 594         const char *mode;
 595         char *new_targets;
 596         char *env_targets;
 597         int ret;
 598
 599 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
 600         usb_ether_init();
 601 #endif
 602
 603         if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
 604                 debug("Saved variables - Skipping\n");
 605                 return 0;
 606         }
 607
 608         ret = set_fdtfile();
 609         if (ret)
 610                 return ret;
 611
 612         bootmode = zynqmp_get_bootmode();
 613
 614         puts("Bootmode: ");
 615         switch (bootmode) {
 616         case USB_MODE:
 617                 puts("USB_MODE\n");
 618                 mode = "usb";
 619                 env_set("modeboot", "usb_dfu_spl");
 620                 break;
 621         case JTAG_MODE:
 622                 puts("JTAG_MODE\n");
 623                 mode = "jtag pxe dhcp";
 624                 env_set("modeboot", "jtagboot");
 625                 break;
 626         case QSPI_MODE_24BIT:
 627         case QSPI_MODE_32BIT:
 628                 mode = "qspi0";
 629                 puts("QSPI_MODE\n");
 630                 env_set("modeboot", "qspiboot");
 631                 break;
 632         case EMMC_MODE:
 633                 puts("EMMC_MODE\n");
 634                 if (uclass_get_device_by_name(UCLASS_MMC,
 635                                               "mmc@ff160000", &dev) &&
 636                     uclass_get_device_by_name(UCLASS_MMC,
 637                                               "sdhci@ff160000", &dev)) {
 638                         puts("Boot from EMMC but without SD0 enabled!\n");
 639                         return -1;
 640                 }
 641                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 642
 643                 mode = "mmc";
 644                 bootseq = dev->seq;
 645                 break;
 646         case SD_MODE:
 647                 puts("SD_MODE\n");
 648                 if (uclass_get_device_by_name(UCLASS_MMC,
 649                                               "mmc@ff160000", &dev) &&
 650                     uclass_get_device_by_name(UCLASS_MMC,
 651                                               "sdhci@ff160000", &dev)) {
 652                         puts("Boot from SD0 but without SD0 enabled!\n");
 653                         return -1;
 654                 }
 655                 debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
 656
 657                 mode = "mmc";
 658                 bootseq = dev->seq;
 659                 env_set("modeboot", "sdboot");
 660                 break;
 661         case SD1_LSHFT_MODE:
 662                 puts("LVL_SHFT_");
 663                 /* fall through */
 664         case SD_MODE1:
 665                 puts("SD_MODE1\n");
 666                 if (uclass_get_device_by_name(UCLASS_MMC,
 667                                               "mmc@ff170000", &dev) &&
 668                     uclass_get_device_by_name(UCLASS_MMC,
 669                                               "sdhci@ff170000", &dev)) {
 670                         puts("Boot from SD1 but without SD1 enabled!\n");
 671                         return -1;
 672                 }
 673                 debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
 674
 675                 mode = "mmc";
 676                 bootseq = dev->seq;
 677                 env_set("modeboot", "sdboot");
 678                 break;
 679         case NAND_MODE:
 680                 puts("NAND_MODE\n");
 681                 mode = "nand0";
 682                 env_set("modeboot", "nandboot");
 683                 break;
 684         default:
 685                 mode = "";
 686                 printf("Invalid Boot Mode:0x%x\n", bootmode);
 687                 break;
 688         }
 689
 690         if (bootseq >= 0) {
 691                 bootseq_len = snprintf(NULL, 0, "%i", bootseq);
 692                 debug("Bootseq len: %x\n", bootseq_len);
 693         }
 694
 695         /*
 696          * One terminating char + one byte for space between mode
 697          * and default boot_targets
 698          */
 699         env_targets = env_get("boot_targets");
 700         if (env_targets)
 701                 env_targets_len = strlen(env_targets);
 702
 703         new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
 704                              bootseq_len);
 705         if (!new_targets)
 706                 return -ENOMEM;
 707
 708         if (bootseq >= 0)
 709                 sprintf(new_targets, "%s%x %s", mode, bootseq,
 710                         env_targets ? env_targets : "");
 711         else
 712                 sprintf(new_targets, "%s %s", mode,
 713                         env_targets ? env_targets : "");
 714
 715         env_set("boot_targets", new_targets);
 716
 717         reset_reason();
 718
 719         return board_late_init_xilinx();
 720 }
 721 #endif
 722
 723 int checkboard(void)
 724 {
 725         puts("Board: Xilinx ZynqMP\n");
 726         return 0;
 727 }