1 // SPDX-License-Identifier: GPL-2.0+
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
6 * Ethernet driver for H3/A64/A83T based SoC's
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
21 #include <fdt_support.h>
22 #include <dm/device_compat.h>
23 #include <linux/bitops.h>
24 #include <linux/delay.h>
25 #include <linux/err.h>
31 #include <power/regulator.h>
33 #define MDIO_CMD_MII_BUSY BIT(0)
34 #define MDIO_CMD_MII_WRITE BIT(1)
36 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
37 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
38 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
39 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
40 #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
41 #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
42 #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
43 #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
44 #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
46 #define CFG_TX_DESCR_NUM 32
47 #define CFG_RX_DESCR_NUM 32
48 #define CFG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
51 * The datasheet says that each descriptor can transfers up to 4096 bytes
52 * But later, the register documentation reduces that value to 2048,
53 * using 2048 cause strange behaviours and even BSP driver use 2047
55 #define CFG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
57 #define TX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_TX_DESCR_NUM)
58 #define RX_TOTAL_BUFSIZE (CFG_ETH_BUFSIZE * CFG_RX_DESCR_NUM)
60 #define H3_EPHY_DEFAULT_VALUE 0x58000
61 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
62 #define H3_EPHY_ADDR_SHIFT 20
63 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
64 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
65 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
66 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
68 #define SC_RMII_EN BIT(13)
69 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
70 #define SC_ETCS_MASK GENMASK(1, 0)
71 #define SC_ETCS_EXT_GMII 0x1
72 #define SC_ETCS_INT_GMII 0x2
73 #define SC_ETXDC_MASK GENMASK(12, 10)
74 #define SC_ETXDC_OFFSET 10
75 #define SC_ERXDC_MASK GENMASK(9, 5)
76 #define SC_ERXDC_OFFSET 5
78 #define CFG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
80 #define AHB_GATE_OFFSET_EPHY 0
82 /* H3/A64 EMAC Register's offset */
83 #define EMAC_CTL0 0x00
84 #define EMAC_CTL0_FULL_DUPLEX BIT(0)
85 #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
86 #define EMAC_CTL0_SPEED_10 (0x2 << 2)
87 #define EMAC_CTL0_SPEED_100 (0x3 << 2)
88 #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
89 #define EMAC_CTL1 0x04
90 #define EMAC_CTL1_SOFT_RST BIT(0)
91 #define EMAC_CTL1_BURST_LEN_SHIFT 24
92 #define EMAC_INT_STA 0x08
93 #define EMAC_INT_EN 0x0c
94 #define EMAC_TX_CTL0 0x10
95 #define EMAC_TX_CTL0_TX_EN BIT(31)
96 #define EMAC_TX_CTL1 0x14
97 #define EMAC_TX_CTL1_TX_MD BIT(1)
98 #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
99 #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
100 #define EMAC_TX_FLOW_CTL 0x1c
101 #define EMAC_TX_DMA_DESC 0x20
102 #define EMAC_RX_CTL0 0x24
103 #define EMAC_RX_CTL0_RX_EN BIT(31)
104 #define EMAC_RX_CTL1 0x28
105 #define EMAC_RX_CTL1_RX_MD BIT(1)
106 #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
107 #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
108 #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
109 #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
110 #define EMAC_RX_DMA_DESC 0x34
111 #define EMAC_MII_CMD 0x48
112 #define EMAC_MII_DATA 0x4c
113 #define EMAC_ADDR0_HIGH 0x50
114 #define EMAC_ADDR0_LOW 0x54
115 #define EMAC_TX_DMA_STA 0xb0
116 #define EMAC_TX_CUR_DESC 0xb4
117 #define EMAC_TX_CUR_BUF 0xb8
118 #define EMAC_RX_DMA_STA 0xc0
119 #define EMAC_RX_CUR_DESC 0xc4
121 #define EMAC_DESC_OWN_DMA BIT(31)
122 #define EMAC_DESC_LAST_DESC BIT(30)
123 #define EMAC_DESC_FIRST_DESC BIT(29)
124 #define EMAC_DESC_CHAIN_SECOND BIT(24)
126 #define EMAC_DESC_RX_ERROR_MASK 0x400068db
128 DECLARE_GLOBAL_DATA_PTR;
130 struct emac_variant {
132 bool soc_has_internal_phy;
136 struct emac_dma_desc {
141 } __aligned(ARCH_DMA_MINALIGN);
143 struct emac_eth_dev {
144 struct emac_dma_desc rx_chain[CFG_TX_DESCR_NUM];
145 struct emac_dma_desc tx_chain[CFG_RX_DESCR_NUM];
146 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
147 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
159 bool use_internal_phy;
161 const struct emac_variant *variant;
164 struct phy_device *phydev;
168 struct reset_ctl tx_rst;
169 struct reset_ctl ephy_rst;
170 struct gpio_desc reset_gpio;
171 struct udevice *phy_reg;
174 struct sun8i_eth_pdata {
175 struct eth_pdata eth_pdata;
181 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
183 struct udevice *dev = bus->priv;
184 struct emac_eth_dev *priv = dev_get_priv(dev);
188 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
189 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
190 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
191 MDIO_CMD_MII_PHY_ADDR_MASK;
194 * The EMAC clock is either 200 or 300 MHz, so we need a divider
195 * of 128 to get the MDIO frequency below the required 2.5 MHz.
197 if (!priv->use_internal_phy)
198 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
199 MDIO_CMD_MII_CLK_CSR_SHIFT;
201 mii_cmd |= MDIO_CMD_MII_BUSY;
203 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
205 ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
206 MDIO_CMD_MII_BUSY, false,
207 CFG_MDIO_TIMEOUT, true);
211 return readl(priv->mac_reg + EMAC_MII_DATA);
214 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
217 struct udevice *dev = bus->priv;
218 struct emac_eth_dev *priv = dev_get_priv(dev);
221 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
222 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
223 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
224 MDIO_CMD_MII_PHY_ADDR_MASK;
227 * The EMAC clock is either 200 or 300 MHz, so we need a divider
228 * of 128 to get the MDIO frequency below the required 2.5 MHz.
230 if (!priv->use_internal_phy)
231 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
232 MDIO_CMD_MII_CLK_CSR_SHIFT;
234 mii_cmd |= MDIO_CMD_MII_WRITE;
235 mii_cmd |= MDIO_CMD_MII_BUSY;
237 writel(val, priv->mac_reg + EMAC_MII_DATA);
238 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
240 return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
241 MDIO_CMD_MII_BUSY, false,
242 CFG_MDIO_TIMEOUT, true);
245 static int sun8i_eth_write_hwaddr(struct udevice *dev)
247 struct emac_eth_dev *priv = dev_get_priv(dev);
248 struct eth_pdata *pdata = dev_get_plat(dev);
249 uchar *mac_id = pdata->enetaddr;
250 u32 macid_lo, macid_hi;
252 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
254 macid_hi = mac_id[4] + (mac_id[5] << 8);
256 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
257 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
262 static void sun8i_adjust_link(struct emac_eth_dev *priv,
263 struct phy_device *phydev)
267 v = readl(priv->mac_reg + EMAC_CTL0);
270 v |= EMAC_CTL0_FULL_DUPLEX;
272 v &= ~EMAC_CTL0_FULL_DUPLEX;
274 v &= ~EMAC_CTL0_SPEED_MASK;
276 switch (phydev->speed) {
278 v |= EMAC_CTL0_SPEED_1000;
281 v |= EMAC_CTL0_SPEED_100;
284 v |= EMAC_CTL0_SPEED_10;
287 writel(v, priv->mac_reg + EMAC_CTL0);
290 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
292 if (priv->use_internal_phy) {
293 /* H3 based SoC's that has an Internal 100MBit PHY
294 * needs to be configured and powered up before use
296 reg &= ~H3_EPHY_DEFAULT_MASK;
297 reg |= H3_EPHY_DEFAULT_VALUE;
298 reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
299 reg &= ~H3_EPHY_SHUTDOWN;
300 return reg | H3_EPHY_SELECT;
303 /* This is to select External Gigabit PHY on those boards with
304 * an internal PHY. Does not hurt on other SoCs. Linux does
307 return reg & ~H3_EPHY_SELECT;
310 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
311 struct emac_eth_dev *priv)
315 reg = readl(priv->sysctl_reg);
317 reg = sun8i_emac_set_syscon_ephy(priv, reg);
319 reg &= ~(SC_ETCS_MASK | SC_EPIT);
320 if (priv->variant->support_rmii)
323 switch (priv->interface) {
324 case PHY_INTERFACE_MODE_MII:
327 case PHY_INTERFACE_MODE_RGMII:
328 case PHY_INTERFACE_MODE_RGMII_ID:
329 case PHY_INTERFACE_MODE_RGMII_RXID:
330 case PHY_INTERFACE_MODE_RGMII_TXID:
331 reg |= SC_EPIT | SC_ETCS_INT_GMII;
333 case PHY_INTERFACE_MODE_RMII:
334 if (priv->variant->support_rmii) {
335 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
339 debug("%s: Invalid PHY interface\n", __func__);
343 if (pdata->tx_delay_ps)
344 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
347 if (pdata->rx_delay_ps)
348 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
351 writel(reg, priv->sysctl_reg);
356 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
358 struct phy_device *phydev;
360 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
364 priv->phydev = phydev;
365 phy_config(priv->phydev);
370 #define cache_clean_descriptor(desc) \
371 flush_dcache_range((uintptr_t)(desc), \
372 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
374 #define cache_inv_descriptor(desc) \
375 invalidate_dcache_range((uintptr_t)(desc), \
376 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
378 static void rx_descs_init(struct emac_eth_dev *priv)
380 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
381 char *rxbuffs = &priv->rxbuffer[0];
382 struct emac_dma_desc *desc_p;
386 * Make sure we don't have dirty cache lines around, which could
387 * be cleaned to DRAM *after* the MAC has already written data to it.
389 invalidate_dcache_range((uintptr_t)desc_table_p,
390 (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
391 invalidate_dcache_range((uintptr_t)rxbuffs,
392 (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
394 for (i = 0; i < CFG_RX_DESCR_NUM; i++) {
395 desc_p = &desc_table_p[i];
396 desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CFG_ETH_BUFSIZE];
397 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
398 desc_p->ctl_size = CFG_ETH_RXSIZE;
399 desc_p->status = EMAC_DESC_OWN_DMA;
402 /* Correcting the last pointer of the chain */
403 desc_p->next = (uintptr_t)&desc_table_p[0];
405 flush_dcache_range((uintptr_t)priv->rx_chain,
406 (uintptr_t)priv->rx_chain +
407 sizeof(priv->rx_chain));
409 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
410 priv->rx_currdescnum = 0;
413 static void tx_descs_init(struct emac_eth_dev *priv)
415 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
416 char *txbuffs = &priv->txbuffer[0];
417 struct emac_dma_desc *desc_p;
420 for (i = 0; i < CFG_TX_DESCR_NUM; i++) {
421 desc_p = &desc_table_p[i];
422 desc_p->buf_addr = (uintptr_t)&txbuffs[i * CFG_ETH_BUFSIZE];
423 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
424 desc_p->ctl_size = 0;
428 /* Correcting the last pointer of the chain */
429 desc_p->next = (uintptr_t)&desc_table_p[0];
431 /* Flush the first TX buffer descriptor we will tell the MAC about. */
432 cache_clean_descriptor(desc_table_p);
434 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
435 priv->tx_currdescnum = 0;
438 static int sun8i_emac_eth_start(struct udevice *dev)
440 struct emac_eth_dev *priv = dev_get_priv(dev);
444 writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
445 ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
446 EMAC_CTL1_SOFT_RST, false, 10, true);
448 printf("%s: Timeout\n", __func__);
452 /* Rewrite mac address after reset */
453 sun8i_eth_write_hwaddr(dev);
455 /* transmission starts after the full frame arrived in TX DMA FIFO */
456 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
459 * RX DMA reads data from RX DMA FIFO to host memory after a
460 * complete frame has been written to RX DMA FIFO
462 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
464 /* DMA burst length */
465 writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
467 /* Initialize rx/tx descriptors */
472 ret = phy_startup(priv->phydev);
476 sun8i_adjust_link(priv, priv->phydev);
478 /* Start RX/TX DMA */
479 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
480 EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
481 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
484 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
485 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
490 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
492 struct emac_eth_dev *priv = dev_get_priv(dev);
493 u32 status, desc_num = priv->rx_currdescnum;
494 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
495 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
498 /* Invalidate entire buffer descriptor */
499 cache_inv_descriptor(desc_p);
501 status = desc_p->status;
503 /* Check for DMA own bit */
504 if (status & EMAC_DESC_OWN_DMA)
507 length = (status >> 16) & 0x3fff;
509 /* make sure we read from DRAM, not our cache */
510 invalidate_dcache_range(data_start,
511 data_start + roundup(length, ARCH_DMA_MINALIGN));
513 if (status & EMAC_DESC_RX_ERROR_MASK) {
514 debug("RX: packet error: 0x%x\n",
515 status & EMAC_DESC_RX_ERROR_MASK);
519 debug("RX: Bad Packet (runt)\n");
523 if (length > CFG_ETH_RXSIZE) {
524 debug("RX: Too large packet (%d bytes)\n", length);
528 *packetp = (uchar *)(ulong)desc_p->buf_addr;
533 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
535 struct emac_eth_dev *priv = dev_get_priv(dev);
536 u32 desc_num = priv->tx_currdescnum;
537 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
538 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
539 uintptr_t data_end = data_start +
540 roundup(length, ARCH_DMA_MINALIGN);
542 desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
544 memcpy((void *)data_start, packet, length);
546 /* Flush data to be sent */
547 flush_dcache_range(data_start, data_end);
549 /* frame begin and end */
550 desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
551 desc_p->status = EMAC_DESC_OWN_DMA;
553 /* make sure the MAC reads the actual data from DRAM */
554 cache_clean_descriptor(desc_p);
556 /* Move to next Descriptor and wrap around */
557 if (++desc_num >= CFG_TX_DESCR_NUM)
559 priv->tx_currdescnum = desc_num;
562 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
565 * Since we copied the data above, we return here without waiting
566 * for the packet to be actually send out.
572 static int sun8i_emac_board_setup(struct udevice *dev,
573 struct emac_eth_dev *priv)
577 ret = clk_enable(&priv->tx_clk);
579 dev_err(dev, "failed to enable TX clock\n");
583 if (reset_valid(&priv->tx_rst)) {
584 ret = reset_deassert(&priv->tx_rst);
586 dev_err(dev, "failed to deassert TX reset\n");
591 /* Only H3/H5 have clock controls for internal EPHY */
592 if (clk_valid(&priv->ephy_clk)) {
593 ret = clk_enable(&priv->ephy_clk);
595 dev_err(dev, "failed to enable EPHY TX clock\n");
600 if (reset_valid(&priv->ephy_rst)) {
601 ret = reset_deassert(&priv->ephy_rst);
603 dev_err(dev, "failed to deassert EPHY TX clock\n");
611 clk_disable(&priv->tx_clk);
615 static int sun8i_mdio_reset(struct mii_dev *bus)
617 struct udevice *dev = bus->priv;
618 struct emac_eth_dev *priv = dev_get_priv(dev);
619 struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
622 if (!dm_gpio_is_valid(&priv->reset_gpio))
626 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
630 udelay(pdata->reset_delays[0]);
632 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
636 udelay(pdata->reset_delays[1]);
638 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
642 udelay(pdata->reset_delays[2]);
647 static int sun8i_mdio_init(const char *name, struct udevice *priv)
649 struct mii_dev *bus = mdio_alloc();
652 debug("Failed to allocate MDIO bus\n");
656 bus->read = sun8i_mdio_read;
657 bus->write = sun8i_mdio_write;
658 snprintf(bus->name, sizeof(bus->name), name);
659 bus->priv = (void *)priv;
660 bus->reset = sun8i_mdio_reset;
662 return mdio_register(bus);
665 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
668 struct emac_eth_dev *priv = dev_get_priv(dev);
669 u32 desc_num = priv->rx_currdescnum;
670 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
672 /* give the current descriptor back to the MAC */
673 desc_p->status |= EMAC_DESC_OWN_DMA;
675 /* Flush Status field of descriptor */
676 cache_clean_descriptor(desc_p);
678 /* Move to next desc and wrap-around condition. */
679 if (++desc_num >= CFG_RX_DESCR_NUM)
681 priv->rx_currdescnum = desc_num;
686 static void sun8i_emac_eth_stop(struct udevice *dev)
688 struct emac_eth_dev *priv = dev_get_priv(dev);
690 /* Stop Rx/Tx transmitter */
691 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
692 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
695 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
696 clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
698 phy_shutdown(priv->phydev);
701 static int sun8i_emac_eth_probe(struct udevice *dev)
703 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
704 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
705 struct emac_eth_dev *priv = dev_get_priv(dev);
708 priv->mac_reg = (void *)pdata->iobase;
710 ret = sun8i_emac_board_setup(dev, priv);
714 sun8i_emac_set_syscon(sun8i_pdata, priv);
717 regulator_set_enable(priv->phy_reg, true);
719 sun8i_mdio_init(dev->name, dev);
720 priv->bus = miiphy_get_dev_by_name(dev->name);
722 return sun8i_phy_init(priv, dev);
725 static const struct eth_ops sun8i_emac_eth_ops = {
726 .start = sun8i_emac_eth_start,
727 .write_hwaddr = sun8i_eth_write_hwaddr,
728 .send = sun8i_emac_eth_send,
729 .recv = sun8i_emac_eth_recv,
730 .free_pkt = sun8i_eth_free_pkt,
731 .stop = sun8i_emac_eth_stop,
734 static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
736 struct ofnode_phandle_args phandle;
739 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
740 NULL, 0, 0, &phandle);
744 /* If the PHY node is not a child of the internal MDIO bus, we are
745 * using some external PHY.
747 if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
748 "allwinner,sun8i-h3-mdio-internal"))
751 ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
753 dev_err(dev, "failed to get EPHY TX clock\n");
757 ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
759 dev_err(dev, "failed to get EPHY TX reset\n");
763 priv->use_internal_phy = true;
768 static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
770 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
771 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
772 struct emac_eth_dev *priv = dev_get_priv(dev);
773 phys_addr_t syscon_base;
775 int node = dev_of_offset(dev);
777 int reset_flags = GPIOD_IS_OUT;
780 pdata->iobase = dev_read_addr(dev);
781 if (pdata->iobase == FDT_ADDR_T_NONE) {
782 debug("%s: Cannot find MAC base address\n", __func__);
786 priv->variant = (const void *)dev_get_driver_data(dev);
788 if (!priv->variant) {
789 printf("%s: Missing variant\n", __func__);
793 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
795 dev_err(dev, "failed to get TX clock\n");
799 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
800 if (ret && ret != -ENOENT) {
801 dev_err(dev, "failed to get TX reset\n");
805 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
807 debug("%s: cannot find syscon node\n", __func__);
811 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
813 debug("%s: cannot find reg property in syscon node\n",
818 syscon_base = fdt_translate_address((void *)gd->fdt_blob, offset, reg);
819 if (syscon_base == FDT_ADDR_T_NONE) {
820 debug("%s: Cannot find syscon base address\n", __func__);
824 priv->sysctl_reg = (void *)syscon_base + priv->variant->syscon_offset;
826 device_get_supply_regulator(dev, "phy-supply", &priv->phy_reg);
828 pdata->phy_interface = -1;
830 priv->use_internal_phy = false;
832 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
834 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
836 pdata->phy_interface = dev_read_phy_mode(dev);
837 debug("phy interface %d\n", pdata->phy_interface);
838 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
841 if (priv->variant->soc_has_internal_phy) {
842 ret = sun8i_handle_internal_phy(dev, priv);
847 priv->interface = pdata->phy_interface;
849 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
850 "allwinner,tx-delay-ps", 0);
851 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
852 printf("%s: Invalid TX delay value %d\n", __func__,
853 sun8i_pdata->tx_delay_ps);
855 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
856 "allwinner,rx-delay-ps", 0);
857 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
858 printf("%s: Invalid RX delay value %d\n", __func__,
859 sun8i_pdata->rx_delay_ps);
861 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
862 "snps,reset-active-low"))
863 reset_flags |= GPIOD_ACTIVE_LOW;
865 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
866 &priv->reset_gpio, reset_flags);
869 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
870 "snps,reset-delays-us",
871 sun8i_pdata->reset_delays, 3);
872 } else if (ret == -ENOENT) {
879 static const struct emac_variant emac_variant_a83t = {
880 .syscon_offset = 0x30,
883 static const struct emac_variant emac_variant_h3 = {
884 .syscon_offset = 0x30,
885 .soc_has_internal_phy = true,
886 .support_rmii = true,
889 static const struct emac_variant emac_variant_r40 = {
890 .syscon_offset = 0x164,
893 static const struct emac_variant emac_variant_v3s = {
894 .syscon_offset = 0x30,
895 .soc_has_internal_phy = true,
898 static const struct emac_variant emac_variant_a64 = {
899 .syscon_offset = 0x30,
900 .support_rmii = true,
903 static const struct emac_variant emac_variant_h6 = {
904 .syscon_offset = 0x30,
905 .support_rmii = true,
908 static const struct udevice_id sun8i_emac_eth_ids[] = {
909 { .compatible = "allwinner,sun8i-a83t-emac",
910 .data = (ulong)&emac_variant_a83t },
911 { .compatible = "allwinner,sun8i-h3-emac",
912 .data = (ulong)&emac_variant_h3 },
913 { .compatible = "allwinner,sun8i-r40-gmac",
914 .data = (ulong)&emac_variant_r40 },
915 { .compatible = "allwinner,sun8i-v3s-emac",
916 .data = (ulong)&emac_variant_v3s },
917 { .compatible = "allwinner,sun50i-a64-emac",
918 .data = (ulong)&emac_variant_a64 },
919 { .compatible = "allwinner,sun50i-h6-emac",
920 .data = (ulong)&emac_variant_h6 },
924 U_BOOT_DRIVER(eth_sun8i_emac) = {
925 .name = "eth_sun8i_emac",
927 .of_match = sun8i_emac_eth_ids,
928 .of_to_plat = sun8i_emac_eth_of_to_plat,
929 .probe = sun8i_emac_eth_probe,
930 .ops = &sun8i_emac_eth_ops,
931 .priv_auto = sizeof(struct emac_eth_dev),
932 .plat_auto = sizeof(struct sun8i_eth_pdata),
933 .flags = DM_FLAG_ALLOC_PRIV_DMA,