2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0+
17 #if !defined(CONFIG_PHYLIB)
18 # error AXI_ETHERNET requires PHYLIB
22 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
23 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
24 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
25 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
27 /* Interrupt Status/Enable/Mask Registers bit definitions */
28 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
29 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
31 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
32 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
34 /* Transmitter Configuration (TC) Register bit definitions */
35 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
37 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
39 /* MDIO Management Configuration (MC) Register bit definitions */
40 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
42 /* MDIO Management Control Register (MCR) Register bit definitions */
43 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
44 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
45 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
46 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
47 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
48 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
49 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
50 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
52 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
55 /* Bitmasks of XAXIDMA_CR_OFFSET register */
56 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
57 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
59 /* Bitmasks of XAXIDMA_SR_OFFSET register */
60 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
62 /* Bitmask for interrupts */
63 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
64 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
65 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
67 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
68 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
69 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
73 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
75 /* Reflect dma offsets */
77 u32 control; /* DMACR */
78 u32 status; /* DMASR */
79 u32 current; /* CURDESC */
81 u32 tail; /* TAILDESC */
84 /* Private driver structures */
86 struct axidma_reg *dmatx;
87 struct axidma_reg *dmarx;
90 struct phy_device *phydev;
96 u32 next; /* Next descriptor pointer */
98 u32 phys; /* Buffer address */
102 u32 cntrl; /* Control */
103 u32 status; /* Status */
105 u32 app1; /* TX start << 16 | insert */
106 u32 app2; /* TX csum seed */
114 /* Static BDs - driver uses only one BD */
115 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
116 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
120 u32 is; /* 0xC: Interrupt status */
122 u32 ie; /* 0x14: Interrupt enable */
124 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
125 u32 tc; /* 0x408: Tx Configuration */
127 u32 emmc; /* 0x410: EMAC mode configuration */
129 u32 mdio_mc; /* 0x500: MII Management Config */
130 u32 mdio_mcr; /* 0x504: MII Management Control */
131 u32 mdio_mwd; /* 0x508: MII Management Write Data */
132 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
134 u32 uaw0; /* 0x700: Unicast address word 0 */
135 u32 uaw1; /* 0x704: Unicast address word 1 */
138 /* Use MII register 1 (MII status register) to detect PHY */
139 #define PHY_DETECT_REG 1
142 * Mask used to verify certain PHY features (or register contents)
143 * in the register above:
144 * 0x1000: 10Mbps full duplex support
145 * 0x0800: 10Mbps half duplex support
146 * 0x0008: Auto-negotiation support
148 #define PHY_DETECT_MASK 0x1808
150 static inline int mdio_wait(struct eth_device *dev)
152 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
155 /* Wait till MDIO interface is ready to accept a new transaction. */
156 while (timeout && (!(in_be32(®s->mdio_mcr)
157 & XAE_MDIO_MCR_READY_MASK))) {
162 printf("%s: Timeout\n", __func__);
168 static u32 phyread(struct eth_device *dev, u32 phyaddress, u32 registernum,
171 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
177 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
178 XAE_MDIO_MCR_PHYAD_MASK) |
179 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
180 & XAE_MDIO_MCR_REGAD_MASK) |
181 XAE_MDIO_MCR_INITIATE_MASK |
182 XAE_MDIO_MCR_OP_READ_MASK;
184 out_be32(®s->mdio_mcr, mdioctrlreg);
190 *val = in_be32(®s->mdio_mrd);
194 static u32 phywrite(struct eth_device *dev, u32 phyaddress, u32 registernum,
197 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
203 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
204 XAE_MDIO_MCR_PHYAD_MASK) |
205 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
206 & XAE_MDIO_MCR_REGAD_MASK) |
207 XAE_MDIO_MCR_INITIATE_MASK |
208 XAE_MDIO_MCR_OP_WRITE_MASK;
211 out_be32(®s->mdio_mwd, data);
213 out_be32(®s->mdio_mcr, mdioctrlreg);
221 /* Setting axi emac and phy to proper setting */
222 static int setup_phy(struct eth_device *dev)
225 u32 i, speed, emmc_reg, ret;
226 struct axidma_priv *priv = dev->priv;
227 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
228 struct phy_device *phydev;
230 u32 supported = SUPPORTED_10baseT_Half |
231 SUPPORTED_10baseT_Full |
232 SUPPORTED_100baseT_Half |
233 SUPPORTED_100baseT_Full |
234 SUPPORTED_1000baseT_Half |
235 SUPPORTED_1000baseT_Full;
237 if (priv->phyaddr == -1) {
238 /* Detect the PHY address */
239 for (i = 31; i >= 0; i--) {
240 ret = phyread(dev, i, PHY_DETECT_REG, &phyreg);
241 if (!ret && (phyreg != 0xFFFF) &&
242 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
243 /* Found a valid PHY address */
245 debug("axiemac: Found valid phy address, %x\n",
252 /* Interface - look at tsec */
253 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
255 phydev->supported &= supported;
256 phydev->advertising = phydev->supported;
257 priv->phydev = phydev;
259 if (phy_startup(phydev)) {
260 printf("axiemac: could not initialize PHY %s\n",
265 printf("%s: No link.\n", phydev->dev->name);
269 switch (phydev->speed) {
271 speed = XAE_EMMC_LINKSPD_1000;
274 speed = XAE_EMMC_LINKSPD_100;
277 speed = XAE_EMMC_LINKSPD_10;
283 /* Setup the emac for the phy speed */
284 emmc_reg = in_be32(®s->emmc);
285 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
288 /* Write new speed setting out to Axi Ethernet */
289 out_be32(®s->emmc, emmc_reg);
292 * Setting the operating speed of the MAC needs a delay. There
293 * doesn't seem to be register to poll, so please consider this
294 * during your application design.
301 /* STOP DMA transfers */
302 static void axiemac_halt(struct eth_device *dev)
304 struct axidma_priv *priv = dev->priv;
307 /* Stop the hardware */
308 temp = in_be32(&priv->dmatx->control);
309 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
310 out_be32(&priv->dmatx->control, temp);
312 temp = in_be32(&priv->dmarx->control);
313 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
314 out_be32(&priv->dmarx->control, temp);
316 debug("axiemac: Halted\n");
319 static int axi_ethernet_init(struct eth_device *dev)
321 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
325 * Check the status of the MgtRdy bit in the interrupt status
326 * registers. This must be done to allow the MGT clock to become stable
327 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
328 * will be valid until this bit is valid.
329 * The bit is always a 1 for all other PHY interfaces.
331 while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) {
336 printf("%s: Timeout\n", __func__);
340 /* Stop the device and reset HW */
341 /* Disable interrupts */
342 out_be32(®s->ie, 0);
344 /* Disable the receiver */
345 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
348 * Stopping the receiver in mid-packet causes a dropped packet
349 * indication from HW. Clear it.
351 /* Set the interrupt status register to clear the interrupt */
352 out_be32(®s->is, XAE_INT_RXRJECT_MASK);
355 /* Set default MDIO divisor */
356 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
358 debug("axiemac: InitHw done\n");
362 static int axiemac_setup_mac(struct eth_device *dev)
364 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
366 /* Set the MAC address */
367 int val = ((dev->enetaddr[3] << 24) | (dev->enetaddr[2] << 16) |
368 (dev->enetaddr[1] << 8) | (dev->enetaddr[0]));
369 out_be32(®s->uaw0, val);
371 val = (dev->enetaddr[5] << 8) | dev->enetaddr[4] ;
372 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
373 out_be32(®s->uaw1, val);
377 /* Reset DMA engine */
378 static void axi_dma_init(struct eth_device *dev)
380 struct axidma_priv *priv = dev->priv;
383 /* Reset the engine so the hardware starts from a known state */
384 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
385 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
387 /* At the initialization time, hardware should finish reset quickly */
389 /* Check transmit/receive channel */
390 /* Reset is done when the reset bit is low */
391 if (!((in_be32(&priv->dmatx->control) |
392 in_be32(&priv->dmarx->control))
393 & XAXIDMA_CR_RESET_MASK)) {
398 printf("%s: Timeout\n", __func__);
401 static int axiemac_init(struct eth_device *dev, bd_t * bis)
403 struct axidma_priv *priv = dev->priv;
404 struct axi_regs *regs = (struct axi_regs *)dev->iobase;
407 debug("axiemac: Init started\n");
409 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
410 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
411 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
412 * would ensure a reset of AxiEthernet.
416 /* Initialize AxiEthernet hardware. */
417 if (axi_ethernet_init(dev))
420 /* Disable all RX interrupts before RxBD space setup */
421 temp = in_be32(&priv->dmarx->control);
422 temp &= ~XAXIDMA_IRQ_ALL_MASK;
423 out_be32(&priv->dmarx->control, temp);
425 /* Start DMA RX channel. Now it's ready to receive data.*/
426 out_be32(&priv->dmarx->current, (u32)&rx_bd);
429 memset(&rx_bd, 0, sizeof(rx_bd));
430 rx_bd.next = (u32)&rx_bd;
431 rx_bd.phys = (u32)&rxframe;
432 rx_bd.cntrl = sizeof(rxframe);
433 /* Flush the last BD so DMA core could see the updates */
434 flush_cache((u32)&rx_bd, sizeof(rx_bd));
436 /* It is necessary to flush rxframe because if you don't do it
437 * then cache can contain uninitialized data */
438 flush_cache((u32)&rxframe, sizeof(rxframe));
440 /* Start the hardware */
441 temp = in_be32(&priv->dmarx->control);
442 temp |= XAXIDMA_CR_RUNSTOP_MASK;
443 out_be32(&priv->dmarx->control, temp);
445 /* Rx BD is ready - start */
446 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
449 out_be32(®s->tc, XAE_TC_TX_MASK);
451 out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
454 if (!setup_phy(dev)) {
459 debug("axiemac: Init complete\n");
463 static int axiemac_send(struct eth_device *dev, void *ptr, int len)
465 struct axidma_priv *priv = dev->priv;
468 if (len > PKTSIZE_ALIGN)
471 /* Flush packet to main memory to be trasfered by DMA */
472 flush_cache((u32)ptr, len);
475 memset(&tx_bd, 0, sizeof(tx_bd));
476 /* At the end of the ring, link the last BD back to the top */
477 tx_bd.next = (u32)&tx_bd;
478 tx_bd.phys = (u32)ptr;
480 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
481 XAXIDMA_BD_CTRL_TXEOF_MASK;
483 /* Flush the last BD so DMA core could see the updates */
484 flush_cache((u32)&tx_bd, sizeof(tx_bd));
486 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
488 out_be32(&priv->dmatx->current, (u32)&tx_bd);
489 /* Start the hardware */
490 temp = in_be32(&priv->dmatx->control);
491 temp |= XAXIDMA_CR_RUNSTOP_MASK;
492 out_be32(&priv->dmatx->control, temp);
496 out_be32(&priv->dmatx->tail, (u32)&tx_bd);
498 /* Wait for transmission to complete */
499 debug("axiemac: Waiting for tx to be done\n");
501 while (timeout && (!(in_be32(&priv->dmatx->status) &
502 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
507 printf("%s: Timeout\n", __func__);
511 debug("axiemac: Sending complete\n");
515 static int isrxready(struct eth_device *dev)
518 struct axidma_priv *priv = dev->priv;
520 /* Read pending interrupts */
521 status = in_be32(&priv->dmarx->status);
523 /* Acknowledge pending interrupts */
524 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
527 * If Reception done interrupt is asserted, call RX call back function
528 * to handle the processed BDs and then raise the according flag.
530 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
536 static int axiemac_recv(struct eth_device *dev)
539 struct axidma_priv *priv = dev->priv;
542 /* Wait for an incoming packet */
546 debug("axiemac: RX data ready\n");
548 /* Disable IRQ for a moment till packet is handled */
549 temp = in_be32(&priv->dmarx->control);
550 temp &= ~XAXIDMA_IRQ_ALL_MASK;
551 out_be32(&priv->dmarx->control, temp);
553 length = rx_bd.app4 & 0xFFFF; /* max length mask */
555 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
557 /* Pass the received frame up for processing */
559 net_process_received_packet(rxframe, length);
562 /* It is useful to clear buffer to be sure that it is consistent */
563 memset(rxframe, 0, sizeof(rxframe));
566 /* Clear the whole buffer and setup it again - all flags are cleared */
567 memset(&rx_bd, 0, sizeof(rx_bd));
568 rx_bd.next = (u32)&rx_bd;
569 rx_bd.phys = (u32)&rxframe;
570 rx_bd.cntrl = sizeof(rxframe);
573 flush_cache((u32)&rx_bd, sizeof(rx_bd));
575 /* It is necessary to flush rxframe because if you don't do it
576 * then cache will contain previous packet */
577 flush_cache((u32)&rxframe, sizeof(rxframe));
579 /* Rx BD is ready - start again */
580 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
582 debug("axiemac: RX completed, framelength = %d\n", length);
587 static int axiemac_miiphy_read(const char *devname, uchar addr,
588 uchar reg, ushort *val)
590 struct eth_device *dev = eth_get_dev();
593 ret = phyread(dev, addr, reg, val);
594 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x\n", addr, reg, *val);
598 static int axiemac_miiphy_write(const char *devname, uchar addr,
599 uchar reg, ushort val)
601 struct eth_device *dev = eth_get_dev();
603 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, val);
604 return phywrite(dev, addr, reg, val);
607 static int axiemac_bus_reset(struct mii_dev *bus)
609 debug("axiemac: Bus reset\n");
613 int xilinx_axiemac_initialize(bd_t *bis, unsigned long base_addr,
614 unsigned long dma_addr)
616 struct eth_device *dev;
617 struct axidma_priv *priv;
619 dev = calloc(1, sizeof(struct eth_device));
623 dev->priv = calloc(1, sizeof(struct axidma_priv));
624 if (dev->priv == NULL) {
630 sprintf(dev->name, "aximac.%lx", base_addr);
632 dev->iobase = base_addr;
633 priv->dmatx = (struct axidma_reg *)dma_addr;
634 /* RX channel offset is 0x30 */
635 priv->dmarx = (struct axidma_reg *)(dma_addr + 0x30);
636 dev->init = axiemac_init;
637 dev->halt = axiemac_halt;
638 dev->send = axiemac_send;
639 dev->recv = axiemac_recv;
640 dev->write_hwaddr = axiemac_setup_mac;
642 #ifdef CONFIG_PHY_ADDR
643 priv->phyaddr = CONFIG_PHY_ADDR;
650 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
651 miiphy_register(dev->name, axiemac_miiphy_read, axiemac_miiphy_write);
652 priv->bus = miiphy_get_dev_by_name(dev->name);
653 priv->bus->reset = axiemac_bus_reset;