1 // SPDX-License-Identifier: GPL-2.0+
3 * Rockchip AXI PCIe host controller driver
5 * Copyright (c) 2016 Rockchip, Inc.
6 * Copyright (c) 2020 Amarula Solutions(India)
7 * Copyright (c) 2020 Jagan Teki <jagan@amarulasolutions.com>
8 * Copyright (c) 2019 Patrick Wildt <patrick@blueri.se>
9 * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
11 * Bits taken from Linux Rockchip PCIe host controller.
15 #include <dm/device_compat.h>
16 #include <generic-phy.h>
18 #include <power/regulator.h>
20 #include <asm-generic/gpio.h>
21 #include <linux/iopoll.h>
23 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
24 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
26 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
27 #define PCIE_CLIENT_BASE 0x0
28 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
29 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
30 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
31 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
32 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
33 #define PCIE_CLIENT_BASIC_STATUS1 0x0048
34 #define PCIE_CLIENT_LINK_STATUS_UP GENMASK(21, 20)
35 #define PCIE_CLIENT_LINK_STATUS_MASK GENMASK(21, 20)
36 #define PCIE_LINK_UP(x) \
37 (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP)
38 #define PCIE_RC_NORMAL_BASE 0x800000
39 #define PCIE_LM_BASE 0x900000
40 #define PCIE_LM_VENDOR_ID (PCIE_LM_BASE + 0x44)
41 #define PCIE_LM_VENDOR_ROCKCHIP 0x1d87
42 #define PCIE_LM_RCBAR (PCIE_LM_BASE + 0x300)
43 #define PCIE_LM_RCBARPIE BIT(19)
44 #define PCIE_LM_RCBARPIS BIT(20)
45 #define PCIE_RC_BASE 0xa00000
46 #define PCIE_RC_CONFIG_DCR (PCIE_RC_BASE + 0x0c4)
47 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
48 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
49 #define PCIE_RC_PCIE_LCAP (PCIE_RC_BASE + 0x0cc)
50 #define PCIE_RC_PCIE_LCAP_APMS_L0S BIT(10)
51 #define PCIE_ATR_BASE 0xc00000
52 #define PCIE_ATR_OB_ADDR0(i) (PCIE_ATR_BASE + 0x000 + (i) * 0x20)
53 #define PCIE_ATR_OB_ADDR1(i) (PCIE_ATR_BASE + 0x004 + (i) * 0x20)
54 #define PCIE_ATR_OB_DESC0(i) (PCIE_ATR_BASE + 0x008 + (i) * 0x20)
55 #define PCIE_ATR_OB_DESC1(i) (PCIE_ATR_BASE + 0x00c + (i) * 0x20)
56 #define PCIE_ATR_IB_ADDR0(i) (PCIE_ATR_BASE + 0x800 + (i) * 0x8)
57 #define PCIE_ATR_IB_ADDR1(i) (PCIE_ATR_BASE + 0x804 + (i) * 0x8)
58 #define PCIE_ATR_HDR_MEM 0x2
59 #define PCIE_ATR_HDR_IO 0x6
60 #define PCIE_ATR_HDR_CFG_TYPE0 0xa
61 #define PCIE_ATR_HDR_CFG_TYPE1 0xb
62 #define PCIE_ATR_HDR_RID BIT(23)
64 #define PCIE_ATR_OB_REGION0_SIZE (32 * 1024 * 1024)
65 #define PCIE_ATR_OB_REGION_SIZE (1 * 1024 * 1024)
67 struct rockchip_pcie {
74 struct reset_ctl core_rst;
75 struct reset_ctl mgmt_rst;
76 struct reset_ctl mgmt_sticky_rst;
77 struct reset_ctl pipe_rst;
78 struct reset_ctl pm_rst;
79 struct reset_ctl pclk_rst;
80 struct reset_ctl aclk_rst;
83 struct gpio_desc ep_gpio;
85 /* vpcie regulators */
86 struct udevice *vpcie12v;
87 struct udevice *vpcie3v3;
88 struct udevice *vpcie1v8;
89 struct udevice *vpcie0v9;
95 static int rockchip_pcie_rd_conf(const struct udevice *udev, pci_dev_t bdf,
96 uint offset, ulong *valuep,
99 struct rockchip_pcie *priv = dev_get_priv(udev);
100 unsigned int bus = PCI_BUS(bdf);
101 unsigned int dev = PCI_DEV(bdf);
102 int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset & ~0x3);
105 if (bus == priv->first_busno && dev == 0) {
106 value = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
107 *valuep = pci_conv_32_to_size(value, offset, size);
111 if ((bus == priv->first_busno + 1) && dev == 0) {
112 value = readl(priv->axi_base + where);
113 *valuep = pci_conv_32_to_size(value, offset, size);
117 *valuep = pci_get_ff(size);
122 static int rockchip_pcie_wr_conf(struct udevice *udev, pci_dev_t bdf,
123 uint offset, ulong value,
124 enum pci_size_t size)
126 struct rockchip_pcie *priv = dev_get_priv(udev);
127 unsigned int bus = PCI_BUS(bdf);
128 unsigned int dev = PCI_DEV(bdf);
129 int where = PCIE_ECAM_OFFSET(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset & ~0x3);
132 if (bus == priv->first_busno && dev == 0) {
133 old = readl(priv->apb_base + PCIE_RC_NORMAL_BASE + where);
134 value = pci_conv_size_to_32(old, value, offset, size);
135 writel(value, priv->apb_base + PCIE_RC_NORMAL_BASE + where);
139 if ((bus == priv->first_busno + 1) && dev == 0) {
140 old = readl(priv->axi_base + where);
141 value = pci_conv_size_to_32(old, value, offset, size);
142 writel(value, priv->axi_base + where);
149 static int rockchip_pcie_atr_init(struct rockchip_pcie *priv)
151 struct udevice *ctlr = pci_get_controller(priv->dev);
152 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
153 u64 addr, size, offset;
157 /* Use region 0 to map PCI configuration space. */
158 writel(25 - 1, priv->apb_base + PCIE_ATR_OB_ADDR0(0));
159 writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(0));
160 writel(PCIE_ATR_HDR_CFG_TYPE0 | PCIE_ATR_HDR_RID,
161 priv->apb_base + PCIE_ATR_OB_DESC0(0));
162 writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(0));
164 for (i = 0; i < hose->region_count; i++) {
165 if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
168 if (hose->regions[i].flags == PCI_REGION_IO)
169 type = PCIE_ATR_HDR_IO;
171 type = PCIE_ATR_HDR_MEM;
173 /* Only support identity mappings. */
174 if (hose->regions[i].bus_start !=
175 hose->regions[i].phys_start)
178 /* Only support mappings aligned on a region boundary. */
179 addr = hose->regions[i].bus_start;
180 if (addr & (PCIE_ATR_OB_REGION_SIZE - 1))
183 /* Mappings should lie between AXI and APB regions. */
184 size = hose->regions[i].size;
185 if (addr < (u64)priv->axi_base + PCIE_ATR_OB_REGION0_SIZE)
187 if (addr + size > (u64)priv->apb_base)
190 offset = addr - (u64)priv->axi_base - PCIE_ATR_OB_REGION0_SIZE;
191 region = 1 + (offset / PCIE_ATR_OB_REGION_SIZE);
194 priv->apb_base + PCIE_ATR_OB_ADDR0(region));
195 writel(0, priv->apb_base + PCIE_ATR_OB_ADDR1(region));
196 writel(type | PCIE_ATR_HDR_RID,
197 priv->apb_base + PCIE_ATR_OB_DESC0(region));
198 writel(0, priv->apb_base + PCIE_ATR_OB_DESC1(region));
200 addr += PCIE_ATR_OB_REGION_SIZE;
201 size -= PCIE_ATR_OB_REGION_SIZE;
206 /* Passthrough inbound translations unmodified. */
207 writel(32 - 1, priv->apb_base + PCIE_ATR_IB_ADDR0(2));
208 writel(0, priv->apb_base + PCIE_ATR_IB_ADDR1(2));
213 static int rockchip_pcie_init_port(struct udevice *dev)
215 struct rockchip_pcie *priv = dev_get_priv(dev);
219 if (dm_gpio_is_valid(&priv->ep_gpio))
220 dm_gpio_set_value(&priv->ep_gpio, 0);
222 ret = reset_assert(&priv->aclk_rst);
224 dev_err(dev, "failed to assert aclk reset (ret=%d)\n", ret);
228 ret = reset_assert(&priv->pclk_rst);
230 dev_err(dev, "failed to assert pclk reset (ret=%d)\n", ret);
234 ret = reset_assert(&priv->pm_rst);
236 dev_err(dev, "failed to assert pm reset (ret=%d)\n", ret);
240 ret = generic_phy_init(&priv->pcie_phy);
242 dev_err(dev, "failed to init phy (ret=%d)\n", ret);
246 ret = reset_assert(&priv->core_rst);
248 dev_err(dev, "failed to assert core reset (ret=%d)\n", ret);
252 ret = reset_assert(&priv->mgmt_rst);
254 dev_err(dev, "failed to assert mgmt reset (ret=%d)\n", ret);
258 ret = reset_assert(&priv->mgmt_sticky_rst);
260 dev_err(dev, "failed to assert mgmt-sticky reset (ret=%d)\n",
265 ret = reset_assert(&priv->pipe_rst);
267 dev_err(dev, "failed to assert pipe reset (ret=%d)\n", ret);
273 ret = reset_deassert(&priv->pm_rst);
275 dev_err(dev, "failed to deassert pm reset (ret=%d)\n", ret);
279 ret = reset_deassert(&priv->aclk_rst);
281 dev_err(dev, "failed to deassert aclk reset (ret=%d)\n", ret);
285 ret = reset_deassert(&priv->pclk_rst);
287 dev_err(dev, "failed to deassert pclk reset (ret=%d)\n", ret);
291 /* Select GEN1 for now */
292 cr = PCIE_CLIENT_GEN_SEL_1;
293 /* Set Root complex mode */
294 cr |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
295 writel(cr, priv->apb_base + PCIE_CLIENT_CONFIG);
297 ret = generic_phy_power_on(&priv->pcie_phy);
299 dev_err(dev, "failed to power on phy (ret=%d)\n", ret);
300 goto err_power_off_phy;
303 ret = reset_deassert(&priv->mgmt_sticky_rst);
305 dev_err(dev, "failed to deassert mgmt-sticky reset (ret=%d)\n",
307 goto err_power_off_phy;
310 ret = reset_deassert(&priv->core_rst);
312 dev_err(dev, "failed to deassert core reset (ret=%d)\n", ret);
313 goto err_power_off_phy;
316 ret = reset_deassert(&priv->mgmt_rst);
318 dev_err(dev, "failed to deassert mgmt reset (ret=%d)\n", ret);
319 goto err_power_off_phy;
322 ret = reset_deassert(&priv->pipe_rst);
324 dev_err(dev, "failed to deassert pipe reset (ret=%d)\n", ret);
325 goto err_power_off_phy;
328 /* Enable Gen1 training */
329 writel(PCIE_CLIENT_LINK_TRAIN_ENABLE,
330 priv->apb_base + PCIE_CLIENT_CONFIG);
332 if (dm_gpio_is_valid(&priv->ep_gpio))
333 dm_gpio_set_value(&priv->ep_gpio, 1);
335 ret = readl_poll_sleep_timeout
336 (priv->apb_base + PCIE_CLIENT_BASIC_STATUS1,
337 status, PCIE_LINK_UP(status), 20, 500 * 1000);
339 dev_err(dev, "PCIe link training gen1 timeout!\n");
340 goto err_power_off_phy;
343 /* Initialize Root Complex registers. */
344 writel(PCIE_LM_VENDOR_ROCKCHIP, priv->apb_base + PCIE_LM_VENDOR_ID);
345 writel(PCI_CLASS_BRIDGE_PCI_NORMAL << 8,
346 priv->apb_base + PCIE_RC_BASE + PCI_CLASS_REVISION);
347 writel(PCIE_LM_RCBARPIE | PCIE_LM_RCBARPIS,
348 priv->apb_base + PCIE_LM_RCBAR);
350 if (dev_read_bool(dev, "aspm-no-l0s")) {
351 val = readl(priv->apb_base + PCIE_RC_PCIE_LCAP);
352 val &= ~PCIE_RC_PCIE_LCAP_APMS_L0S;
353 writel(val, priv->apb_base + PCIE_RC_PCIE_LCAP);
356 /* Configure Address Translation. */
357 ret = rockchip_pcie_atr_init(priv);
359 dev_err(dev, "PCIE-%d: ATR init failed\n", dev_seq(dev));
360 goto err_power_off_phy;
366 generic_phy_power_off(&priv->pcie_phy);
368 generic_phy_exit(&priv->pcie_phy);
372 static int rockchip_pcie_set_vpcie(struct udevice *dev)
374 struct rockchip_pcie *priv = dev_get_priv(dev);
377 ret = regulator_set_enable_if_allowed(priv->vpcie12v, true);
378 if (ret && ret != -ENOSYS) {
379 dev_err(dev, "failed to enable vpcie12v (ret=%d)\n", ret);
383 ret = regulator_set_enable_if_allowed(priv->vpcie3v3, true);
384 if (ret && ret != -ENOSYS) {
385 dev_err(dev, "failed to enable vpcie3v3 (ret=%d)\n", ret);
386 goto err_disable_12v;
389 ret = regulator_set_enable_if_allowed(priv->vpcie1v8, true);
390 if (ret && ret != -ENOSYS) {
391 dev_err(dev, "failed to enable vpcie1v8 (ret=%d)\n", ret);
392 goto err_disable_3v3;
395 ret = regulator_set_enable_if_allowed(priv->vpcie0v9, true);
396 if (ret && ret != -ENOSYS) {
397 dev_err(dev, "failed to enable vpcie0v9 (ret=%d)\n", ret);
398 goto err_disable_1v8;
404 regulator_set_enable_if_allowed(priv->vpcie1v8, false);
406 regulator_set_enable_if_allowed(priv->vpcie3v3, false);
408 regulator_set_enable_if_allowed(priv->vpcie12v, false);
412 static int rockchip_pcie_parse_dt(struct udevice *dev)
414 struct rockchip_pcie *priv = dev_get_priv(dev);
417 priv->axi_base = dev_read_addr_name(dev, "axi-base");
418 if (priv->axi_base == FDT_ADDR_T_NONE)
421 priv->apb_base = dev_read_addr_name(dev, "apb-base");
422 if (priv->apb_base == FDT_ADDR_T_NONE)
425 ret = reset_get_by_name(dev, "core", &priv->core_rst);
427 dev_err(dev, "failed to get core reset (ret=%d)\n", ret);
431 ret = reset_get_by_name(dev, "mgmt", &priv->mgmt_rst);
433 dev_err(dev, "failed to get mgmt reset (ret=%d)\n", ret);
437 ret = reset_get_by_name(dev, "mgmt-sticky", &priv->mgmt_sticky_rst);
439 dev_err(dev, "failed to get mgmt-sticky reset (ret=%d)\n", ret);
443 ret = reset_get_by_name(dev, "pipe", &priv->pipe_rst);
445 dev_err(dev, "failed to get pipe reset (ret=%d)\n", ret);
449 ret = reset_get_by_name(dev, "pm", &priv->pm_rst);
451 dev_err(dev, "failed to get pm reset (ret=%d)\n", ret);
455 ret = reset_get_by_name(dev, "pclk", &priv->pclk_rst);
457 dev_err(dev, "failed to get pclk reset (ret=%d)\n", ret);
461 ret = reset_get_by_name(dev, "aclk", &priv->aclk_rst);
463 dev_err(dev, "failed to get aclk reset (ret=%d)\n", ret);
467 ret = device_get_supply_regulator(dev, "vpcie12v-supply",
469 if (ret && ret != -ENOENT) {
470 dev_err(dev, "failed to get vpcie12v supply (ret=%d)\n", ret);
474 ret = device_get_supply_regulator(dev, "vpcie3v3-supply",
476 if (ret && ret != -ENOENT) {
477 dev_err(dev, "failed to get vpcie3v3 supply (ret=%d)\n", ret);
481 ret = device_get_supply_regulator(dev, "vpcie1v8-supply",
483 if (ret && ret != -ENOENT) {
484 dev_err(dev, "failed to get vpcie1v8 supply (ret=%d)\n", ret);
488 ret = device_get_supply_regulator(dev, "vpcie0v9-supply",
490 if (ret && ret != -ENOENT) {
491 dev_err(dev, "failed to get vpcie0v9 supply (ret=%d)\n", ret);
495 ret = generic_phy_get_by_index(dev, 0, &priv->pcie_phy);
497 dev_err(dev, "failed to get pcie-phy (ret=%d)\n", ret);
501 ret = gpio_request_by_name(dev, "ep-gpios", 0,
502 &priv->ep_gpio, GPIOD_IS_OUT);
504 dev_err(dev, "failed to find ep-gpios property\n");
511 static int rockchip_pcie_probe(struct udevice *dev)
513 struct rockchip_pcie *priv = dev_get_priv(dev);
514 struct udevice *ctlr = pci_get_controller(dev);
515 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
518 priv->first_busno = dev_seq(dev);
521 ret = rockchip_pcie_parse_dt(dev);
525 ret = rockchip_pcie_set_vpcie(dev);
529 ret = rockchip_pcie_init_port(dev);
531 goto err_disable_vpcie;
533 dev_info(dev, "PCIE-%d: Link up (Bus%d)\n",
534 dev_seq(dev), hose->first_busno);
539 regulator_set_enable_if_allowed(priv->vpcie0v9, false);
540 regulator_set_enable_if_allowed(priv->vpcie1v8, false);
541 regulator_set_enable_if_allowed(priv->vpcie3v3, false);
542 regulator_set_enable_if_allowed(priv->vpcie12v, false);
544 if (dm_gpio_is_valid(&priv->ep_gpio))
545 dm_gpio_free(dev, &priv->ep_gpio);
549 static const struct dm_pci_ops rockchip_pcie_ops = {
550 .read_config = rockchip_pcie_rd_conf,
551 .write_config = rockchip_pcie_wr_conf,
554 static const struct udevice_id rockchip_pcie_ids[] = {
555 { .compatible = "rockchip,rk3399-pcie" },
559 U_BOOT_DRIVER(rockchip_pcie) = {
560 .name = "rockchip_pcie",
562 .of_match = rockchip_pcie_ids,
563 .ops = &rockchip_pcie_ops,
564 .probe = rockchip_pcie_probe,
565 .priv_auto = sizeof(struct rockchip_pcie),