1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Intel Corporation <www.intel.com>
11 #include <asm/arch/clock_manager.h>
12 #include <asm/arch/system_manager.h>
14 #include <dt-bindings/clock/agilex-clock.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 static ulong cm_get_rate_dm(u32 id)
25 ret = uclass_get_device_by_driver(UCLASS_CLK,
26 DM_GET_DRIVER(socfpga_agilex_clk),
32 ret = clk_request(dev, &clk);
36 rate = clk_get_rate(&clk);
40 if ((rate == (unsigned long)-ENOSYS) ||
41 (rate == (unsigned long)-ENXIO) ||
42 (rate == (unsigned long)-EIO)) {
43 debug("%s id %u: clk_get_rate err: %ld\n",
51 static u32 cm_get_rate_dm_khz(u32 id)
53 return cm_get_rate_dm(id) / 1000;
56 unsigned long cm_get_mpu_clk_hz(void)
58 return cm_get_rate_dm(AGILEX_MPU_CLK);
61 unsigned int cm_get_l4_sys_free_clk_hz(void)
63 return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
66 u32 cm_get_qspi_controller_clk_hz(void)
68 return readl(socfpga_get_sysmgr_addr() +
69 SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
72 void cm_print_clock_quick_summary(void)
74 printf("MPU %10d kHz\n",
75 cm_get_rate_dm_khz(AGILEX_MPU_CLK));
76 printf("L4 Main %8d kHz\n",
77 cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
78 printf("L4 sys free %8d kHz\n",
79 cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
80 printf("L4 MP %8d kHz\n",
81 cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
82 printf("L4 SP %8d kHz\n",
83 cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
84 printf("SDMMC %8d kHz\n",
85 cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));