1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
5 * Based on original Kirkwood support which is
6 * Copyright (C) Marvell International Ltd. and its affiliates
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
15 #define UBOOT_CNTR 0 /* counter to use for uboot timer */
17 /* Timer reload and current value registers */
18 struct orion5x_tmr_val {
19 u32 reload; /* Timer reload reg */
20 u32 val; /* Timer value reg */
24 struct orion5x_tmr_registers {
25 u32 ctrl; /* Timer control reg */
27 struct orion5x_tmr_val tmr[2];
32 struct orion5x_tmr_registers *orion5x_tmr_regs =
33 (struct orion5x_tmr_registers *)ORION5X_TIMER_BASE;
36 * ARM Timers Registers Map
38 #define CNTMR_CTRL_REG (&orion5x_tmr_regs->ctrl)
39 #define CNTMR_RELOAD_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].reload)
40 #define CNTMR_VAL_REG(tmrnum) (&orion5x_tmr_regs->tmr[tmrnum].val)
43 * ARM Timers Control Register
44 * CPU_TIMERS_CTRL_REG (CTCR)
46 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
47 #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
48 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
49 #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
51 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
52 #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
53 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
54 #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
57 * ARM Timer\Watchdog Reload Register
58 * CNTMR_RELOAD_REG (TRR)
60 #define TRG_ARM_TIMER_REL_OFFS 0
61 #define TRG_ARM_TIMER_REL_MASK 0xffffffff
64 * ARM Timer\Watchdog Register
65 * CNTMR_VAL_REG (TVRG)
67 #define TVR_ARM_TIMER_OFFS 0
68 #define TVR_ARM_TIMER_MASK 0xffffffff
69 #define TVR_ARM_TIMER_MAX 0xffffffff
70 #define TIMER_LOAD_VAL 0xffffffff
72 static inline ulong read_timer(void)
74 return readl(CNTMR_VAL_REG(UBOOT_CNTR))
75 / (CONFIG_SYS_TCLK / 1000);
78 DECLARE_GLOBAL_DATA_PTR;
80 #define timestamp gd->arch.tbl
81 #define lastdec gd->arch.lastinc
83 static ulong get_timer_masked(void)
85 ulong now = read_timer();
89 timestamp += lastdec - now;
91 /* we have an overflow ... */
92 timestamp += lastdec +
93 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
100 ulong get_timer(ulong base)
102 return get_timer_masked() - base;
105 static inline ulong uboot_cntr_val(void)
107 return readl(CNTMR_VAL_REG(UBOOT_CNTR));
110 void __udelay(unsigned long usec)
115 current = uboot_cntr_val();
116 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
118 if (current < delayticks) {
119 delayticks -= current;
120 while (uboot_cntr_val() < current)
122 while ((TIMER_LOAD_VAL - delayticks) < uboot_cntr_val())
125 while (uboot_cntr_val() > (current - delayticks))
135 unsigned int cntmrctrl;
137 /* load value into timer */
138 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
139 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
141 /* enable timer in auto reload mode */
142 cntmrctrl = readl(CNTMR_CTRL_REG);
143 cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
144 cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
145 writel(cntmrctrl, CNTMR_CTRL_REG);
149 void timer_init_r(void)
151 /* init the timestamp and lastdec value */
152 lastdec = read_timer();
157 * This function is derived from PowerPC code (read timebase as long long).
158 * On ARM it just returns the timer value.
160 unsigned long long get_ticks(void)
166 * This function is derived from PowerPC code (timebase clock frequency).
167 * On ARM it returns the number of timer ticks per second.
169 ulong get_tbclk(void)
171 return (ulong)CONFIG_SYS_HZ;