drivers/pci/pci_auto.c

   1 /*
   2  * arch/powerpc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <[email protected]>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <errno.h>
  15 #include <pci.h>
  16
  17 #ifdef DEBUG
  18 #define DEBUGF(x...) printf(x)
  19 #else
  20 #define DEBUGF(x...)
  21 #endif /* DEBUG */
  22
  23 #define PCIAUTO_IDE_MODE_MASK           0x05
  24
  25 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
  26 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
  27 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  8
  28 #endif
  29
  30 /*
  31  *
  32  */
  33
  34 void pciauto_region_init(struct pci_region *res)
  35 {
  36         /*
  37          * Avoid allocating PCI resources from address 0 -- this is illegal
  38          * according to PCI 2.1 and moreover, this is known to cause Linux IDE
  39          * drivers to fail. Use a reasonable starting value of 0x1000 instead.
  40          */
  41         res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
  42 }
  43
  44 void pciauto_region_align(struct pci_region *res, pci_size_t size)
  45 {
  46         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  47 }
  48
  49 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  50         pci_addr_t *bar)
  51 {
  52         pci_addr_t addr;
  53
  54         if (!res) {
  55                 DEBUGF("No resource");
  56                 goto error;
  57         }
  58
  59         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  60
  61         if (addr - res->bus_start + size > res->size) {
  62                 DEBUGF("No room in resource");
  63                 goto error;
  64         }
  65
  66         res->bus_lower = addr + size;
  67
  68         DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
  69
  70         *bar = addr;
  71         return 0;
  72
  73  error:
  74         *bar = (pci_addr_t)-1;
  75         return -1;
  76 }
  77
  78 /*
  79  *
  80  */
  81
  82 void pciauto_setup_device(struct pci_controller *hose,
  83                           pci_dev_t dev, int bars_num,
  84                           struct pci_region *mem,
  85                           struct pci_region *prefetch,
  86                           struct pci_region *io)
  87 {
  88         u32 bar_response;
  89         pci_size_t bar_size;
  90         u16 cmdstat = 0;
  91         int bar, bar_nr = 0;
  92 #ifndef CONFIG_PCI_ENUM_ONLY
  93         pci_addr_t bar_value;
  94         struct pci_region *bar_res;
  95         int found_mem64 = 0;
  96 #endif
  97
  98         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
  99         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
 100
 101         for (bar = PCI_BASE_ADDRESS_0;
 102                 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
 103                 /* Tickle the BAR and get the response */
 104 #ifndef CONFIG_PCI_ENUM_ONLY
 105                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 106 #endif
 107                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 108
 109                 /* If BAR is not implemented go to the next BAR */
 110                 if (!bar_response)
 111                         continue;
 112
 113 #ifndef CONFIG_PCI_ENUM_ONLY
 114                 found_mem64 = 0;
 115 #endif
 116
 117                 /* Check the BAR type and set our address mask */
 118                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 119                         bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
 120                                    & 0xffff) + 1;
 121 #ifndef CONFIG_PCI_ENUM_ONLY
 122                         bar_res = io;
 123 #endif
 124
 125                         DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
 126                 } else {
 127                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 128                              PCI_BASE_ADDRESS_MEM_TYPE_64) {
 129                                 u32 bar_response_upper;
 130                                 u64 bar64;
 131
 132 #ifndef CONFIG_PCI_ENUM_ONLY
 133                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 134                                         0xffffffff);
 135 #endif
 136                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 137                                         &bar_response_upper);
 138
 139                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 140
 141                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 142 #ifndef CONFIG_PCI_ENUM_ONLY
 143                                 found_mem64 = 1;
 144 #endif
 145                         } else {
 146                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 147                         }
 148 #ifndef CONFIG_PCI_ENUM_ONLY
 149                         if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
 150                                 bar_res = prefetch;
 151                         else
 152                                 bar_res = mem;
 153 #endif
 154
 155                         DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
 156                 }
 157
 158 #ifndef CONFIG_PCI_ENUM_ONLY
 159                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
 160                         /* Write it out and update our limit */
 161                         pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
 162
 163                         if (found_mem64) {
 164                                 bar += 4;
 165 #ifdef CONFIG_SYS_PCI_64BIT
 166                                 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
 167 #else
 168                                 /*
 169                                  * If we are a 64-bit decoder then increment to the
 170                                  * upper 32 bits of the bar and force it to locate
 171                                  * in the lower 4GB of memory.
 172                                  */
 173                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 174 #endif
 175                         }
 176
 177                 }
 178 #endif
 179                 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 180                         PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 181
 182                 DEBUGF("\n");
 183
 184                 bar_nr++;
 185         }
 186
 187         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 188         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
 189                 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
 190         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 191 }
 192
 193 int pciauto_setup_rom(struct pci_controller *hose, pci_dev_t dev)
 194 {
 195         pci_addr_t bar_value;
 196         pci_size_t bar_size;
 197         u32 bar_response;
 198         u16 cmdstat = 0;
 199
 200         pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS, 0xfffffffe);
 201         pci_hose_read_config_dword(hose, dev, PCI_ROM_ADDRESS, &bar_response);
 202         if (!bar_response)
 203                 return -ENOENT;
 204
 205         bar_size = -(bar_response & ~1);
 206         DEBUGF("PCI Autoconfig: ROM, size=%#x, ", bar_size);
 207         if (pciauto_region_allocate(hose->pci_mem, bar_size, &bar_value) == 0) {
 208                 pci_hose_write_config_dword(hose, dev, PCI_ROM_ADDRESS,
 209                                             bar_value);
 210         }
 211         DEBUGF("\n");
 212         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 213         cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 214         pci_hose_write_config_word(hose, dev, PCI_COMMAND, cmdstat);
 215
 216         return 0;
 217 }
 218
 219 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 220                                          pci_dev_t dev, int sub_bus)
 221 {
 222         struct pci_region *pci_mem = hose->pci_mem;
 223         struct pci_region *pci_prefetch = hose->pci_prefetch;
 224         struct pci_region *pci_io = hose->pci_io;
 225         u16 cmdstat, prefechable_64;
 226
 227         pci_hose_read_config_word(hose, dev, PCI_COMMAND, &cmdstat);
 228         pci_hose_read_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 229                                 &prefechable_64);
 230         prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 231
 232         /* Configure bus number registers */
 233         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
 234                                    PCI_BUS(dev) - hose->first_busno);
 235         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
 236                                    sub_bus - hose->first_busno);
 237         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 238
 239         if (pci_mem) {
 240                 /* Round memory allocator to 1MB boundary */
 241                 pciauto_region_align(pci_mem, 0x100000);
 242
 243                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 244                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 245                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 246
 247                 cmdstat |= PCI_COMMAND_MEMORY;
 248         }
 249
 250         if (pci_prefetch) {
 251                 /* Round memory allocator to 1MB boundary */
 252                 pciauto_region_align(pci_prefetch, 0x100000);
 253
 254                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 255                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
 256                                         (pci_prefetch->bus_lower & 0xfff00000) >> 16);
 257                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 258 #ifdef CONFIG_SYS_PCI_64BIT
 259                         pci_hose_write_config_dword(hose, dev,
 260                                         PCI_PREF_BASE_UPPER32,
 261                                         pci_prefetch->bus_lower >> 32);
 262 #else
 263                         pci_hose_write_config_dword(hose, dev,
 264                                         PCI_PREF_BASE_UPPER32,
 265                                         0x0);
 266 #endif
 267
 268                 cmdstat |= PCI_COMMAND_MEMORY;
 269         } else {
 270                 /* We don't support prefetchable memory for now, so disable */
 271                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 272                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
 273                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
 274                         pci_hose_write_config_word(hose, dev, PCI_PREF_BASE_UPPER32, 0x0);
 275                         pci_hose_write_config_word(hose, dev, PCI_PREF_LIMIT_UPPER32, 0x0);
 276                 }
 277         }
 278
 279         if (pci_io) {
 280                 /* Round I/O allocator to 4KB boundary */
 281                 pciauto_region_align(pci_io, 0x1000);
 282
 283                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 284                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 285                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 286                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 287
 288                 cmdstat |= PCI_COMMAND_IO;
 289         }
 290
 291         /* Enable memory and I/O accesses, enable bus master */
 292         pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 293                                         cmdstat | PCI_COMMAND_MASTER);
 294 }
 295
 296 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 297                                           pci_dev_t dev, int sub_bus)
 298 {
 299         struct pci_region *pci_mem = hose->pci_mem;
 300         struct pci_region *pci_prefetch = hose->pci_prefetch;
 301         struct pci_region *pci_io = hose->pci_io;
 302
 303         /* Configure bus number registers */
 304         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
 305                                    sub_bus - hose->first_busno);
 306
 307         if (pci_mem) {
 308                 /* Round memory allocator to 1MB boundary */
 309                 pciauto_region_align(pci_mem, 0x100000);
 310
 311                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 312                                 (pci_mem->bus_lower - 1) >> 16);
 313         }
 314
 315         if (pci_prefetch) {
 316                 u16 prefechable_64;
 317
 318                 pci_hose_read_config_word(hose, dev,
 319                                         PCI_PREF_MEMORY_LIMIT,
 320                                         &prefechable_64);
 321                 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
 322
 323                 /* Round memory allocator to 1MB boundary */
 324                 pciauto_region_align(pci_prefetch, 0x100000);
 325
 326                 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
 327                                 (pci_prefetch->bus_lower - 1) >> 16);
 328                 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
 329 #ifdef CONFIG_SYS_PCI_64BIT
 330                         pci_hose_write_config_dword(hose, dev,
 331                                         PCI_PREF_LIMIT_UPPER32,
 332                                         (pci_prefetch->bus_lower - 1) >> 32);
 333 #else
 334                         pci_hose_write_config_dword(hose, dev,
 335                                         PCI_PREF_LIMIT_UPPER32,
 336                                         0x0);
 337 #endif
 338         }
 339
 340         if (pci_io) {
 341                 /* Round I/O allocator to 4KB boundary */
 342                 pciauto_region_align(pci_io, 0x1000);
 343
 344                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 345                                 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
 346                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 347                                 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
 348         }
 349 }
 350
 351 /*
 352  *
 353  */
 354
 355 void pciauto_config_init(struct pci_controller *hose)
 356 {
 357         int i;
 358
 359         hose->pci_io = hose->pci_mem = hose->pci_prefetch = NULL;
 360
 361         for (i = 0; i < hose->region_count; i++) {
 362                 switch(hose->regions[i].flags) {
 363                 case PCI_REGION_IO:
 364                         if (!hose->pci_io ||
 365                             hose->pci_io->size < hose->regions[i].size)
 366                                 hose->pci_io = hose->regions + i;
 367                         break;
 368                 case PCI_REGION_MEM:
 369                         if (!hose->pci_mem ||
 370                             hose->pci_mem->size < hose->regions[i].size)
 371                                 hose->pci_mem = hose->regions + i;
 372                         break;
 373                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
 374                         if (!hose->pci_prefetch ||
 375                             hose->pci_prefetch->size < hose->regions[i].size)
 376                                 hose->pci_prefetch = hose->regions + i;
 377                         break;
 378                 }
 379         }
 380
 381
 382         if (hose->pci_mem) {
 383                 pciauto_region_init(hose->pci_mem);
 384
 385                 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
 386                        "\t\tPhysical Memory [%llx-%llxx]\n",
 387                     (u64)hose->pci_mem->bus_start,
 388                     (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
 389                     (u64)hose->pci_mem->phys_start,
 390                     (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
 391         }
 392
 393         if (hose->pci_prefetch) {
 394                 pciauto_region_init(hose->pci_prefetch);
 395
 396                 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
 397                        "\t\tPhysical Memory [%llx-%llx]\n",
 398                     (u64)hose->pci_prefetch->bus_start,
 399                     (u64)(hose->pci_prefetch->bus_start +
 400                             hose->pci_prefetch->size - 1),
 401                     (u64)hose->pci_prefetch->phys_start,
 402                     (u64)(hose->pci_prefetch->phys_start +
 403                             hose->pci_prefetch->size - 1));
 404         }
 405
 406         if (hose->pci_io) {
 407                 pciauto_region_init(hose->pci_io);
 408
 409                 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
 410                        "\t\tPhysical Memory: [%llx-%llx]\n",
 411                     (u64)hose->pci_io->bus_start,
 412                     (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
 413                     (u64)hose->pci_io->phys_start,
 414                     (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
 415
 416         }
 417 }
 418
 419 /*
 420  * HJF: Changed this to return int. I think this is required
 421  * to get the correct result when scanning bridges
 422  */
 423 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 424 {
 425         unsigned int sub_bus = PCI_BUS(dev);
 426         unsigned short class;
 427         unsigned char prg_iface;
 428         int n;
 429
 430         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 431
 432         switch (class) {
 433         case PCI_CLASS_BRIDGE_PCI:
 434                 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n",
 435                        PCI_DEV(dev));
 436
 437                 pciauto_setup_device(hose, dev, 2, hose->pci_mem,
 438                         hose->pci_prefetch, hose->pci_io);
 439
 440 #ifdef CONFIG_DM_PCI
 441                 n = dm_pci_hose_probe_bus(hose, dev);
 442                 if (n < 0)
 443                         return n;
 444                 sub_bus = (unsigned int)n;
 445 #else
 446                 /* Passing in current_busno allows for sibling P2P bridges */
 447                 hose->current_busno++;
 448                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 449                 /*
 450                  * need to figure out if this is a subordinate bridge on the bus
 451                  * to be able to properly set the pri/sec/sub bridge registers.
 452                  */
 453                 n = pci_hose_scan_bus(hose, hose->current_busno);
 454
 455                 /* figure out the deepest we've gone for this leg */
 456                 sub_bus = max((unsigned int)n, sub_bus);
 457                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 458
 459                 sub_bus = hose->current_busno;
 460 #endif
 461                 break;
 462
 463         case PCI_CLASS_STORAGE_IDE:
 464                 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
 465                 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
 466                         DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
 467                         return sub_bus;
 468                 }
 469
 470                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 471                         hose->pci_prefetch, hose->pci_io);
 472                 break;
 473
 474         case PCI_CLASS_BRIDGE_CARDBUS:
 475                 /*
 476                  * just do a minimal setup of the bridge,
 477                  * let the OS take care of the rest
 478                  */
 479                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 480                         hose->pci_prefetch, hose->pci_io);
 481
 482                 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 483                         PCI_DEV(dev));
 484
 485 #ifndef CONFIG_DM_PCI
 486                 hose->current_busno++;
 487 #endif
 488                 break;
 489
 490 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
 491         case PCI_CLASS_BRIDGE_OTHER:
 492                 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
 493                        PCI_DEV(dev));
 494                 break;
 495 #endif
 496 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
 497         case PCI_CLASS_BRIDGE_OTHER:
 498                 /*
 499                  * The host/PCI bridge 1 seems broken in 8349 - it presents
 500                  * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
 501                  * device claiming resources io/mem/irq.. we only allow for
 502                  * the PIMMR window to be allocated (BAR0 - 1MB size)
 503                  */
 504                 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
 505                 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 506                         hose->pci_prefetch, hose->pci_io);
 507                 break;
 508 #endif
 509
 510         case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
 511                 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
 512
 513         default:
 514                 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
 515                         hose->pci_prefetch, hose->pci_io);
 516                 break;
 517         }
 518
 519         return sub_bus;
 520 }