1 // SPDX-License-Identifier: GPL-2.0+
3 * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/projects/i2c)
6 * (C) Copyright Peter Korsgaard <peter@korsgaard.com>
8 * Copyright (C) 2020 SiFive, Inc.
9 * Pragnesh Patel <pragnesh.patel@sifive.com>
11 * Support for the GRLIB port of the controller by
12 * Andreas Larsson <andreas@gaisler.com>
16 #include <asm/global_data.h>
20 #include <dm/device_compat.h>
23 #include <linux/compat.h>
24 #include <linux/log2.h>
25 #include <linux/delay.h>
28 #define OCI2C_PRELOW 0
29 #define OCI2C_PREHIGH 1
30 #define OCI2C_CONTROL 2
32 #define OCI2C_CMD 4 /* write only */
33 #define OCI2C_STATUS 4 /* read only, same address as OCI2C_CMD */
35 #define OCI2C_CTRL_IEN 0x40
36 #define OCI2C_CTRL_EN 0x80
38 #define OCI2C_CMD_START 0x91
39 #define OCI2C_CMD_STOP 0x41
40 #define OCI2C_CMD_READ 0x21
41 #define OCI2C_CMD_WRITE 0x11
42 #define OCI2C_CMD_READ_ACK 0x21
43 #define OCI2C_CMD_READ_NACK 0x29
44 #define OCI2C_CMD_IACK 0x01
46 #define OCI2C_STAT_IF 0x01
47 #define OCI2C_STAT_TIP 0x02
48 #define OCI2C_STAT_ARBLOST 0x20
49 #define OCI2C_STAT_BUSY 0x40
50 #define OCI2C_STAT_NACK 0x80
61 #define OCORES_FLAG_BROKEN_IRQ BIT(1) /* Broken IRQ for FU540-C000 SoC */
63 struct ocores_i2c_bus {
71 int state; /* see STATE_ */
75 void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
76 u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
79 DECLARE_GLOBAL_DATA_PTR;
81 /* Boolean attribute values */
87 static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value)
89 writeb(value, i2c->base + (reg << i2c->reg_shift));
92 static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value)
94 writew(value, i2c->base + (reg << i2c->reg_shift));
97 static void oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value)
99 writel(value, i2c->base + (reg << i2c->reg_shift));
102 static void oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value)
104 out_be16(i2c->base + (reg << i2c->reg_shift), value);
107 static void oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value)
109 out_be32(i2c->base + (reg << i2c->reg_shift), value);
112 static inline u8 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg)
114 return readb(i2c->base + (reg << i2c->reg_shift));
117 static inline u8 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg)
119 return readw(i2c->base + (reg << i2c->reg_shift));
122 static inline u8 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg)
124 return readl(i2c->base + (reg << i2c->reg_shift));
127 static inline u8 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg)
129 return in_be16(i2c->base + (reg << i2c->reg_shift));
132 static inline u8 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg)
134 return in_be32(i2c->base + (reg << i2c->reg_shift));
137 static inline void oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value)
139 i2c->setreg(i2c, reg, value);
142 static inline u8 oc_getreg(struct ocores_i2c_bus *i2c, int reg)
144 return i2c->getreg(i2c, reg);
147 static inline u8 i2c_8bit_addr_from_msg(const struct i2c_msg *msg)
149 return (msg->addr << 1) | (msg->flags & I2C_M_RD ? 1 : 0);
152 static void ocores_process(struct ocores_i2c_bus *i2c, u8 stat)
154 struct i2c_msg *msg = i2c->msg;
156 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
157 /* stop has been sent */
158 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
163 if (stat & OCI2C_STAT_ARBLOST) {
164 i2c->state = STATE_ERROR;
165 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
169 if (i2c->state == STATE_START || i2c->state == STATE_WRITE) {
171 (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
173 if (stat & OCI2C_STAT_NACK) {
174 i2c->state = STATE_ERROR;
175 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
179 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
183 if (i2c->pos == msg->len) {
189 if (i2c->nmsgs) { /* end? */
191 if (!(msg->flags & I2C_M_NOSTART)) {
192 u8 addr = i2c_8bit_addr_from_msg(msg);
194 i2c->state = STATE_START;
196 oc_setreg(i2c, OCI2C_DATA, addr);
197 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
200 i2c->state = (msg->flags & I2C_M_RD)
201 ? STATE_READ : STATE_WRITE;
203 i2c->state = STATE_DONE;
204 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
209 if (i2c->state == STATE_READ) {
210 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len - 1) ?
211 OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
213 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
214 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
218 static irqreturn_t ocores_isr(int irq, void *dev_id)
220 struct ocores_i2c_bus *i2c = dev_id;
221 u8 stat = oc_getreg(i2c, OCI2C_STATUS);
223 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ) {
224 if ((stat & OCI2C_STAT_IF) && !(stat & OCI2C_STAT_BUSY))
226 } else if (!(stat & OCI2C_STAT_IF)) {
229 ocores_process(i2c, stat);
235 * Wait until something change in a given register
236 * @i2c: ocores I2C device instance
237 * @reg: register to query
238 * @mask: bitmask to apply on register value
239 * @val: expected result
240 * @msec: timeout in msec
242 * Timeout is necessary to avoid to stay here forever when the chip
243 * does not answer correctly.
245 * Return: 0 on success, -ETIMEDOUT on timeout
247 static int ocores_wait(struct ocores_i2c_bus *i2c,
248 int reg, u8 mask, u8 val,
249 const unsigned long msec)
254 u8 status = oc_getreg(i2c, reg);
256 if ((status & mask) == val)
262 if (count == (1000 * msec))
269 * Wait until is possible to process some data
270 * @i2c: ocores I2C device instance
272 * Used when the device is in polling mode (interrupts disabled).
274 * Return: 0 on success, -ETIMEDOUT on timeout
276 static int ocores_poll_wait(struct ocores_i2c_bus *i2c)
281 if (i2c->state == STATE_DONE || i2c->state == STATE_ERROR) {
282 /* transfer is over */
283 mask = OCI2C_STAT_BUSY;
285 /* on going transfer */
286 mask = OCI2C_STAT_TIP;
288 * We wait for the data to be transferred (8bit),
289 * then we start polling on the ACK/NACK bit
291 udelay((8 * 1000) / i2c->bus_clk_khz);
295 * once we are here we expect to get the expected result immediately
296 * so if after 1ms we timeout then something is broken.
298 err = ocores_wait(i2c, OCI2C_STATUS, mask, 0, 1);
300 debug("%s: STATUS timeout, bit 0x%x did not clear in 1ms\n",
306 * It handles an IRQ-less transfer
307 * @i2c: ocores I2C device instance
309 * Even if IRQ are disabled, the I2C OpenCore IP behavior is exactly the same
310 * (only that IRQ are not produced). This means that we can re-use entirely
311 * ocores_isr(), we just add our polling code around it.
313 * It can run in atomic context
315 static void ocores_process_polling(struct ocores_i2c_bus *i2c)
321 err = ocores_poll_wait(i2c);
323 i2c->state = STATE_ERROR;
327 ret = ocores_isr(-1, i2c);
328 if (ret == IRQ_NONE) {
329 break; /* all messages have been transferred */
331 if (i2c->flags & OCORES_FLAG_BROKEN_IRQ)
332 if (i2c->state == STATE_DONE)
338 static int ocores_xfer_core(struct ocores_i2c_bus *i2c,
339 struct i2c_msg *msgs, int num, bool polling)
343 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
346 oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~OCI2C_CTRL_IEN);
351 i2c->state = STATE_START;
353 oc_setreg(i2c, OCI2C_DATA, i2c_8bit_addr_from_msg(i2c->msg));
354 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
357 ocores_process_polling(i2c);
359 return (i2c->state == STATE_DONE) ? num : -EIO;
362 static int ocores_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
364 struct ocores_i2c_bus *bus = dev_get_priv(dev);
367 debug("i2c_xfer: %d messages\n", nmsgs);
369 ret = ocores_xfer_core(bus, msg, nmsgs, 1);
372 debug("i2c_write: error sending\n");
379 static int ocores_i2c_enable_clk(struct udevice *dev)
381 struct ocores_i2c_bus *bus = dev_get_priv(dev);
385 ret = clk_get_by_index(dev, 0, &bus->clk);
389 ret = clk_enable(&bus->clk);
393 clk_rate = clk_get_rate(&bus->clk);
397 bus->ip_clk_khz = clk_rate / 1000;
404 static int ocores_init(struct udevice *dev, struct ocores_i2c_bus *bus)
408 u8 ctrl = oc_getreg(bus, OCI2C_CONTROL);
410 /* make sure the device is disabled */
411 ctrl &= ~(OCI2C_CTRL_EN | OCI2C_CTRL_IEN);
412 oc_setreg(bus, OCI2C_CONTROL, ctrl);
414 prescale = (bus->ip_clk_khz / (5 * bus->bus_clk_khz)) - 1;
415 prescale = clamp(prescale, 0, 0xffff);
417 diff = bus->ip_clk_khz / (5 * (prescale + 1)) - bus->bus_clk_khz;
418 if (abs(diff) > bus->bus_clk_khz / 10) {
419 debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
420 bus->ip_clk_khz, bus->bus_clk_khz);
424 oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
425 oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
427 /* Init the device */
428 oc_setreg(bus, OCI2C_CMD, OCI2C_CMD_IACK);
429 oc_setreg(bus, OCI2C_CONTROL, ctrl | OCI2C_CTRL_EN);
435 * Read and write functions for the GRLIB port of the controller. Registers are
436 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
437 * register. The subsequent registers have their offsets decreased accordingly.
439 static u8 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg)
444 if (reg != OCI2C_PRELOW)
446 rd = in_be32(i2c->base + (rreg << i2c->reg_shift));
447 if (reg == OCI2C_PREHIGH)
448 return (u8)(rd >> 8);
453 static void oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value)
458 if (reg != OCI2C_PRELOW)
460 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
461 curr = in_be32(i2c->base + (rreg << i2c->reg_shift));
462 if (reg == OCI2C_PRELOW)
463 wr = (curr & 0xff00) | value;
465 wr = (((u32)value) << 8) | (curr & 0xff);
469 out_be32(i2c->base + (rreg << i2c->reg_shift), wr);
472 static int ocores_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
476 struct ocores_i2c_bus *bus = dev_get_priv(dev);
479 speed = speed / 1000;
481 prescale = (bus->ip_clk_khz / (5 * speed)) - 1;
482 prescale = clamp(prescale, 0, 0xffff);
484 diff = bus->ip_clk_khz / (5 * (prescale + 1)) - speed;
485 if (abs(diff) > speed / 10) {
486 debug("Unsupported clock settings: core: %d KHz, bus: %d KHz\n",
487 bus->ip_clk_khz, speed);
491 oc_setreg(bus, OCI2C_PRELOW, prescale & 0xff);
492 oc_setreg(bus, OCI2C_PREHIGH, prescale >> 8);
494 bus->bus_clk_khz = speed;
498 int ocores_i2c_get_bus_speed(struct udevice *dev)
500 struct ocores_i2c_bus *bus = dev_get_priv(dev);
502 return (bus->bus_clk_khz * 1000);
505 static const struct dm_i2c_ops ocores_i2c_ops = {
506 .xfer = ocores_i2c_xfer,
507 .set_bus_speed = ocores_i2c_set_bus_speed,
508 .get_bus_speed = ocores_i2c_get_bus_speed,
511 static int ocores_i2c_probe(struct udevice *dev)
513 struct ocores_i2c_bus *bus = dev_get_priv(dev);
514 bool clock_frequency_present;
516 u32 clock_frequency_khz;
519 bus->base = (void __iomem *)devfdt_get_addr(dev);
521 if (dev_read_u32(dev, "reg-shift", &bus->reg_shift)) {
522 /* no 'reg-shift', check for deprecated 'regstep' */
523 ret = dev_read_u32(dev, "regstep", &val);
526 "missing both reg-shift and regstep property: %d\n", ret);
529 bus->reg_shift = ilog2(val);
531 "regstep property deprecated, use reg-shift\n");
535 if (dev_read_u32(dev, "clock-frequency", &val)) {
536 bus->bus_clk_khz = 100;
537 clock_frequency_present = FALSE;
539 bus->bus_clk_khz = val / 1000;
540 clock_frequency_khz = val / 1000;
541 clock_frequency_present = TRUE;
544 ret = ocores_i2c_enable_clk(dev);
548 if (bus->ip_clk_khz == 0) {
549 if (dev_read_u32(dev, "opencores,ip-clock-frequency", &val)) {
550 if (!clock_frequency_present) {
552 "Missing required parameter 'opencores,ip-clock-frequency'\n");
553 clk_disable(&bus->clk);
557 bus->ip_clk_khz = clock_frequency_khz;
559 "Deprecated usage of the 'clock-frequency' property, please update to 'opencores,ip-clock-frequency'\n");
561 bus->ip_clk_khz = val / 1000;
562 if (clock_frequency_present)
563 bus->bus_clk_khz = clock_frequency_khz;
567 bus->reg_io_width = dev_read_u32_default(dev, "reg-io-width", 1);
569 if (dev_get_driver_data(dev) == TYPE_GRLIB) {
570 debug("GRLIB variant of i2c-ocores\n");
571 bus->setreg = oc_setreg_grlib;
572 bus->getreg = oc_getreg_grlib;
575 if (!bus->setreg || !bus->getreg) {
576 bool be = (cpu_to_be32(0x12345678) == 0x12345678);
578 switch (bus->reg_io_width) {
580 bus->setreg = oc_setreg_8;
581 bus->getreg = oc_getreg_8;
585 bus->setreg = be ? oc_setreg_16be : oc_setreg_16;
586 bus->getreg = be ? oc_getreg_16be : oc_getreg_16;
590 bus->setreg = be ? oc_setreg_32be : oc_setreg_32;
591 bus->getreg = be ? oc_getreg_32be : oc_getreg_32;
595 debug("Unsupported I/O width (%d)\n",
603 * Set OCORES_FLAG_BROKEN_IRQ to enable workaround for
604 * FU540-C000 SoC in polling mode.
605 * Since the SoC does have an interrupt, its DT has an interrupt
606 * property - But this should be bypassed as the IRQ logic in this
610 if (device_is_compatible(dev, "sifive,fu540-c000-i2c"))
611 bus->flags |= OCORES_FLAG_BROKEN_IRQ;
613 ret = ocores_init(dev, bus);
620 clk_disable(&bus->clk);
624 static const struct udevice_id ocores_i2c_ids[] = {
625 { .compatible = "opencores,i2c-ocores", .data = TYPE_OCORES },
626 { .compatible = "aeroflexgaisler,i2cmst", .data = TYPE_GRLIB },
627 { .compatible = "sifive,fu540-c000-i2c" },
628 { .compatible = "sifive,i2c0" },
631 U_BOOT_DRIVER(i2c_ocores) = {
632 .name = "i2c_ocores",
634 .of_match = ocores_i2c_ids,
635 .probe = ocores_i2c_probe,
636 .priv_auto = sizeof(struct ocores_i2c_bus),
637 .ops = &ocores_i2c_ops,