2 * Copyright 2013 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale Vybrid vf610twr board.
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
16 #define CONFIG_SYS_FSL_CLK
18 #define CONFIG_MACH_TYPE 4146
20 #define CONFIG_SKIP_LOWLEVEL_INIT
22 /* Enable passing of ATAGs */
23 #define CONFIG_CMDLINE_TAG
25 #define CONFIG_CMD_FUSE
26 #ifdef CONFIG_CMD_FUSE
27 #define CONFIG_MXC_OCOTP
30 /* Size of malloc() pool */
31 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
33 /* Allow to overwrite serial and ethaddr */
34 #define CONFIG_ENV_OVERWRITE
35 #define CONFIG_BAUDRATE 115200
38 #define CONFIG_CMD_NAND
39 #define CONFIG_CMD_NAND_TRIMFFS
40 #define CONFIG_SYS_NAND_ONFI_DETECTION
42 #ifdef CONFIG_CMD_NAND
43 #define CONFIG_SYS_MAX_NAND_DEVICE 1
44 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
47 #define CONFIG_CMD_UBIFS
51 /* Dynamic MTD partition support */
52 #define CONFIG_CMD_MTDPARTS
53 #define CONFIG_MTD_PARTITIONS
54 #define CONFIG_MTD_DEVICE
55 #define MTDIDS_DEFAULT "nand0=fsl_nfc"
56 #define MTDPARTS_DEFAULT "mtdparts=fsl_nfc:" \
65 #define CONFIG_FSL_ESDHC
66 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
67 #define CONFIG_SYS_FSL_ESDHC_NUM 1
69 #define CONFIG_GENERIC_MMC
71 #define CONFIG_FEC_MXC
73 #define IMX_FEC_BASE ENET_BASE_ADDR
74 #define CONFIG_FEC_XCV_TYPE RMII
75 #define CONFIG_FEC_MXC_PHYADDR 0
77 #define CONFIG_PHY_MICREL
81 #ifdef CONFIG_FSL_QSPI
82 #define FSL_QSPI_FLASH_SIZE (1 << 24)
83 #define FSL_QSPI_FLASH_NUM 2
84 #define CONFIG_SYS_FSL_QSPI_LE
88 #define CONFIG_SYS_I2C
89 #define CONFIG_SYS_I2C_MXC
90 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
91 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
92 #define CONFIG_SYS_SPD_BUS_NUM 0
95 #define CONFIG_SYS_LOAD_ADDR 0x82000000
97 /* We boot from the gfxRAM area of the OCRAM. */
98 #define CONFIG_SYS_TEXT_BASE 0x3f408000
99 #define CONFIG_BOARD_SIZE_LIMIT 524288
102 * We do have 128MB of memory on the Vybrid Tower board. Leave the last
103 * 16MB alone to avoid conflicts with Cortex-M4 firmwares running from
104 * DDR3. Hence, limit the memory range for image processing to 112MB
105 * using bootm_size. All of the following must be within this range.
106 * We have the default load at 32MB into DDR (for the kernel), FDT at
107 * 64MB and the ramdisk 512KB above that (allowing for hopefully never
108 * seen large trees). This allows a reasonable split between ramdisk
109 * and kernel size, where the ram disk can be a bit larger.
111 #define MEM_LAYOUT_ENV_SETTINGS \
112 "bootm_size=0x07000000\0" \
113 "loadaddr=0x82000000\0" \
114 "kernel_addr_r=0x82000000\0" \
115 "fdt_addr=0x84000000\0" \
116 "fdt_addr_r=0x84000000\0" \
117 "rdaddr=0x84080000\0" \
118 "ramdisk_addr_r=0x84080000\0"
120 #define CONFIG_EXTRA_ENV_SETTINGS \
121 MEM_LAYOUT_ENV_SETTINGS \
122 "script=boot.scr\0" \
125 "fdt_file=vf610-twr.dtb\0" \
128 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
130 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
131 "update_sd_firmware_filename=u-boot.imx\0" \
132 "update_sd_firmware=" \
133 "if test ${ip_dyn} = yes; then " \
134 "setenv get_cmd dhcp; " \
136 "setenv get_cmd tftp; " \
138 "if mmc dev ${mmcdev}; then " \
139 "if ${get_cmd} ${update_sd_firmware_filename}; then " \
140 "setexpr fw_sz ${filesize} / 0x200; " \
141 "setexpr fw_sz ${fw_sz} + 1; " \
142 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \
145 "mmcargs=setenv bootargs console=${console},${baudrate} " \
146 "root=${mmcroot}\0" \
148 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
149 "bootscript=echo Running bootscript from mmc ...; " \
151 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
152 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
153 "mmcboot=echo Booting from mmc ...; " \
155 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
156 "if run loadfdt; then " \
157 "bootz ${loadaddr} - ${fdt_addr}; " \
159 "if test ${boot_fdt} = try; then " \
162 "echo WARN: Cannot load the DT; " \
168 "netargs=setenv bootargs console=${console},${baudrate} " \
170 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
171 "netboot=echo Booting from net ...; " \
173 "if test ${ip_dyn} = yes; then " \
174 "setenv get_cmd dhcp; " \
176 "setenv get_cmd tftp; " \
178 "${get_cmd} ${image}; " \
179 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
180 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
181 "bootz ${loadaddr} - ${fdt_addr}; " \
183 "if test ${boot_fdt} = try; then " \
186 "echo WARN: Cannot load the DT; " \
193 #define CONFIG_BOOTCOMMAND \
194 "mmc dev ${mmcdev}; if mmc rescan; then " \
195 "if run loadbootscript; then " \
198 "if run loadimage; then " \
200 "else run netboot; " \
203 "else run netboot; fi"
205 /* Miscellaneous configurable options */
206 #define CONFIG_SYS_LONGHELP /* undef to save memory */
207 #undef CONFIG_AUTO_COMPLETE
208 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
209 #define CONFIG_SYS_PBSIZE \
210 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
211 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
212 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
214 #define CONFIG_SYS_MEMTEST_START 0x80010000
215 #define CONFIG_SYS_MEMTEST_END 0x87C00000
219 * The stack sizes are set up in start.S using the settings below
221 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
223 /* Physical memory map */
224 #define CONFIG_NR_DRAM_BANKS 1
225 #define PHYS_SDRAM (0x80000000)
226 #define PHYS_SDRAM_SIZE (128 * 1024 * 1024)
228 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
229 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
230 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
232 #define CONFIG_SYS_INIT_SP_OFFSET \
233 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
234 #define CONFIG_SYS_INIT_SP_ADDR \
235 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
237 /* FLASH and environment organization */
238 #define CONFIG_SYS_NO_FLASH
240 #ifdef CONFIG_ENV_IS_IN_MMC
241 #define CONFIG_ENV_SIZE (8 * 1024)
243 #define CONFIG_ENV_OFFSET (12 * 64 * 1024)
244 #define CONFIG_SYS_MMC_ENV_DEV 0
247 #ifdef CONFIG_ENV_IS_IN_NAND
248 #define CONFIG_ENV_SIZE (64 * 2048)
249 #define CONFIG_ENV_SECT_SIZE (64 * 2048)
250 #define CONFIG_ENV_RANGE (512 * 1024)
251 #define CONFIG_ENV_OFFSET 0x180000