1 // SPDX-License-Identifier: GPL-2.0+
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
5 * Keith Outwater, keith_outwater@mvis.com
7 * Copyright (c) 2019 SED Systems, a division of Calian Ltd.
11 * Configuration support for Xilinx Virtex2 devices. Based
12 * on spartan2.c (Rich Ireland, rireland@enterasys.com).
18 #include <linux/delay.h>
25 #define PRINTF(fmt, args...) printf(fmt, ##args)
27 #define PRINTF(fmt, args...)
31 * If the SelectMap interface can be overrun by the processor, define
32 * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
33 * configuration file and add board-specific support for checking BUSY status.
34 * By default, assume that the SelectMap interface cannot be overrun.
36 #ifndef CONFIG_SYS_FPGA_CHECK_BUSY
37 #undef CONFIG_SYS_FPGA_CHECK_BUSY
40 #ifndef CONFIG_FPGA_DELAY
41 #define CONFIG_FPGA_DELAY()
45 * Check for errors during configuration by default
47 #ifndef CONFIG_SYS_FPGA_CHECK_ERROR
48 #define CONFIG_SYS_FPGA_CHECK_ERROR
52 * The default timeout in mS for INIT_B to deassert after PROG_B has
53 * been deasserted. Per the latest Virtex II Handbook (page 347), the
54 * max time from PORG_B deassertion to INIT_B deassertion is 4uS per
55 * data frame for the XC2V8000. The XC2V8000 has 2860 data frames
56 * which yields 11.44 mS. So let's make it bigger in order to handle
57 * an XC2V1000, if anyone can ever get ahold of one.
59 #ifndef CONFIG_SYS_FPGA_WAIT_INIT
60 #define CONFIG_SYS_FPGA_WAIT_INIT CONFIG_SYS_HZ / 2 /* 500 ms */
64 * The default timeout for waiting for BUSY to deassert during configuration.
65 * This is normally not necessary since for most reasonable configuration
66 * clock frequencies (i.e. 66 MHz or less), BUSY monitoring is unnecessary.
68 #ifndef CONFIG_SYS_FPGA_WAIT_BUSY
69 #define CONFIG_SYS_FPGA_WAIT_BUSY CONFIG_SYS_HZ / 200 /* 5 ms*/
72 /* Default timeout for waiting for FPGA to enter operational mode after
73 * configuration data has been written.
75 #ifndef CONFIG_SYS_FPGA_WAIT_CONFIG
76 #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ / 5 /* 200 ms */
79 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
80 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
82 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
83 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
85 static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize,
86 bitstream_type bstype, int flags)
88 int ret_val = FPGA_FAIL;
90 switch (desc->iface) {
92 PRINTF("%s: Launching Slave Serial Load\n", __func__);
93 ret_val = virtex2_ss_load(desc, buf, bsize);
97 PRINTF("%s: Launching Slave Parallel Load\n", __func__);
98 ret_val = virtex2_ssm_load(desc, buf, bsize);
102 printf("%s: Unsupported interface type, %d\n",
103 __func__, desc->iface);
108 static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
110 int ret_val = FPGA_FAIL;
112 switch (desc->iface) {
114 PRINTF("%s: Launching Slave Serial Dump\n", __func__);
115 ret_val = virtex2_ss_dump(desc, buf, bsize);
119 PRINTF("%s: Launching Slave Parallel Dump\n", __func__);
120 ret_val = virtex2_ssm_dump(desc, buf, bsize);
124 printf("%s: Unsupported interface type, %d\n",
125 __func__, desc->iface);
130 static int virtex2_info(xilinx_desc *desc)
136 * Virtex-II Slave SelectMap or Serial configuration loader. Configuration
138 * 1. Set the FPGA's PROG_B line low.
139 * 2. Set the FPGA's PROG_B line high. Wait for INIT_B to go high.
140 * 3. Write data to the SelectMap port. If INIT_B goes low at any time
141 * this process, a configuration error (most likely CRC failure) has
142 * ocurred. At this point a status word may be read from the
143 * SelectMap interface to determine the source of the problem (You
144 * could, for instance, put this in your 'abort' function handler).
145 * 4. After all data has been written, test the state of the FPGA
146 * INIT_B and DONE lines. If both are high, configuration has
147 * succeeded. Congratulations!
149 static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
153 PRINTF("%s:%d: Start with interface functions @ 0x%p\n",
154 __func__, __LINE__, fn);
157 printf("%s:%d: NULL Interface function table!\n",
162 /* Gotta split this one up (so the stack won't blow??) */
163 PRINTF("%s:%d: Function Table:\n"
171 &fn, fn, fn->pre, fn->pgm, fn->init, fn->err);
172 PRINTF(" clock 0x%p\n"
180 fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata,
181 fn->busy, fn->abort, fn->post);
183 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
184 printf("Initializing FPGA Device %d...\n", cookie);
187 * Run the pre configuration function if there is one.
193 * Assert the program line. The minimum pulse width for
194 * Virtex II devices is 300 nS (Tprogram parameter in datasheet).
195 * There is no maximum value for the pulse width. Check to make
196 * sure that INIT_B goes low after assertion of PROG_B
198 (*fn->pgm)(true, true, cookie);
202 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
203 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to assert.\n",
204 __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
205 (*fn->abort)(cookie);
208 } while (!(*fn->init)(cookie));
210 (*fn->pgm)(false, true, cookie);
213 (*fn->clk)(true, true, cookie);
216 * Start a timer and wait for INIT_B to go high
221 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_INIT) {
222 printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
223 __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_INIT);
224 (*fn->abort)(cookie);
227 } while ((*fn->init)(cookie) && (*fn->busy)(cookie));
230 (*fn->wr)(true, true, cookie);
232 (*fn->cs)(true, true, cookie);
238 static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
241 int ret_val = FPGA_SUCCESS;
246 * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
250 (*fn->cs)(false, true, cookie);
252 (*fn->wr)(false, true, cookie);
254 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
259 * Check for successful configuration. FPGA INIT_B and DONE
260 * should both be high upon successful configuration. Continue pulsing
261 * clock with data set to all ones until DONE is asserted and for 8
262 * clock cycles afterwards.
266 if ((*fn->done)(cookie) == FPGA_SUCCESS &&
267 !((*fn->init)(cookie))) {
272 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_CONFIG) {
273 printf("%s:%d: ** Timeout after %d ticks waiting for DONE to assert and INIT to deassert\n",
274 __func__, __LINE__, CONFIG_SYS_FPGA_WAIT_CONFIG);
275 (*fn->abort)(cookie);
280 unsigned char dummy = 0xff;
281 (*fn->wbulkdata)(&dummy, 1, true, cookie);
283 (*fn->wdata)(0xff, true, cookie);
285 (*fn->clk)(false, true, cookie);
287 (*fn->clk)(true, true, cookie);
291 if (ret_val == FPGA_SUCCESS) {
292 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
293 printf("Initialization of FPGA device %d complete\n", cookie);
296 * Run the post configuration function if there is one.
301 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
302 printf("** Initialization of FPGA device %d FAILED\n",
309 static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
311 int ret_val = FPGA_FAIL;
312 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
313 size_t bytecount = 0;
314 unsigned char *data = (unsigned char *)buf;
315 int cookie = desc->cookie;
317 ret_val = virtex2_slave_pre(fn, cookie);
318 if (ret_val != FPGA_SUCCESS)
322 * Load the data byte by byte
324 while (bytecount < bsize) {
325 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
327 (*fn->abort)(cookie);
332 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
333 PRINTF("%s:%d:done went active early, bytecount = %d\n",
334 __func__, __LINE__, bytecount);
338 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
339 if ((*fn->init)(cookie)) {
340 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
342 printf("%zu = buffer offset, %zu = buffer size\n",
344 (*fn->abort)(cookie);
349 (*fn->wdata)(data[bytecount++], true, cookie);
353 * Cycle the clock pin
355 (*fn->clk)(false, true, cookie);
357 (*fn->clk)(true, true, cookie);
359 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
361 while ((*fn->busy)(cookie)) {
362 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT_BUSY) {
363 printf("%s:%d: ** Timeout after %d ticks waiting for BUSY to deassert\n",
365 CONFIG_SYS_FPGA_WAIT_BUSY);
366 (*fn->abort)(cookie);
372 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
373 if (bytecount % (bsize / 40) == 0)
378 return virtex2_slave_post(fn, cookie);
382 * Read the FPGA configuration data
384 static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
386 int ret_val = FPGA_FAIL;
387 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
390 unsigned char *data = (unsigned char *)buf;
391 size_t bytecount = 0;
392 int cookie = desc->cookie;
394 printf("Starting Dump of FPGA Device %d...\n", cookie);
396 (*fn->cs)(true, true, cookie);
397 (*fn->clk)(true, true, cookie);
399 while (bytecount < bsize) {
400 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
402 (*fn->abort)(cookie);
407 * Cycle the clock and read the data
409 (*fn->clk)(false, true, cookie);
410 (*fn->clk)(true, true, cookie);
411 (*fn->rdata)(&data[bytecount++], cookie);
412 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
413 if (bytecount % (bsize / 40) == 0)
419 * Deassert CS_B and cycle the clock to deselect the device.
421 (*fn->cs)(false, false, cookie);
422 (*fn->clk)(false, true, cookie);
423 (*fn->clk)(true, true, cookie);
425 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
430 printf("%s:%d: NULL Interface function table!\n",
436 static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
438 int ret_val = FPGA_FAIL;
439 xilinx_virtex2_slave_fns *fn = desc->iface_fns;
440 unsigned char *data = (unsigned char *)buf;
441 int cookie = desc->cookie;
443 ret_val = virtex2_slave_pre(fn, cookie);
444 if (ret_val != FPGA_SUCCESS)
448 /* Load the data in a single chunk */
449 (*fn->wbulkdata)(data, bsize, true, cookie);
451 size_t bytecount = 0;
454 * Load the data bit by bit
456 while (bytecount < bsize) {
457 unsigned char curr_data = data[bytecount++];
460 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
462 (*fn->abort) (cookie);
467 if ((*fn->done)(cookie) == FPGA_SUCCESS) {
468 PRINTF("%s:%d:done went active early, bytecount = %d\n",
469 __func__, __LINE__, bytecount);
473 #ifdef CONFIG_SYS_FPGA_CHECK_ERROR
474 if ((*fn->init)(cookie)) {
475 printf("\n%s:%d: ** Error: INIT asserted during configuration\n",
477 printf("%zu = buffer offset, %zu = buffer size\n",
479 (*fn->abort)(cookie);
484 for (bit = 7; bit >= 0; --bit) {
485 unsigned char curr_bit = (curr_data >> bit) & 1;
486 (*fn->wdata)(curr_bit, true, cookie);
488 (*fn->clk)(false, true, cookie);
490 (*fn->clk)(true, true, cookie);
493 /* Slave serial never uses a busy pin */
495 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
496 if (bytecount % (bsize / 40) == 0)
502 return virtex2_slave_post(fn, cookie);
505 static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
507 printf("%s: Slave Serial Dumping is unsupported\n", __func__);
511 /* vim: set ts=4 tw=78: */
513 struct xilinx_fpga_op virtex2_op = {
514 .load = virtex2_load,
515 .dump = virtex2_dump,
516 .info = virtex2_info,