1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2017-2019, 2021 NXP
5 * Peng Fan <peng.fan@nxp.com>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/global_data.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-imx/hab.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/syscounter.h>
21 #include <asm/ptrace.h>
22 #include <asm/armv8/mmu.h>
23 #include <dm/uclass.h>
24 #include <dm/device.h>
25 #include <efi_loader.h>
27 #include <env_internal.h>
29 #include <fdt_support.h>
33 #include <linux/bitops.h>
34 #include <linux/bitfield.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 #if defined(CONFIG_IMX_HAB)
39 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
47 #ifdef CONFIG_SPL_BUILD
48 struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
49 unsigned long freq = readl(&sctr->cntfid0);
51 /* Update with accurate clock frequency */
52 asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
54 clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
55 SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
64 void enable_tzc380(void)
66 struct iomuxc_gpr_base_regs *gpr =
67 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
69 /* Enable TZASC and lock setting */
70 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
71 setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
74 * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
75 * order to avoid AXI Bus errors when GPU is in use
77 setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
80 * imx8mn and imx8mp implements the lock bit for
81 * TZASC_ID_SWAP_BYPASS, enable it to lock settings
83 setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
86 * set Region 0 attribute to allow secure and non-secure
87 * read/write permission. Found some masters like usb dwc3
88 * controllers can't work with secure memory.
90 writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
93 void set_wdog_reset(struct wdog_regs *wdog)
96 * Output WDOG_B signal to reset external pmic or POR_B decided by
97 * the board design. Without external reset, the peripherals/DDR/
98 * PMIC are not reset, that may cause system working abnormal.
99 * WDZST bit is write-once only bit. Align this bit in kernel,
100 * otherwise kernel code will have no chance to set this bit.
102 setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
105 #ifdef CONFIG_ARMV8_PSCI
106 #define PTE_MAP_NS PTE_BLOCK_NS
111 static struct mm_region imx8m_mem_map[] = {
117 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
118 PTE_BLOCK_OUTER_SHARE
124 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
125 PTE_BLOCK_NON_SHARE |
126 PTE_BLOCK_PXN | PTE_BLOCK_UXN
132 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
133 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
139 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140 PTE_BLOCK_NON_SHARE |
141 PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
147 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
148 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
153 .size = 0x3f500000UL,
154 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
155 PTE_BLOCK_NON_SHARE |
156 PTE_BLOCK_PXN | PTE_BLOCK_UXN
159 .virt = 0x40000000UL,
160 .phys = 0x40000000UL,
161 .size = PHYS_SDRAM_SIZE,
162 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
163 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
164 #ifdef PHYS_SDRAM_2_SIZE
167 .virt = 0x100000000UL,
168 .phys = 0x100000000UL,
169 .size = PHYS_SDRAM_2_SIZE,
170 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
171 PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
174 /* empty entrie to split table entry 5 if needed when TEEs are used */
177 /* List terminator */
182 struct mm_region *mem_map = imx8m_mem_map;
184 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
188 for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
189 if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
192 hang(); /* Entry not found, this must never happen. */
195 void enable_caches(void)
197 /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
198 * If OPTEE does not run, still update the MMU table according to dram banks structure
199 * to set correct dram size from board_phys_sdram_size
203 * please make sure that entry initial value matches
204 * imx8m_mem_map for DRAM1
206 int entry = imx8m_find_dram_entry_in_mem_map();
207 u64 attrs = imx8m_mem_map[entry].attrs;
209 while (i < CONFIG_NR_DRAM_BANKS &&
210 entry < ARRAY_SIZE(imx8m_mem_map)) {
211 if (gd->bd->bi_dram[i].start == 0)
213 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
214 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
215 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
216 imx8m_mem_map[entry].attrs = attrs;
217 debug("Added memory mapping (%d): %llx %llx\n", entry,
218 imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
226 __weak int board_phys_sdram_size(phys_size_t *size)
231 *size = PHYS_SDRAM_SIZE;
233 #ifdef PHYS_SDRAM_2_SIZE
234 *size += PHYS_SDRAM_2_SIZE;
241 phys_size_t sdram_size;
244 ret = board_phys_sdram_size(&sdram_size);
248 /* rom_pointer[1] contains the size of TEE occupies */
249 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
250 gd->ram_size = sdram_size - rom_pointer[1];
252 gd->ram_size = sdram_size;
257 int dram_init_banksize(void)
261 phys_size_t sdram_size;
262 phys_size_t sdram_b1_size, sdram_b2_size;
264 ret = board_phys_sdram_size(&sdram_size);
268 /* Bank 1 can't cross over 4GB space */
269 if (sdram_size > 0xc0000000) {
270 sdram_b1_size = 0xc0000000;
271 sdram_b2_size = sdram_size - 0xc0000000;
273 sdram_b1_size = sdram_size;
277 gd->bd->bi_dram[bank].start = PHYS_SDRAM;
278 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
279 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
280 phys_size_t optee_size = (size_t)rom_pointer[1];
282 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
283 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
284 if (++bank >= CONFIG_NR_DRAM_BANKS) {
285 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
289 gd->bd->bi_dram[bank].start = optee_start + optee_size;
290 gd->bd->bi_dram[bank].size = PHYS_SDRAM +
291 sdram_b1_size - gd->bd->bi_dram[bank].start;
294 gd->bd->bi_dram[bank].size = sdram_b1_size;
298 if (++bank >= CONFIG_NR_DRAM_BANKS) {
299 puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
302 gd->bd->bi_dram[bank].start = 0x100000000UL;
303 gd->bd->bi_dram[bank].size = sdram_b2_size;
309 phys_size_t get_effective_memsize(void)
312 phys_size_t sdram_size;
313 phys_size_t sdram_b1_size;
314 ret = board_phys_sdram_size(&sdram_size);
316 /* Bank 1 can't cross over 4GB space */
317 if (sdram_size > 0xc0000000) {
318 sdram_b1_size = 0xc0000000;
320 sdram_b1_size = sdram_size;
323 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
325 /* We will relocate u-boot to Top of dram1. Tee position has two cases:
326 * 1. At the top of dram1, Then return the size removed optee size.
327 * 2. In the middle of dram1, return the size of dram1.
329 if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
330 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
333 return sdram_b1_size;
335 return PHYS_SDRAM_SIZE;
339 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
344 * Some IPs have their accessible address space restricted by
345 * the interconnect. Let's make sure U-Boot only ever uses the
346 * space below the 4G address boundary (which is 3GiB big),
347 * even when the effective available memory is bigger.
349 top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
352 * rom_pointer[0] stores the TEE memory start address.
353 * rom_pointer[1] stores the size TEE uses.
354 * We need to reserve the memory region for TEE.
356 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
357 rom_pointer[1] && top_addr > rom_pointer[0])
358 top_addr = rom_pointer[0];
363 static u32 get_cpu_variant_type(u32 type)
365 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
366 struct fuse_bank *bank = &ocotp->bank[1];
367 struct fuse_bank1_regs *fuse =
368 (struct fuse_bank1_regs *)bank->fuse_regs;
370 u32 value = readl(&fuse->tester4);
372 if (type == MXC_CPU_IMX8MQ) {
373 if ((value & 0x3) == 0x2)
374 return MXC_CPU_IMX8MD;
375 else if (value & 0x200000)
376 return MXC_CPU_IMX8MQL;
378 } else if (type == MXC_CPU_IMX8MM) {
379 switch (value & 0x3) {
381 if (value & 0x1c0000)
382 return MXC_CPU_IMX8MMDL;
384 return MXC_CPU_IMX8MMD;
386 if (value & 0x1c0000)
387 return MXC_CPU_IMX8MMSL;
389 return MXC_CPU_IMX8MMS;
391 if (value & 0x1c0000)
392 return MXC_CPU_IMX8MML;
395 } else if (type == MXC_CPU_IMX8MN) {
396 switch (value & 0x3) {
398 if (value & 0x1000000) {
399 if (value & 0x10000000) /* MIPI DSI */
400 return MXC_CPU_IMX8MNUD;
402 return MXC_CPU_IMX8MNDL;
404 return MXC_CPU_IMX8MND;
407 if (value & 0x1000000) {
408 if (value & 0x10000000) /* MIPI DSI */
409 return MXC_CPU_IMX8MNUS;
411 return MXC_CPU_IMX8MNSL;
413 return MXC_CPU_IMX8MNS;
416 if (value & 0x1000000) {
417 if (value & 0x10000000) /* MIPI DSI */
418 return MXC_CPU_IMX8MNUQ;
420 return MXC_CPU_IMX8MNL;
424 } else if (type == MXC_CPU_IMX8MP) {
425 u32 value0 = readl(&fuse->tester3);
428 if ((value0 & 0xc0000) == 0x80000)
429 return MXC_CPU_IMX8MPD;
432 if ((value0 & 0x43000000) == 0x43000000)
436 if ((value & 0x8) == 0x8)
440 if ((value & 0x3) == 0x3)
444 if ((value & 0xc0) == 0xc0)
448 if ((value & 0x180000) == 0x180000)
451 /* mipi dsi disabled */
452 if ((value & 0x60000) == 0x60000)
457 return MXC_CPU_IMX8MPUL;
459 return MXC_CPU_IMX8MPL;
461 return MXC_CPU_IMX8MP6;
471 u32 get_cpu_rev(void)
473 struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
474 u32 reg = readl(&ana_pll->digprog);
475 u32 type = (reg >> 16) & 0xff;
476 u32 major_low = (reg >> 8) & 0xff;
482 if (major_low == 0x43) {
483 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
484 } else if (major_low == 0x42) {
486 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
487 } else if (major_low == 0x41) {
488 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
490 if (reg == CHIP_REV_1_0) {
492 * For B0 chip, the DIGPROG is not updated,
493 * it is still TO1.0. we have to check ROM
494 * version or OCOTP_READ_FUSE_DATA.
495 * 0xff0055aa is magic number for B1.
497 if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
499 * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
500 * so have to check ROM to distinguish them
502 rom_version = readl((void __iomem *)ROM_VERSION_B0);
504 if (rom_version == CHIP_REV_2_2)
510 readl((void __iomem *)ROM_VERSION_A0);
511 if (rom_version != CHIP_REV_1_0) {
512 rom_version = readl((void __iomem *)ROM_VERSION_B0);
514 if (rom_version == CHIP_REV_2_0)
520 type = get_cpu_variant_type(type);
523 return (type << 12) | reg;
526 static void imx_set_wdog_powerdown(bool enable)
528 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
529 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
530 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
532 /* Write to the PDE (Power Down Enable) bit */
533 writew(enable, &wdog1->wmcr);
534 writew(enable, &wdog2->wmcr);
535 writew(enable, &wdog3->wmcr);
538 static int imx8m_check_clock(void)
543 if (CONFIG_IS_ENABLED(CLK)) {
544 ret = uclass_get_device_by_name(UCLASS_CLK,
545 "clock-controller@30380000",
548 printf("Failed to find clock node. Check device tree\n");
555 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8m_check_clock);
557 static void imx8m_setup_snvs(void)
559 /* Enable SNVS clock */
560 clock_enable(CCGR_SNVS, 1);
561 /* Initialize glitch detect */
562 writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
563 /* Clear interrupt status */
564 writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
567 static void imx8m_setup_csu_tzasc(void)
569 const uintptr_t tzasc_base[4] = {
570 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
574 if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
578 for (i = 0; i < 64; i++)
579 writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
582 for (j = 0; j < 4; j++) {
583 writel(0x77777777, (void *)(tzasc_base[j]));
584 writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
585 for (i = 0; i <= 0x10; i += 4)
586 writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
590 int arch_cpu_init(void)
592 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
594 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
599 * ROM might disable clock for SCTR,
600 * enable the clock before timer_init.
602 if (IS_ENABLED(CONFIG_SPL_BUILD))
603 clock_enable(CCGR_SCTR, 1);
605 * Init timer at very early state, because sscg pll setting
610 if (IS_ENABLED(CONFIG_SPL_BUILD)) {
612 imx_set_wdog_powerdown(false);
614 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
615 is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
616 is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
617 /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
618 struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
619 struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
620 struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
621 struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
623 writel(0x1, &pgc_core2->pgcr);
624 writel(0x1, &pgc_core3->pgcr);
625 if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
626 writel(0x1, &pgc_core1->pgcr);
627 writel(0xE, &gpc->cpu_pgc_dn_trg);
629 writel(0xC, &gpc->cpu_pgc_dn_trg);
635 clock_enable(CCGR_OCOTP, 1);
636 if (readl(&ocotp->ctrl) & 0x200)
637 writel(0x200, &ocotp->ctrl_clr);
642 imx8m_setup_csu_tzasc();
647 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
648 struct rom_api *g_rom_api = (struct rom_api *)0x980;
651 #if defined(CONFIG_IMX8M)
653 int imx8m_detect_secondary_image_boot(void)
655 u32 *rom_log_addr = (u32 *)0x9e0;
658 int i, boot_secondary = 0;
660 /* If the ROM event log pointer is not valid. */
661 if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
665 /* Parse the ROM event ID version 2 log */
666 rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
667 for (i = 0; i < 128; i++) {
668 event_id = rom_log[i] >> 24;
670 case 0x00: /* End of list */
671 return boot_secondary;
672 /* Log entries with 1 parameter, skip 1 */
673 case 0x80: /* Start to perform the device initialization */
674 case 0x81: /* The boot device initialization completes */
675 case 0x82: /* Starts to execute boot device driver pre-config */
676 case 0x8f: /* The boot device initialization fails */
677 case 0x90: /* Start to read data from boot device */
678 case 0x91: /* Reading data from boot device completes */
679 case 0x9f: /* Reading data from boot device fails */
682 /* Log entries with 2 parameters, skip 2 */
683 case 0xa0: /* Image authentication result */
684 case 0xc0: /* Jump to the boot image soon */
687 /* Boot from the secondary boot image */
696 return boot_secondary;
699 int spl_mmc_emmc_boot_partition(struct mmc *mmc)
703 part = default_spl_mmc_emmc_boot_partition(mmc);
707 ret = imx8m_detect_secondary_image_boot();
709 printf("Could not get boot partition! Using %d\n", part);
715 * Swap the eMMC boot partitions in case there was a
716 * fallback event (i.e. primary image was corrupted
717 * and that corruption was recognized by the BootROM),
718 * so the SPL loads the rest of the U-Boot from the
719 * correct eMMC boot partition, since the BootROM
720 * leaves the boot partition set to the corrupted one.
731 int boot_mode_getprisec(void)
733 return !!imx8m_detect_secondary_image_boot();
737 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
738 #ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
739 #define IMG_CNTN_SET1_OFFSET GENMASK(22, 19)
740 unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
741 unsigned long raw_sect)
745 if (fuse_read(2, 1, &val)) {
746 debug("Error reading fuse!\n");
750 val = FIELD_GET(IMG_CNTN_SET1_OFFSET, val);
752 debug("Secondary image boot disabled!\n");
762 else /* flash.bin offset = 1 MiB * 2^n */
763 offset = SZ_1M << val;
766 offset -= CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET;
768 if (imx8m_detect_secondary_image_boot())
773 #endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */
776 bool is_usb_boot(void)
778 return get_boot_device() == USB_BOOT;
781 #ifdef CONFIG_OF_SYSTEM_SETUP
782 bool check_fdt_new_path(void *blob)
784 const char *soc_path = "/soc@0";
787 nodeoff = fdt_path_offset(blob, soc_path);
794 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
799 const char *status = "disabled";
801 for (i = 0; i < size_array; i++) {
802 nodeoff = fdt_path_offset(blob, nodes_path[i]);
804 continue; /* Not found, skip it */
806 debug("Found %s node\n", nodes_path[i]);
809 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
811 if (rc == -FDT_ERR_NOSPACE) {
812 rc = fdt_increase_size(blob, 512);
816 printf("Unable to update property %s:%s, err=%s\n",
817 nodes_path[i], "status", fdt_strerror(rc));
819 printf("Modify %s:%s disabled\n",
820 nodes_path[i], "status");
828 bool check_dcss_fused(void)
830 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
831 struct fuse_bank *bank = &ocotp->bank[1];
832 struct fuse_bank1_regs *fuse =
833 (struct fuse_bank1_regs *)bank->fuse_regs;
834 u32 value = readl(&fuse->tester4);
836 if (value & 0x4000000)
842 static int disable_mipi_dsi_nodes(void *blob)
844 static const char * const nodes_path[] = {
845 "/mipi_dsi@30A00000",
846 "/mipi_dsi_bridge@30A00000",
848 "/soc@0/bus@30800000/mipi_dsi@30a00000",
849 "/soc@0/bus@30800000/dphy@30a00300",
850 "/soc@0/bus@30800000/mipi-dsi@30a00000",
853 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
856 static int disable_dcss_nodes(void *blob)
858 static const char * const nodes_path[] = {
862 "/hdmi_cec@32c33800",
863 "/hdmi_drm@32c00000",
864 "/display-subsystem",
867 "/soc@0/bus@32c00000/display-controller@32e00000",
868 "/soc@0/bus@32c00000/hdmi@32c00000",
871 return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
874 static int check_mipi_dsi_nodes(void *blob)
876 static const char * const lcdif_path[] = {
878 "/soc@0/bus@30000000/lcdif@30320000",
879 "/soc@0/bus@30000000/lcd-controller@30320000"
881 static const char * const mipi_dsi_path[] = {
882 "/mipi_dsi@30A00000",
883 "/soc@0/bus@30800000/mipi_dsi@30a00000"
885 static const char * const lcdif_ep_path[] = {
886 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
887 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
888 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
890 static const char * const mipi_dsi_ep_path[] = {
891 "/mipi_dsi@30A00000/port@1/endpoint",
892 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
893 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
898 bool new_path = check_fdt_new_path(blob);
899 int i = new_path ? 1 : 0;
901 nodeoff = fdt_path_offset(blob, lcdif_path[i]);
902 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
904 * If can't find lcdif node or lcdif node is disabled,
905 * then disable all mipi dsi, since they only can input
908 return disable_mipi_dsi_nodes(blob);
911 nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
912 if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
915 nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
918 * If can't find lcdif endpoint, then disable all mipi dsi,
919 * since they only can input from DCSS
921 return disable_mipi_dsi_nodes(blob);
924 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
925 nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
927 if (nodeoff > 0 && nodeoff == lookup_node)
930 return disable_mipi_dsi_nodes(blob);
934 int disable_vpu_nodes(void *blob)
936 static const char * const nodes_path_8mq[] = {
938 "/soc@0/vpu@38300000",
939 "/soc@0/video-codec@38300000",
940 "/soc@0/video-codec@38310000",
941 "/soc@0/blk-ctrl@38320000",
944 static const char * const nodes_path_8mm[] = {
948 "/soc@0/video-codec@38300000",
949 "/soc@0/video-codec@38310000",
950 "/soc@0/blk-ctrl@38330000",
953 static const char * const nodes_path_8mp[] = {
956 "/vpu_vc8000e@38320000",
957 "/soc@0/video-codec@38300000",
958 "/soc@0/video-codec@38310000",
959 "/soc@0/blk-ctrl@38330000",
963 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
964 else if (is_imx8mm())
965 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
966 else if (is_imx8mp())
967 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
972 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
973 static int low_drive_gpu_freq(void *blob)
975 static const char *nodes_path_8mn[] = {
977 "/soc@0/gpu@38000000"
983 nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
987 cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
992 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
996 assignedclks[cnt - 1] = 200000000;
997 assignedclks[cnt - 2] = 200000000;
999 for (i = 0; i < cnt; i++) {
1000 debug("<%u>, ", assignedclks[i]);
1001 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
1005 return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
1009 static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
1014 nodeoff = fdt_path_offset(blob, ep1);
1016 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
1017 nodeoff = fdt_path_offset(blob, ep2);
1019 if (nodeoff > 0 && nodeoff == lookup_node)
1026 int disable_dsi_lcdif_nodes(void *blob)
1030 static const char * const dsi_path_8mp[] = {
1031 "/soc@0/bus@32c00000/mipi_dsi@32e60000"
1034 static const char * const lcdif_path_8mp[] = {
1035 "/soc@0/bus@32c00000/lcd-controller@32e80000"
1038 static const char * const lcdif_ep_path_8mp[] = {
1039 "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
1041 static const char * const dsi_ep_path_8mp[] = {
1042 "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
1045 ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
1049 if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
1050 /* Disable lcdif node */
1051 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1057 int disable_lvds_lcdif_nodes(void *blob)
1061 static const char * const ldb_path_8mp[] = {
1062 "/soc@0/bus@32c00000/ldb@32ec005c",
1063 "/soc@0/bus@32c00000/phy@32ec0128"
1066 static const char * const lcdif_path_8mp[] = {
1067 "/soc@0/bus@32c00000/lcd-controller@32e90000"
1070 static const char * const lcdif_ep_path_8mp[] = {
1071 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
1072 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
1074 static const char * const ldb_ep_path_8mp[] = {
1075 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
1076 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
1079 ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
1083 for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
1084 if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
1085 /* Disable lcdif node */
1086 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1093 int disable_gpu_nodes(void *blob)
1095 static const char * const nodes_path_8mn[] = {
1097 "/soc@/gpu@38000000"
1100 static const char * const nodes_path_8mp[] = {
1106 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1108 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
1111 int disable_npu_nodes(void *blob)
1113 static const char * const nodes_path_8mp[] = {
1115 "/soc@0/npu@38500000",
1118 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1121 int disable_isp_nodes(void *blob)
1123 static const char * const nodes_path_8mp[] = {
1124 "/soc@0/bus@32c00000/camera/isp@32e10000",
1125 "/soc@0/bus@32c00000/camera/isp@32e20000"
1128 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1131 int disable_dsp_nodes(void *blob)
1133 static const char * const nodes_path_8mp[] = {
1137 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1140 static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
1142 static const char * const thermal_path[] = {
1143 "/thermal-zones/cpu-thermal/cooling-maps/map0"
1146 int nodeoff, cnt, i, ret, j;
1147 u32 cooling_dev[12];
1149 for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
1150 nodeoff = fdt_path_offset(blob, thermal_path[i]);
1152 continue; /* Not found, skip it */
1154 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
1159 printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
1161 for (j = 0; j < cnt; j++)
1162 cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
1164 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
1165 sizeof(u32) * (12 - disabled_cores * 3));
1167 printf("Warning: %s, cooling-device setprop failed %d\n",
1168 thermal_path[i], ret);
1172 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
1176 static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
1178 static const char * const pmu_path[] = {
1182 int nodeoff, cnt, i, ret, j;
1183 u32 irq_affinity[4];
1185 for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
1186 nodeoff = fdt_path_offset(blob, pmu_path[i]);
1188 continue; /* Not found, skip it */
1190 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
1196 printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
1198 for (j = 0; j < cnt; j++)
1199 irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
1201 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
1202 sizeof(u32) * (4 - disabled_cores));
1204 printf("Warning: %s, interrupt-affinity setprop failed %d\n",
1209 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
1213 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
1215 static const char * const nodes_path[] = {
1224 if (disabled_cores > 3)
1227 i = 3 - disabled_cores;
1229 for (; i < 3; i++) {
1230 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1232 continue; /* Not found, skip it */
1234 debug("Found %s node\n", nodes_path[i]);
1236 rc = fdt_del_node(blob, nodeoff);
1238 printf("Unable to delete node %s, err=%s\n",
1239 nodes_path[i], fdt_strerror(rc));
1241 printf("Delete node %s\n", nodes_path[i]);
1245 disable_thermal_cpu_nodes(blob, disabled_cores);
1246 disable_pmu_cpu_nodes(blob, disabled_cores);
1251 static int cleanup_nodes_for_efi(void *blob)
1253 static const char * const path[][2] = {
1254 { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
1255 { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
1256 { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
1257 { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
1261 for (i = 0; i < ARRAY_SIZE(path); i++) {
1262 nodeoff = fdt_path_offset(blob, path[i][0]);
1264 continue; /* Not found, skip it */
1265 debug("Found %s node\n", path[i][0]);
1267 rc = fdt_delprop(blob, nodeoff, path[i][1]);
1268 if (rc == -FDT_ERR_NOTFOUND)
1271 printf("Unable to update property %s:%s, err=%s\n",
1272 path[i][0], path[i][1], fdt_strerror(rc));
1276 printf("Remove %s:%s\n", path[i][0], path[i][1]);
1282 static int fixup_thermal_trips(void *blob, const char *name)
1287 node = fdt_path_offset(blob, "/thermal-zones");
1291 node = fdt_subnode_offset(blob, node, name);
1295 node = fdt_subnode_offset(blob, node, "trips");
1299 get_cpu_temp_grade(&minc, &maxc);
1301 fdt_for_each_subnode(trip, blob, node) {
1305 type = fdt_getprop(blob, trip, "type", NULL);
1310 if (!strcmp(type, "critical"))
1312 else if (!strcmp(type, "passive"))
1313 temp = 1000 * (maxc - 10);
1315 ret = fdt_setprop_u32(blob, trip, "temperature", temp);
1324 #define OPTEE_SHM_SIZE 0x00400000
1325 static int ft_add_optee_node(void *fdt, struct bd_info *bd)
1327 struct fdt_memory carveout;
1328 const char *path, *subpath;
1329 phys_addr_t optee_start;
1335 * No TEE space allocated indicating no TEE running, so no
1336 * need to add optee node in dts
1338 if (!rom_pointer[1])
1341 optee_start = (phys_addr_t)rom_pointer[0];
1342 optee_size = rom_pointer[1] - OPTEE_SHM_SIZE;
1344 offs = fdt_increase_size(fdt, 512);
1346 printf("No Space for dtb\n");
1351 offs = fdt_path_offset(fdt, path);
1354 offs = fdt_path_offset(fdt, path);
1357 printf("Could not find root node.\n");
1361 subpath = "firmware";
1362 offs = fdt_add_subnode(fdt, offs, subpath);
1364 printf("Could not create %s node.\n", subpath);
1370 offs = fdt_add_subnode(fdt, offs, subpath);
1372 printf("Could not create %s node.\n", subpath);
1376 fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
1377 fdt_setprop_string(fdt, offs, "method", "smc");
1379 carveout.start = optee_start,
1380 carveout.end = optee_start + optee_size - 1,
1381 ret = fdtdec_add_reserved_memory(fdt, "optee_core", &carveout, NULL, 0,
1382 NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
1384 printf("Could not create optee_core node.\n");
1388 carveout.start = optee_start + optee_size;
1389 carveout.end = optee_start + optee_size + OPTEE_SHM_SIZE - 1;
1390 ret = fdtdec_add_reserved_memory(fdt, "optee_shm", &carveout, NULL, 0,
1391 NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
1393 printf("Could not create optee_shm node.\n");
1400 int ft_system_setup(void *blob, struct bd_info *bd)
1402 #ifdef CONFIG_IMX8MQ
1407 if (get_boot_device() == USB_BOOT) {
1408 disable_dcss_nodes(blob);
1410 bool new_path = check_fdt_new_path(blob);
1411 int v = new_path ? 1 : 0;
1412 static const char * const usb_dwc3_path[] = {
1413 "/usb@38100000/dwc3",
1414 "/soc@0/usb@38100000"
1417 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1419 const char *speed = "high-speed";
1421 debug("Found %s node\n", usb_dwc3_path[v]);
1425 rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1427 if (rc == -FDT_ERR_NOSPACE) {
1428 rc = fdt_increase_size(blob, 512);
1430 goto usb_modify_speed;
1432 printf("Unable to set property %s:%s, err=%s\n",
1433 usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1435 printf("Modify %s:%s = %s\n",
1436 usb_dwc3_path[v], "maximum-speed", speed);
1439 printf("Can't found %s node\n", usb_dwc3_path[v]);
1443 /* Disable the CPU idle for A0 chip since the HW does not support it */
1444 if (is_soc_rev(CHIP_REV_1_0)) {
1445 static const char * const nodes_path[] = {
1452 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1453 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1455 continue; /* Not found, skip it */
1457 debug("Found %s node\n", nodes_path[i]);
1459 rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
1460 if (rc == -FDT_ERR_NOTFOUND)
1463 printf("Unable to update property %s:%s, err=%s\n",
1464 nodes_path[i], "status", fdt_strerror(rc));
1468 debug("Remove %s:%s\n", nodes_path[i],
1474 disable_vpu_nodes(blob);
1475 if (check_dcss_fused()) {
1476 printf("DCSS is fused\n");
1477 disable_dcss_nodes(blob);
1478 check_mipi_dsi_nodes(blob);
1483 disable_cpu_nodes(blob, 2);
1485 #elif defined(CONFIG_IMX8MM)
1486 if (is_imx8mml() || is_imx8mmdl() || is_imx8mmsl())
1487 disable_vpu_nodes(blob);
1489 if (is_imx8mmd() || is_imx8mmdl())
1490 disable_cpu_nodes(blob, 2);
1491 else if (is_imx8mms() || is_imx8mmsl())
1492 disable_cpu_nodes(blob, 3);
1494 #elif defined(CONFIG_IMX8MN)
1495 if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl())
1496 disable_gpu_nodes(blob);
1497 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1499 int ldm_gpu = low_drive_gpu_freq(blob);
1502 printf("Update GPU node assigned-clock-rates failed\n");
1504 printf("Update GPU node assigned-clock-rates ok\n");
1508 if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1509 disable_cpu_nodes(blob, 2);
1510 else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1511 disable_cpu_nodes(blob, 3);
1513 #elif defined(CONFIG_IMX8MP)
1514 if (is_imx8mpul()) {
1516 disable_gpu_nodes(blob);
1519 disable_dsi_lcdif_nodes(blob);
1522 disable_lvds_lcdif_nodes(blob);
1525 if (is_imx8mpul() || is_imx8mpl())
1526 disable_vpu_nodes(blob);
1528 if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1529 disable_npu_nodes(blob);
1531 if (is_imx8mpul() || is_imx8mpl())
1532 disable_isp_nodes(blob);
1534 if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1535 disable_dsp_nodes(blob);
1538 disable_cpu_nodes(blob, 2);
1541 cleanup_nodes_for_efi(blob);
1543 if (fixup_thermal_trips(blob, "cpu-thermal"))
1544 printf("Failed to update cpu-thermal trip(s)");
1545 if (IS_ENABLED(CONFIG_IMX8MP) &&
1546 fixup_thermal_trips(blob, "soc-thermal"))
1547 printf("Failed to update soc-thermal trip(s)");
1549 return ft_add_optee_node(blob, bd);
1553 #if !CONFIG_IS_ENABLED(SYSRESET)
1554 void reset_cpu(void)
1556 struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1558 /* Clear WDA to trigger WDOG_B immediately */
1559 writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1563 * spin for .5 seconds before reset
1569 #if defined(CONFIG_ARCH_MISC_INIT)
1570 int arch_misc_init(void)
1572 if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1573 struct udevice *dev;
1576 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1578 printf("Failed to initialize caam_jr: %d\n", ret);
1585 #if defined(CONFIG_SPL_BUILD)
1586 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1587 bool serror_need_skip = true;
1589 void do_error(struct pt_regs *pt_regs)
1592 * If stack is still in ROM reserved OCRAM not switch to SPL,
1593 * it is the ROM SError
1597 asm volatile("mov %0, sp" : "=r"(sp) : );
1599 if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1600 /* Check for ERR050342, imx8mq HDCP enabled parts */
1601 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1602 serror_need_skip = false;
1603 return; /* Do nothing skip the SError in ROM */
1606 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1607 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1608 serror_need_skip = false;
1609 return; /* Do nothing skip the SError in ROM */
1614 printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr);
1616 panic("Resetting CPU ...\n");
1621 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
1622 enum env_location arch_env_get_location(enum env_operation op, int prio)
1624 enum boot_device dev = get_boot_device();
1627 return ENVL_UNKNOWN;
1631 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1632 return ENVL_SPI_FLASH;
1633 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1635 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1637 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
1638 return ENVL_NOWHERE;
1639 return ENVL_UNKNOWN;
1642 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1643 return ENVL_SPI_FLASH;
1644 return ENVL_NOWHERE;
1646 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1648 return ENVL_NOWHERE;
1655 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1657 else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
1659 else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
1661 return ENVL_NOWHERE;
1663 return ENVL_NOWHERE;
1669 #ifdef CONFIG_IMX_BOOTAUX
1670 const struct rproc_att hostmap[] = {
1671 /* aux core , host core, size */
1672 { 0x00000000, 0x007e0000, 0x00020000 },
1674 { 0x00180000, 0x00180000, 0x00008000 },
1676 { 0x00900000, 0x00900000, 0x00020000 },
1678 { 0x00920000, 0x00920000, 0x00020000 },
1679 /* QSPI Code - alias */
1680 { 0x08000000, 0x08000000, 0x08000000 },
1681 /* DDR (Code) - alias */
1682 { 0x10000000, 0x80000000, 0x0FFE0000 },
1684 { 0x1FFE0000, 0x007E0000, 0x00040000 },
1686 { 0x20180000, 0x00180000, 0x00008000 },
1688 { 0x20200000, 0x00900000, 0x00040000 },
1690 { 0x40000000, 0x40000000, 0x80000000 },
1694 const struct rproc_att *imx_bootaux_get_hostmap(void)