spl: mmc: Try to clean up raw-mode options
[J-u-boot.git] / arch / arm / mach-imx / imx8m / soc.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2017-2019, 2021 NXP
4  *
5  * Peng Fan <peng.fan@nxp.com>
6  */
7
8 #include <config.h>
9 #include <cpu_func.h>
10 #include <event.h>
11 #include <init.h>
12 #include <log.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/global_data.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/mach-imx/hab.h>
19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/syscounter.h>
21 #include <asm/ptrace.h>
22 #include <asm/armv8/mmu.h>
23 #include <dm/uclass.h>
24 #include <dm/device.h>
25 #include <efi_loader.h>
26 #include <env.h>
27 #include <env_internal.h>
28 #include <errno.h>
29 #include <fdt_support.h>
30 #include <fsl_wdog.h>
31 #include <fuse.h>
32 #include <imx_sip.h>
33 #include <linux/bitops.h>
34 #include <linux/bitfield.h>
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #if defined(CONFIG_IMX_HAB)
39 struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
40         .bank = 1,
41         .word = 3,
42 };
43 #endif
44
45 int timer_init(void)
46 {
47 #ifdef CONFIG_SPL_BUILD
48         struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
49         unsigned long freq = readl(&sctr->cntfid0);
50
51         /* Update with accurate clock frequency */
52         asm volatile("msr cntfrq_el0, %0" : : "r" (freq) : "memory");
53
54         clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
55                         SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
56 #endif
57
58         gd->arch.tbl = 0;
59         gd->arch.tbu = 0;
60
61         return 0;
62 }
63
64 void enable_tzc380(void)
65 {
66         struct iomuxc_gpr_base_regs *gpr =
67                 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
68
69         /* Enable TZASC and lock setting */
70         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
71         setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
72
73         /*
74          * According to TRM, TZASC_ID_SWAP_BYPASS should be set in
75          * order to avoid AXI Bus errors when GPU is in use
76          */
77         setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
78
79         /*
80          * imx8mn and imx8mp implements the lock bit for
81          * TZASC_ID_SWAP_BYPASS, enable it to lock settings
82          */
83         setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK);
84
85         /*
86          * set Region 0 attribute to allow secure and non-secure
87          * read/write permission. Found some masters like usb dwc3
88          * controllers can't work with secure memory.
89          */
90         writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
91 }
92
93 void set_wdog_reset(struct wdog_regs *wdog)
94 {
95         /*
96          * Output WDOG_B signal to reset external pmic or POR_B decided by
97          * the board design. Without external reset, the peripherals/DDR/
98          * PMIC are not reset, that may cause system working abnormal.
99          * WDZST bit is write-once only bit. Align this bit in kernel,
100          * otherwise kernel code will have no chance to set this bit.
101          */
102         setbits_le16(&wdog->wcr, WDOG_WDT_MASK | WDOG_WDZST_MASK);
103 }
104
105 #ifdef CONFIG_ARMV8_PSCI
106 #define PTE_MAP_NS      PTE_BLOCK_NS
107 #else
108 #define PTE_MAP_NS      0
109 #endif
110
111 static struct mm_region imx8m_mem_map[] = {
112         {
113                 /* ROM */
114                 .virt = 0x0UL,
115                 .phys = 0x0UL,
116                 .size = 0x100000UL,
117                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
118                          PTE_BLOCK_OUTER_SHARE
119         }, {
120                 /* CAAM */
121                 .virt = 0x100000UL,
122                 .phys = 0x100000UL,
123                 .size = 0x8000UL,
124                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
125                          PTE_BLOCK_NON_SHARE |
126                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
127         }, {
128                 /* OCRAM_S */
129                 .virt = 0x180000UL,
130                 .phys = 0x180000UL,
131                 .size = 0x8000UL,
132                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
133                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
134         }, {
135                 /* TCM */
136                 .virt = 0x7C0000UL,
137                 .phys = 0x7C0000UL,
138                 .size = 0x80000UL,
139                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
140                          PTE_BLOCK_NON_SHARE |
141                          PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_MAP_NS
142         }, {
143                 /* OCRAM */
144                 .virt = 0x900000UL,
145                 .phys = 0x900000UL,
146                 .size = 0x200000UL,
147                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
148                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
149         }, {
150                 /* AIPS */
151                 .virt = 0xB00000UL,
152                 .phys = 0xB00000UL,
153                 .size = 0x3f500000UL,
154                 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
155                          PTE_BLOCK_NON_SHARE |
156                          PTE_BLOCK_PXN | PTE_BLOCK_UXN
157         }, {
158                 /* DRAM1 */
159                 .virt = 0x40000000UL,
160                 .phys = 0x40000000UL,
161                 .size = PHYS_SDRAM_SIZE,
162                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
163                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
164 #ifdef PHYS_SDRAM_2_SIZE
165         }, {
166                 /* DRAM2 */
167                 .virt = 0x100000000UL,
168                 .phys = 0x100000000UL,
169                 .size = PHYS_SDRAM_2_SIZE,
170                 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
171                          PTE_BLOCK_OUTER_SHARE | PTE_MAP_NS
172 #endif
173         }, {
174                 /* empty entrie to split table entry 5 if needed when TEEs are used */
175                 0,
176         }, {
177                 /* List terminator */
178                 0,
179         }
180 };
181
182 struct mm_region *mem_map = imx8m_mem_map;
183
184 static unsigned int imx8m_find_dram_entry_in_mem_map(void)
185 {
186         int i;
187
188         for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++)
189                 if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE)
190                         return i;
191
192         hang(); /* Entry not found, this must never happen. */
193 }
194
195 void enable_caches(void)
196 {
197         /* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
198          * If OPTEE does not run, still update the MMU table according to dram banks structure
199          * to set correct dram size from board_phys_sdram_size
200          */
201         int i = 0;
202         /*
203          * please make sure that entry initial value matches
204          * imx8m_mem_map for DRAM1
205          */
206         int entry = imx8m_find_dram_entry_in_mem_map();
207         u64 attrs = imx8m_mem_map[entry].attrs;
208
209         while (i < CONFIG_NR_DRAM_BANKS &&
210                entry < ARRAY_SIZE(imx8m_mem_map)) {
211                 if (gd->bd->bi_dram[i].start == 0)
212                         break;
213                 imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
214                 imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
215                 imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
216                 imx8m_mem_map[entry].attrs = attrs;
217                 debug("Added memory mapping (%d): %llx %llx\n", entry,
218                       imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
219                 i++; entry++;
220         }
221
222         icache_enable();
223         dcache_enable();
224 }
225
226 __weak int board_phys_sdram_size(phys_size_t *size)
227 {
228         if (!size)
229                 return -EINVAL;
230
231         *size = PHYS_SDRAM_SIZE;
232
233 #ifdef PHYS_SDRAM_2_SIZE
234         *size += PHYS_SDRAM_2_SIZE;
235 #endif
236         return 0;
237 }
238
239 int dram_init(void)
240 {
241         phys_size_t sdram_size;
242         int ret;
243
244         ret = board_phys_sdram_size(&sdram_size);
245         if (ret)
246                 return ret;
247
248         /* rom_pointer[1] contains the size of TEE occupies */
249         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1])
250                 gd->ram_size = sdram_size - rom_pointer[1];
251         else
252                 gd->ram_size = sdram_size;
253
254         return 0;
255 }
256
257 int dram_init_banksize(void)
258 {
259         int bank = 0;
260         int ret;
261         phys_size_t sdram_size;
262         phys_size_t sdram_b1_size, sdram_b2_size;
263
264         ret = board_phys_sdram_size(&sdram_size);
265         if (ret)
266                 return ret;
267
268         /* Bank 1 can't cross over 4GB space */
269         if (sdram_size > 0xc0000000) {
270                 sdram_b1_size = 0xc0000000;
271                 sdram_b2_size = sdram_size - 0xc0000000;
272         } else {
273                 sdram_b1_size = sdram_size;
274                 sdram_b2_size = 0;
275         }
276
277         gd->bd->bi_dram[bank].start = PHYS_SDRAM;
278         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) && rom_pointer[1]) {
279                 phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
280                 phys_size_t optee_size = (size_t)rom_pointer[1];
281
282                 gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
283                 if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
284                         if (++bank >= CONFIG_NR_DRAM_BANKS) {
285                                 puts("CONFIG_NR_DRAM_BANKS is not enough\n");
286                                 return -1;
287                         }
288
289                         gd->bd->bi_dram[bank].start = optee_start + optee_size;
290                         gd->bd->bi_dram[bank].size = PHYS_SDRAM +
291                                 sdram_b1_size - gd->bd->bi_dram[bank].start;
292                 }
293         } else {
294                 gd->bd->bi_dram[bank].size = sdram_b1_size;
295         }
296
297         if (sdram_b2_size) {
298                 if (++bank >= CONFIG_NR_DRAM_BANKS) {
299                         puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
300                         return -1;
301                 }
302                 gd->bd->bi_dram[bank].start = 0x100000000UL;
303                 gd->bd->bi_dram[bank].size = sdram_b2_size;
304         }
305
306         return 0;
307 }
308
309 phys_size_t get_effective_memsize(void)
310 {
311         int ret;
312         phys_size_t sdram_size;
313         phys_size_t sdram_b1_size;
314         ret = board_phys_sdram_size(&sdram_size);
315         if (!ret) {
316                 /* Bank 1 can't cross over 4GB space */
317                 if (sdram_size > 0xc0000000) {
318                         sdram_b1_size = 0xc0000000;
319                 } else {
320                         sdram_b1_size = sdram_size;
321                 }
322
323                 if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && !IS_ENABLED(CONFIG_SPL_BUILD) &&
324                     rom_pointer[1]) {
325                         /* We will relocate u-boot to Top of dram1. Tee position has two cases:
326                          * 1. At the top of dram1,  Then return the size removed optee size.
327                          * 2. In the middle of dram1, return the size of dram1.
328                          */
329                         if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
330                                 return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
331                 }
332
333                 return sdram_b1_size;
334         } else {
335                 return PHYS_SDRAM_SIZE;
336         }
337 }
338
339 phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
340 {
341         ulong top_addr;
342
343         /*
344          * Some IPs have their accessible address space restricted by
345          * the interconnect. Let's make sure U-Boot only ever uses the
346          * space below the 4G address boundary (which is 3GiB big),
347          * even when the effective available memory is bigger.
348          */
349         top_addr = clamp_val((u64)PHYS_SDRAM + gd->ram_size, 0, 0xffffffff);
350
351         /*
352          * rom_pointer[0] stores the TEE memory start address.
353          * rom_pointer[1] stores the size TEE uses.
354          * We need to reserve the memory region for TEE.
355          */
356         if (!IS_ENABLED(CONFIG_ARMV8_PSCI) && rom_pointer[0] &&
357             rom_pointer[1] && top_addr > rom_pointer[0])
358                 top_addr = rom_pointer[0];
359
360         return top_addr;
361 }
362
363 static u32 get_cpu_variant_type(u32 type)
364 {
365         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
366         struct fuse_bank *bank = &ocotp->bank[1];
367         struct fuse_bank1_regs *fuse =
368                 (struct fuse_bank1_regs *)bank->fuse_regs;
369
370         u32 value = readl(&fuse->tester4);
371
372         if (type == MXC_CPU_IMX8MQ) {
373                 if ((value & 0x3) == 0x2)
374                         return MXC_CPU_IMX8MD;
375                 else if (value & 0x200000)
376                         return MXC_CPU_IMX8MQL;
377
378         } else if (type == MXC_CPU_IMX8MM) {
379                 switch (value & 0x3) {
380                 case 2:
381                         if (value & 0x1c0000)
382                                 return MXC_CPU_IMX8MMDL;
383                         else
384                                 return MXC_CPU_IMX8MMD;
385                 case 3:
386                         if (value & 0x1c0000)
387                                 return MXC_CPU_IMX8MMSL;
388                         else
389                                 return MXC_CPU_IMX8MMS;
390                 default:
391                         if (value & 0x1c0000)
392                                 return MXC_CPU_IMX8MML;
393                         break;
394                 }
395         } else if (type == MXC_CPU_IMX8MN) {
396                 switch (value & 0x3) {
397                 case 2:
398                         if (value & 0x1000000) {
399                                 if (value & 0x10000000)  /* MIPI DSI */
400                                         return MXC_CPU_IMX8MNUD;
401                                 else
402                                         return MXC_CPU_IMX8MNDL;
403                         } else {
404                                 return MXC_CPU_IMX8MND;
405                         }
406                 case 3:
407                         if (value & 0x1000000) {
408                                 if (value & 0x10000000)  /* MIPI DSI */
409                                         return MXC_CPU_IMX8MNUS;
410                                 else
411                                         return MXC_CPU_IMX8MNSL;
412                         } else {
413                                 return MXC_CPU_IMX8MNS;
414                         }
415                 default:
416                         if (value & 0x1000000) {
417                                 if (value & 0x10000000)  /* MIPI DSI */
418                                         return MXC_CPU_IMX8MNUQ;
419                                 else
420                                         return MXC_CPU_IMX8MNL;
421                         }
422                         break;
423                 }
424         } else if (type == MXC_CPU_IMX8MP) {
425                 u32 value0 = readl(&fuse->tester3);
426                 u32 flag = 0;
427
428                 if ((value0 & 0xc0000) == 0x80000)
429                         return MXC_CPU_IMX8MPD;
430
431                         /* vpu disabled */
432                 if ((value0 & 0x43000000) == 0x43000000)
433                         flag = 1;
434
435                 /* npu disabled*/
436                 if ((value & 0x8) == 0x8)
437                         flag |= BIT(1);
438
439                 /* isp disabled */
440                 if ((value & 0x3) == 0x3)
441                         flag |= BIT(2);
442
443                 /* gpu disabled */
444                 if ((value & 0xc0) == 0xc0)
445                         flag |= BIT(3);
446
447                 /* lvds disabled */
448                 if ((value & 0x180000) == 0x180000)
449                         flag |= BIT(4);
450
451                 /* mipi dsi disabled */
452                 if ((value & 0x60000) == 0x60000)
453                         flag |= BIT(5);
454
455                 switch (flag) {
456                 case 0x3f:
457                         return MXC_CPU_IMX8MPUL;
458                 case 7:
459                         return MXC_CPU_IMX8MPL;
460                 case 2:
461                         return MXC_CPU_IMX8MP6;
462                 default:
463                         break;
464                 }
465
466         }
467
468         return type;
469 }
470
471 u32 get_cpu_rev(void)
472 {
473         struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
474         u32 reg = readl(&ana_pll->digprog);
475         u32 type = (reg >> 16) & 0xff;
476         u32 major_low = (reg >> 8) & 0xff;
477         u32 rom_version;
478
479         reg &= 0xff;
480
481         /* iMX8MP */
482         if (major_low == 0x43) {
483                 type = get_cpu_variant_type(MXC_CPU_IMX8MP);
484         } else if (major_low == 0x42) {
485                 /* iMX8MN */
486                 type = get_cpu_variant_type(MXC_CPU_IMX8MN);
487         } else if (major_low == 0x41) {
488                 type = get_cpu_variant_type(MXC_CPU_IMX8MM);
489         } else {
490                 if (reg == CHIP_REV_1_0) {
491                         /*
492                          * For B0 chip, the DIGPROG is not updated,
493                          * it is still TO1.0. we have to check ROM
494                          * version or OCOTP_READ_FUSE_DATA.
495                          * 0xff0055aa is magic number for B1.
496                          */
497                         if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) {
498                                 /*
499                                  * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1,
500                                  * so have to check ROM to distinguish them
501                                  */
502                                 rom_version = readl((void __iomem *)ROM_VERSION_B0);
503                                 rom_version &= 0xff;
504                                 if (rom_version == CHIP_REV_2_2)
505                                         reg = CHIP_REV_2_2;
506                                 else
507                                         reg = CHIP_REV_2_1;
508                         } else {
509                                 rom_version =
510                                         readl((void __iomem *)ROM_VERSION_A0);
511                                 if (rom_version != CHIP_REV_1_0) {
512                                         rom_version = readl((void __iomem *)ROM_VERSION_B0);
513                                         rom_version &= 0xff;
514                                         if (rom_version == CHIP_REV_2_0)
515                                                 reg = CHIP_REV_2_0;
516                                 }
517                         }
518                 }
519
520                 type = get_cpu_variant_type(type);
521         }
522
523         return (type << 12) | reg;
524 }
525
526 static void imx_set_wdog_powerdown(bool enable)
527 {
528         struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
529         struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
530         struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
531
532         /* Write to the PDE (Power Down Enable) bit */
533         writew(enable, &wdog1->wmcr);
534         writew(enable, &wdog2->wmcr);
535         writew(enable, &wdog3->wmcr);
536 }
537
538 static int imx8m_check_clock(void)
539 {
540         struct udevice *dev;
541         int ret;
542
543         if (CONFIG_IS_ENABLED(CLK)) {
544                 ret = uclass_get_device_by_name(UCLASS_CLK,
545                                                 "clock-controller@30380000",
546                                                 &dev);
547                 if (ret < 0) {
548                         printf("Failed to find clock node. Check device tree\n");
549                         return ret;
550                 }
551         }
552
553         return 0;
554 }
555 EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8m_check_clock);
556
557 static void imx8m_setup_snvs(void)
558 {
559         /* Enable SNVS clock */
560         clock_enable(CCGR_SNVS, 1);
561         /* Initialize glitch detect */
562         writel(SNVS_LPPGDR_INIT, SNVS_BASE_ADDR + SNVS_LPLVDR);
563         /* Clear interrupt status */
564         writel(0xffffffff, SNVS_BASE_ADDR + SNVS_LPSR);
565 }
566
567 static void imx8m_setup_csu_tzasc(void)
568 {
569         const uintptr_t tzasc_base[4] = {
570                 0x301f0000, 0x301f0000, 0x301f0000, 0x301f0000
571         };
572         int i, j;
573
574         if (!IS_ENABLED(CONFIG_ARMV8_PSCI))
575                 return;
576
577         /* CSU */
578         for (i = 0; i < 64; i++)
579                 writel(0x00ff00ff, (void *)CSU_BASE_ADDR + (4 * i));
580
581         /* TZASC */
582         for (j = 0; j < 4; j++) {
583                 writel(0x77777777, (void *)(tzasc_base[j]));
584                 writel(0x77777777, (void *)(tzasc_base[j]) + 0x4);
585                 for (i = 0; i <= 0x10; i += 4)
586                         writel(0, (void *)(tzasc_base[j]) + 0x40 + i);
587         }
588 }
589
590 int arch_cpu_init(void)
591 {
592         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
593
594 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
595         icache_enable();
596 #endif
597
598         /*
599          * ROM might disable clock for SCTR,
600          * enable the clock before timer_init.
601          */
602         if (IS_ENABLED(CONFIG_SPL_BUILD))
603                 clock_enable(CCGR_SCTR, 1);
604         /*
605          * Init timer at very early state, because sscg pll setting
606          * will use it
607          */
608         timer_init();
609
610         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
611                 clock_init();
612                 imx_set_wdog_powerdown(false);
613
614                 if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() ||
615                     is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() ||
616                     is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) {
617                         /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */
618                         struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840);
619                         struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880);
620                         struct pgc_reg *pgc_core3 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x8C0);
621                         struct gpc_reg *gpc = (struct gpc_reg *)GPC_BASE_ADDR;
622
623                         writel(0x1, &pgc_core2->pgcr);
624                         writel(0x1, &pgc_core3->pgcr);
625                         if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) {
626                                 writel(0x1, &pgc_core1->pgcr);
627                                 writel(0xE, &gpc->cpu_pgc_dn_trg);
628                         } else {
629                                 writel(0xC, &gpc->cpu_pgc_dn_trg);
630                         }
631                 }
632         }
633
634         if (is_imx8mq()) {
635                 clock_enable(CCGR_OCOTP, 1);
636                 if (readl(&ocotp->ctrl) & 0x200)
637                         writel(0x200, &ocotp->ctrl_clr);
638         }
639
640         imx8m_setup_snvs();
641
642         imx8m_setup_csu_tzasc();
643
644         return 0;
645 }
646
647 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
648 struct rom_api *g_rom_api = (struct rom_api *)0x980;
649 #endif
650
651 #if defined(CONFIG_IMX8M)
652 #include <spl.h>
653 int imx8m_detect_secondary_image_boot(void)
654 {
655         u32 *rom_log_addr = (u32 *)0x9e0;
656         u32 *rom_log;
657         u8 event_id;
658         int i, boot_secondary = 0;
659
660         /* If the ROM event log pointer is not valid. */
661         if (*rom_log_addr < 0x900000 || *rom_log_addr >= 0xb00000 ||
662             *rom_log_addr & 0x3)
663                 return -EINVAL;
664
665         /* Parse the ROM event ID version 2 log */
666         rom_log = (u32 *)(uintptr_t)(*rom_log_addr);
667         for (i = 0; i < 128; i++) {
668                 event_id = rom_log[i] >> 24;
669                 switch (event_id) {
670                 case 0x00: /* End of list */
671                         return boot_secondary;
672                 /* Log entries with 1 parameter, skip 1 */
673                 case 0x80: /* Start to perform the device initialization */
674                 case 0x81: /* The boot device initialization completes */
675                 case 0x82: /* Starts to execute boot device driver pre-config */
676                 case 0x8f: /* The boot device initialization fails */
677                 case 0x90: /* Start to read data from boot device */
678                 case 0x91: /* Reading data from boot device completes */
679                 case 0x9f: /* Reading data from boot device fails */
680                         i += 1;
681                         continue;
682                 /* Log entries with 2 parameters, skip 2 */
683                 case 0xa0: /* Image authentication result */
684                 case 0xc0: /* Jump to the boot image soon */
685                         i += 2;
686                         continue;
687                 /* Boot from the secondary boot image */
688                 case 0x51:
689                         boot_secondary = 1;
690                         continue;
691                 default:
692                         continue;
693                 }
694         }
695
696         return boot_secondary;
697 }
698
699 int spl_mmc_emmc_boot_partition(struct mmc *mmc)
700 {
701         int part, ret;
702
703         part = default_spl_mmc_emmc_boot_partition(mmc);
704         if (part == 0)
705                 return part;
706
707         ret = imx8m_detect_secondary_image_boot();
708         if (ret < 0) {
709                 printf("Could not get boot partition! Using %d\n", part);
710                 return part;
711         }
712
713         if (ret == 1) {
714                 /*
715                  * Swap the eMMC boot partitions in case there was a
716                  * fallback event (i.e. primary image was corrupted
717                  * and that corruption was recognized by the BootROM),
718                  * so the SPL loads the rest of the U-Boot from the
719                  * correct eMMC boot partition, since the BootROM
720                  * leaves the boot partition set to the corrupted one.
721                  */
722                 if (part == 1)
723                         part = 2;
724                 else if (part == 2)
725                         part = 1;
726         }
727
728         return part;
729 }
730
731 int boot_mode_getprisec(void)
732 {
733         return !!imx8m_detect_secondary_image_boot();
734 }
735 #endif
736
737 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
738 #ifdef SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
739 #define IMG_CNTN_SET1_OFFSET    GENMASK(22, 19)
740 unsigned long arch_spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
741                                                 unsigned long raw_sect)
742 {
743         u32 val, offset;
744
745         if (fuse_read(2, 1, &val)) {
746                 debug("Error reading fuse!\n");
747                 return raw_sect;
748         }
749
750         val = FIELD_GET(IMG_CNTN_SET1_OFFSET, val);
751         if (val > 10) {
752                 debug("Secondary image boot disabled!\n");
753                 return raw_sect;
754         }
755
756         if (val == 0)
757                 offset = SZ_4M;
758         else if (val == 1)
759                 offset = SZ_2M;
760         else if (val == 2)
761                 offset = SZ_1M;
762         else    /* flash.bin offset = 1 MiB * 2^n */
763                 offset = SZ_1M << val;
764
765         offset /= 512;
766         offset -= CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET;
767
768         if (imx8m_detect_secondary_image_boot())
769                 raw_sect += offset;
770
771         return raw_sect;
772 }
773 #endif /* SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION */
774 #endif
775
776 bool is_usb_boot(void)
777 {
778         return get_boot_device() == USB_BOOT;
779 }
780
781 #ifdef CONFIG_OF_SYSTEM_SETUP
782 bool check_fdt_new_path(void *blob)
783 {
784         const char *soc_path = "/soc@0";
785         int nodeoff;
786
787         nodeoff = fdt_path_offset(blob, soc_path);
788         if (nodeoff < 0)
789                 return false;
790
791         return true;
792 }
793
794 static int disable_fdt_nodes(void *blob, const char *const nodes_path[], int size_array)
795 {
796         int i = 0;
797         int rc;
798         int nodeoff;
799         const char *status = "disabled";
800
801         for (i = 0; i < size_array; i++) {
802                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
803                 if (nodeoff < 0)
804                         continue; /* Not found, skip it */
805
806                 debug("Found %s node\n", nodes_path[i]);
807
808 add_status:
809                 rc = fdt_setprop(blob, nodeoff, "status", status, strlen(status) + 1);
810                 if (rc) {
811                         if (rc == -FDT_ERR_NOSPACE) {
812                                 rc = fdt_increase_size(blob, 512);
813                                 if (!rc)
814                                         goto add_status;
815                         }
816                         printf("Unable to update property %s:%s, err=%s\n",
817                                nodes_path[i], "status", fdt_strerror(rc));
818                 } else {
819                         printf("Modify %s:%s disabled\n",
820                                nodes_path[i], "status");
821                 }
822         }
823
824         return 0;
825 }
826
827 #ifdef CONFIG_IMX8MQ
828 bool check_dcss_fused(void)
829 {
830         struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
831         struct fuse_bank *bank = &ocotp->bank[1];
832         struct fuse_bank1_regs *fuse =
833                 (struct fuse_bank1_regs *)bank->fuse_regs;
834         u32 value = readl(&fuse->tester4);
835
836         if (value & 0x4000000)
837                 return true;
838
839         return false;
840 }
841
842 static int disable_mipi_dsi_nodes(void *blob)
843 {
844         static const char * const nodes_path[] = {
845                 "/mipi_dsi@30A00000",
846                 "/mipi_dsi_bridge@30A00000",
847                 "/dsi_phy@30A00300",
848                 "/soc@0/bus@30800000/mipi_dsi@30a00000",
849                 "/soc@0/bus@30800000/dphy@30a00300",
850                 "/soc@0/bus@30800000/mipi-dsi@30a00000",
851         };
852
853         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
854 }
855
856 static int disable_dcss_nodes(void *blob)
857 {
858         static const char * const nodes_path[] = {
859                 "/dcss@0x32e00000",
860                 "/dcss@32e00000",
861                 "/hdmi@32c00000",
862                 "/hdmi_cec@32c33800",
863                 "/hdmi_drm@32c00000",
864                 "/display-subsystem",
865                 "/sound-hdmi",
866                 "/sound-hdmi-arc",
867                 "/soc@0/bus@32c00000/display-controller@32e00000",
868                 "/soc@0/bus@32c00000/hdmi@32c00000",
869         };
870
871         return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path));
872 }
873
874 static int check_mipi_dsi_nodes(void *blob)
875 {
876         static const char * const lcdif_path[] = {
877                 "/lcdif@30320000",
878                 "/soc@0/bus@30000000/lcdif@30320000",
879                 "/soc@0/bus@30000000/lcd-controller@30320000"
880         };
881         static const char * const mipi_dsi_path[] = {
882                 "/mipi_dsi@30A00000",
883                 "/soc@0/bus@30800000/mipi_dsi@30a00000"
884         };
885         static const char * const lcdif_ep_path[] = {
886                 "/lcdif@30320000/port@0/mipi-dsi-endpoint",
887                 "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint",
888                 "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint"
889         };
890         static const char * const mipi_dsi_ep_path[] = {
891                 "/mipi_dsi@30A00000/port@1/endpoint",
892                 "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint",
893                 "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0"
894         };
895
896         int lookup_node;
897         int nodeoff;
898         bool new_path = check_fdt_new_path(blob);
899         int i = new_path ? 1 : 0;
900
901         nodeoff = fdt_path_offset(blob, lcdif_path[i]);
902         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff)) {
903                 /*
904                  * If can't find lcdif node or lcdif node is disabled,
905                  * then disable all mipi dsi, since they only can input
906                  * from DCSS
907                  */
908                 return disable_mipi_dsi_nodes(blob);
909         }
910
911         nodeoff = fdt_path_offset(blob, mipi_dsi_path[i]);
912         if (nodeoff < 0 || !fdtdec_get_is_enabled(blob, nodeoff))
913                 return 0;
914
915         nodeoff = fdt_path_offset(blob, lcdif_ep_path[i]);
916         if (nodeoff < 0) {
917                 /*
918                  * If can't find lcdif endpoint, then disable all mipi dsi,
919                  * since they only can input from DCSS
920                  */
921                 return disable_mipi_dsi_nodes(blob);
922         }
923
924         lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
925         nodeoff = fdt_path_offset(blob, mipi_dsi_ep_path[i]);
926
927         if (nodeoff > 0 && nodeoff == lookup_node)
928                 return 0;
929
930         return disable_mipi_dsi_nodes(blob);
931 }
932 #endif
933
934 int disable_vpu_nodes(void *blob)
935 {
936         static const char * const nodes_path_8mq[] = {
937                 "/vpu@38300000",
938                 "/soc@0/vpu@38300000",
939                 "/soc@0/video-codec@38300000",
940                 "/soc@0/video-codec@38310000",
941                 "/soc@0/blk-ctrl@38320000",
942         };
943
944         static const char * const nodes_path_8mm[] = {
945                 "/vpu_g1@38300000",
946                 "/vpu_g2@38310000",
947                 "/vpu_h1@38320000",
948                 "/soc@0/video-codec@38300000",
949                 "/soc@0/video-codec@38310000",
950                 "/soc@0/blk-ctrl@38330000",
951         };
952
953         static const char * const nodes_path_8mp[] = {
954                 "/vpu_g1@38300000",
955                 "/vpu_g2@38310000",
956                 "/vpu_vc8000e@38320000",
957                 "/soc@0/video-codec@38300000",
958                 "/soc@0/video-codec@38310000",
959                 "/soc@0/blk-ctrl@38330000",
960         };
961
962         if (is_imx8mq())
963                 return disable_fdt_nodes(blob, nodes_path_8mq, ARRAY_SIZE(nodes_path_8mq));
964         else if (is_imx8mm())
965                 return disable_fdt_nodes(blob, nodes_path_8mm, ARRAY_SIZE(nodes_path_8mm));
966         else if (is_imx8mp())
967                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
968         else
969                 return -EPERM;
970 }
971
972 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
973 static int low_drive_gpu_freq(void *blob)
974 {
975         static const char *nodes_path_8mn[] = {
976                 "/gpu@38000000",
977                 "/soc@0/gpu@38000000"
978         };
979
980         int nodeoff, cnt, i;
981         u32 assignedclks[7];
982
983         nodeoff = fdt_path_offset(blob, nodes_path_8mn[0]);
984         if (nodeoff < 0)
985                 return nodeoff;
986
987         cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7);
988         if (cnt < 0)
989                 return cnt;
990
991         if (cnt != 7)
992                 printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
993         if (cnt < 2)
994                 return -1;
995
996         assignedclks[cnt - 1] = 200000000;
997         assignedclks[cnt - 2] = 200000000;
998
999         for (i = 0; i < cnt; i++) {
1000                 debug("<%u>, ", assignedclks[i]);
1001                 assignedclks[i] = cpu_to_fdt32(assignedclks[i]);
1002         }
1003         debug("\n");
1004
1005         return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks));
1006 }
1007 #endif
1008
1009 static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
1010 {
1011         int lookup_node;
1012         int nodeoff;
1013
1014         nodeoff = fdt_path_offset(blob, ep1);
1015         if (nodeoff) {
1016                 lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
1017                 nodeoff = fdt_path_offset(blob, ep2);
1018
1019                 if (nodeoff > 0 && nodeoff == lookup_node)
1020                         return true;
1021         }
1022
1023         return false;
1024 }
1025
1026 int disable_dsi_lcdif_nodes(void *blob)
1027 {
1028         int ret;
1029
1030         static const char * const dsi_path_8mp[] = {
1031                 "/soc@0/bus@32c00000/mipi_dsi@32e60000"
1032         };
1033
1034         static const char * const lcdif_path_8mp[] = {
1035                 "/soc@0/bus@32c00000/lcd-controller@32e80000"
1036         };
1037
1038         static const char * const lcdif_ep_path_8mp[] = {
1039                 "/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
1040         };
1041         static const char * const dsi_ep_path_8mp[] = {
1042                 "/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
1043         };
1044
1045         ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
1046         if (ret)
1047                 return ret;
1048
1049         if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
1050                 /* Disable lcdif node */
1051                 return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1052         }
1053
1054         return 0;
1055 }
1056
1057 int disable_lvds_lcdif_nodes(void *blob)
1058 {
1059         int ret, i;
1060
1061         static const char * const ldb_path_8mp[] = {
1062                 "/soc@0/bus@32c00000/ldb@32ec005c",
1063                 "/soc@0/bus@32c00000/phy@32ec0128"
1064         };
1065
1066         static const char * const lcdif_path_8mp[] = {
1067                 "/soc@0/bus@32c00000/lcd-controller@32e90000"
1068         };
1069
1070         static const char * const lcdif_ep_path_8mp[] = {
1071                 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
1072                 "/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
1073         };
1074         static const char * const ldb_ep_path_8mp[] = {
1075                 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
1076                 "/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
1077         };
1078
1079         ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
1080         if (ret)
1081                 return ret;
1082
1083         for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
1084                 if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
1085                         /* Disable lcdif node */
1086                         return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
1087                 }
1088         }
1089
1090         return 0;
1091 }
1092
1093 int disable_gpu_nodes(void *blob)
1094 {
1095         static const char * const nodes_path_8mn[] = {
1096                 "/gpu@38000000",
1097                 "/soc@/gpu@38000000"
1098         };
1099
1100         static const char * const nodes_path_8mp[] = {
1101                 "/gpu3d@38000000",
1102                 "/gpu2d@38008000"
1103         };
1104
1105         if (is_imx8mp())
1106                 return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1107         else
1108                 return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
1109 }
1110
1111 int disable_npu_nodes(void *blob)
1112 {
1113         static const char * const nodes_path_8mp[] = {
1114                 "/vipsi@38500000",
1115                 "/soc@0/npu@38500000",
1116         };
1117
1118         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1119 }
1120
1121 int disable_isp_nodes(void *blob)
1122 {
1123         static const char * const nodes_path_8mp[] = {
1124                 "/soc@0/bus@32c00000/camera/isp@32e10000",
1125                 "/soc@0/bus@32c00000/camera/isp@32e20000"
1126         };
1127
1128         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1129 }
1130
1131 int disable_dsp_nodes(void *blob)
1132 {
1133         static const char * const nodes_path_8mp[] = {
1134                 "/dsp@3b6e8000"
1135         };
1136
1137         return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
1138 }
1139
1140 static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
1141 {
1142         static const char * const thermal_path[] = {
1143                 "/thermal-zones/cpu-thermal/cooling-maps/map0"
1144         };
1145
1146         int nodeoff, cnt, i, ret, j;
1147         u32 cooling_dev[12];
1148
1149         for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
1150                 nodeoff = fdt_path_offset(blob, thermal_path[i]);
1151                 if (nodeoff < 0)
1152                         continue; /* Not found, skip it */
1153
1154                 cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12);
1155                 if (cnt < 0)
1156                         continue;
1157
1158                 if (cnt != 12)
1159                         printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt);
1160
1161                 for (j = 0; j < cnt; j++)
1162                         cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
1163
1164                 ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
1165                                   sizeof(u32) * (12 - disabled_cores * 3));
1166                 if (ret < 0) {
1167                         printf("Warning: %s, cooling-device setprop failed %d\n",
1168                                thermal_path[i], ret);
1169                         continue;
1170                 }
1171
1172                 printf("Update node %s, cooling-device prop\n", thermal_path[i]);
1173         }
1174 }
1175
1176 static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
1177 {
1178         static const char * const pmu_path[] = {
1179                 "/pmu"
1180         };
1181
1182         int nodeoff, cnt, i, ret, j;
1183         u32 irq_affinity[4];
1184
1185         for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
1186                 nodeoff = fdt_path_offset(blob, pmu_path[i]);
1187                 if (nodeoff < 0)
1188                         continue; /* Not found, skip it */
1189
1190                 cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity",
1191                                                  irq_affinity, 4);
1192                 if (cnt < 0)
1193                         continue;
1194
1195                 if (cnt != 4)
1196                         printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt);
1197
1198                 for (j = 0; j < cnt; j++)
1199                         irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
1200
1201                 ret = fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity,
1202                                  sizeof(u32) * (4 - disabled_cores));
1203                 if (ret < 0) {
1204                         printf("Warning: %s, interrupt-affinity setprop failed %d\n",
1205                                pmu_path[i], ret);
1206                         continue;
1207                 }
1208
1209                 printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]);
1210         }
1211 }
1212
1213 static int disable_cpu_nodes(void *blob, u32 disabled_cores)
1214 {
1215         static const char * const nodes_path[] = {
1216                 "/cpus/cpu@1",
1217                 "/cpus/cpu@2",
1218                 "/cpus/cpu@3",
1219         };
1220         u32 i = 0;
1221         int rc;
1222         int nodeoff;
1223
1224         if (disabled_cores > 3)
1225                 return -EINVAL;
1226
1227         i = 3 - disabled_cores;
1228
1229         for (; i < 3; i++) {
1230                 nodeoff = fdt_path_offset(blob, nodes_path[i]);
1231                 if (nodeoff < 0)
1232                         continue; /* Not found, skip it */
1233
1234                 debug("Found %s node\n", nodes_path[i]);
1235
1236                 rc = fdt_del_node(blob, nodeoff);
1237                 if (rc < 0) {
1238                         printf("Unable to delete node %s, err=%s\n",
1239                                nodes_path[i], fdt_strerror(rc));
1240                 } else {
1241                         printf("Delete node %s\n", nodes_path[i]);
1242                 }
1243         }
1244
1245         disable_thermal_cpu_nodes(blob, disabled_cores);
1246         disable_pmu_cpu_nodes(blob, disabled_cores);
1247
1248         return 0;
1249 }
1250
1251 static int cleanup_nodes_for_efi(void *blob)
1252 {
1253         static const char * const path[][2] = {
1254                 { "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
1255                 { "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
1256                 { "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
1257                 { "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
1258         };
1259         int nodeoff, i, rc;
1260
1261         for (i = 0; i < ARRAY_SIZE(path); i++) {
1262                 nodeoff = fdt_path_offset(blob, path[i][0]);
1263                 if (nodeoff < 0)
1264                         continue; /* Not found, skip it */
1265                 debug("Found %s node\n", path[i][0]);
1266
1267                 rc = fdt_delprop(blob, nodeoff, path[i][1]);
1268                 if (rc == -FDT_ERR_NOTFOUND)
1269                         continue;
1270                 if (rc) {
1271                         printf("Unable to update property %s:%s, err=%s\n",
1272                                path[i][0], path[i][1], fdt_strerror(rc));
1273                         return rc;
1274                 }
1275
1276                 printf("Remove %s:%s\n", path[i][0], path[i][1]);
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int fixup_thermal_trips(void *blob, const char *name)
1283 {
1284         int minc, maxc;
1285         int node, trip;
1286
1287         node = fdt_path_offset(blob, "/thermal-zones");
1288         if (node < 0)
1289                 return node;
1290
1291         node = fdt_subnode_offset(blob, node, name);
1292         if (node < 0)
1293                 return node;
1294
1295         node = fdt_subnode_offset(blob, node, "trips");
1296         if (node < 0)
1297                 return node;
1298
1299         get_cpu_temp_grade(&minc, &maxc);
1300
1301         fdt_for_each_subnode(trip, blob, node) {
1302                 const char *type;
1303                 int temp, ret;
1304
1305                 type = fdt_getprop(blob, trip, "type", NULL);
1306                 if (!type)
1307                         continue;
1308
1309                 temp = 0;
1310                 if (!strcmp(type, "critical"))
1311                         temp = 1000 * maxc;
1312                 else if (!strcmp(type, "passive"))
1313                         temp = 1000 * (maxc - 10);
1314                 if (temp) {
1315                         ret = fdt_setprop_u32(blob, trip, "temperature", temp);
1316                         if (ret)
1317                                 return ret;
1318                 }
1319         }
1320
1321         return 0;
1322 }
1323
1324 #define OPTEE_SHM_SIZE 0x00400000
1325 static int ft_add_optee_node(void *fdt, struct bd_info *bd)
1326 {
1327         struct fdt_memory carveout;
1328         const char *path, *subpath;
1329         phys_addr_t optee_start;
1330         size_t optee_size;
1331         int offs;
1332         int ret;
1333
1334         /*
1335          * No TEE space allocated indicating no TEE running, so no
1336          * need to add optee node in dts
1337          */
1338         if (!rom_pointer[1])
1339                 return 0;
1340
1341         optee_start = (phys_addr_t)rom_pointer[0];
1342         optee_size = rom_pointer[1] - OPTEE_SHM_SIZE;
1343
1344         offs = fdt_increase_size(fdt, 512);
1345         if (offs) {
1346                 printf("No Space for dtb\n");
1347                 return 1;
1348         }
1349
1350         path = "/firmware";
1351         offs = fdt_path_offset(fdt, path);
1352         if (offs < 0) {
1353                 path = "/";
1354                 offs = fdt_path_offset(fdt, path);
1355
1356                 if (offs < 0) {
1357                         printf("Could not find root node.\n");
1358                         return offs;
1359                 }
1360
1361                 subpath = "firmware";
1362                 offs = fdt_add_subnode(fdt, offs, subpath);
1363                 if (offs < 0) {
1364                         printf("Could not create %s node.\n", subpath);
1365                         return offs;
1366                 }
1367         }
1368
1369         subpath = "optee";
1370         offs = fdt_add_subnode(fdt, offs, subpath);
1371         if (offs < 0) {
1372                 printf("Could not create %s node.\n", subpath);
1373                 return offs;
1374         }
1375
1376         fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz");
1377         fdt_setprop_string(fdt, offs, "method", "smc");
1378
1379         carveout.start = optee_start,
1380         carveout.end = optee_start + optee_size - 1,
1381         ret = fdtdec_add_reserved_memory(fdt, "optee_core", &carveout, NULL, 0,
1382                                          NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
1383         if (ret < 0) {
1384                 printf("Could not create optee_core node.\n");
1385                 return ret;
1386         }
1387
1388         carveout.start = optee_start + optee_size;
1389         carveout.end = optee_start + optee_size + OPTEE_SHM_SIZE - 1;
1390         ret = fdtdec_add_reserved_memory(fdt, "optee_shm", &carveout, NULL, 0,
1391                                          NULL, FDTDEC_RESERVED_MEMORY_NO_MAP);
1392         if (ret < 0) {
1393                 printf("Could not create optee_shm node.\n");
1394                 return ret;
1395         }
1396
1397         return 0;
1398 }
1399
1400 int ft_system_setup(void *blob, struct bd_info *bd)
1401 {
1402 #ifdef CONFIG_IMX8MQ
1403         int i = 0;
1404         int rc;
1405         int nodeoff;
1406
1407         if (get_boot_device() == USB_BOOT) {
1408                 disable_dcss_nodes(blob);
1409
1410                 bool new_path = check_fdt_new_path(blob);
1411                 int v = new_path ? 1 : 0;
1412                 static const char * const usb_dwc3_path[] = {
1413                         "/usb@38100000/dwc3",
1414                         "/soc@0/usb@38100000"
1415                 };
1416
1417                 nodeoff = fdt_path_offset(blob, usb_dwc3_path[v]);
1418                 if (nodeoff >= 0) {
1419                         const char *speed = "high-speed";
1420
1421                         debug("Found %s node\n", usb_dwc3_path[v]);
1422
1423 usb_modify_speed:
1424
1425                         rc = fdt_setprop(blob, nodeoff, "maximum-speed", speed, strlen(speed) + 1);
1426                         if (rc) {
1427                                 if (rc == -FDT_ERR_NOSPACE) {
1428                                         rc = fdt_increase_size(blob, 512);
1429                                         if (!rc)
1430                                                 goto usb_modify_speed;
1431                                 }
1432                                 printf("Unable to set property %s:%s, err=%s\n",
1433                                        usb_dwc3_path[v], "maximum-speed", fdt_strerror(rc));
1434                         } else {
1435                                 printf("Modify %s:%s = %s\n",
1436                                        usb_dwc3_path[v], "maximum-speed", speed);
1437                         }
1438                 } else {
1439                         printf("Can't found %s node\n", usb_dwc3_path[v]);
1440                 }
1441         }
1442
1443         /* Disable the CPU idle for A0 chip since the HW does not support it */
1444         if (is_soc_rev(CHIP_REV_1_0)) {
1445                 static const char * const nodes_path[] = {
1446                         "/cpus/cpu@0",
1447                         "/cpus/cpu@1",
1448                         "/cpus/cpu@2",
1449                         "/cpus/cpu@3",
1450                 };
1451
1452                 for (i = 0; i < ARRAY_SIZE(nodes_path); i++) {
1453                         nodeoff = fdt_path_offset(blob, nodes_path[i]);
1454                         if (nodeoff < 0)
1455                                 continue; /* Not found, skip it */
1456
1457                         debug("Found %s node\n", nodes_path[i]);
1458
1459                         rc = fdt_delprop(blob, nodeoff, "cpu-idle-states");
1460                         if (rc == -FDT_ERR_NOTFOUND)
1461                                 continue;
1462                         if (rc) {
1463                                 printf("Unable to update property %s:%s, err=%s\n",
1464                                        nodes_path[i], "status", fdt_strerror(rc));
1465                                 return rc;
1466                         }
1467
1468                         debug("Remove %s:%s\n", nodes_path[i],
1469                                "cpu-idle-states");
1470                 }
1471         }
1472
1473         if (is_imx8mql()) {
1474                 disable_vpu_nodes(blob);
1475                 if (check_dcss_fused()) {
1476                         printf("DCSS is fused\n");
1477                         disable_dcss_nodes(blob);
1478                         check_mipi_dsi_nodes(blob);
1479                 }
1480         }
1481
1482         if (is_imx8md())
1483                 disable_cpu_nodes(blob, 2);
1484
1485 #elif defined(CONFIG_IMX8MM)
1486         if (is_imx8mml() || is_imx8mmdl() ||  is_imx8mmsl())
1487                 disable_vpu_nodes(blob);
1488
1489         if (is_imx8mmd() || is_imx8mmdl())
1490                 disable_cpu_nodes(blob, 2);
1491         else if (is_imx8mms() || is_imx8mmsl())
1492                 disable_cpu_nodes(blob, 3);
1493
1494 #elif defined(CONFIG_IMX8MN)
1495         if (is_imx8mnl() || is_imx8mndl() ||  is_imx8mnsl())
1496                 disable_gpu_nodes(blob);
1497 #ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
1498         else {
1499                 int ldm_gpu = low_drive_gpu_freq(blob);
1500
1501                 if (ldm_gpu < 0)
1502                         printf("Update GPU node assigned-clock-rates failed\n");
1503                 else
1504                         printf("Update GPU node assigned-clock-rates ok\n");
1505         }
1506 #endif
1507
1508         if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud())
1509                 disable_cpu_nodes(blob, 2);
1510         else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus())
1511                 disable_cpu_nodes(blob, 3);
1512
1513 #elif defined(CONFIG_IMX8MP)
1514         if (is_imx8mpul()) {
1515                 /* Disable GPU */
1516                 disable_gpu_nodes(blob);
1517
1518                 /* Disable DSI */
1519                 disable_dsi_lcdif_nodes(blob);
1520
1521                 /* Disable LVDS */
1522                 disable_lvds_lcdif_nodes(blob);
1523         }
1524
1525         if (is_imx8mpul() || is_imx8mpl())
1526                 disable_vpu_nodes(blob);
1527
1528         if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1529                 disable_npu_nodes(blob);
1530
1531         if (is_imx8mpul() || is_imx8mpl())
1532                 disable_isp_nodes(blob);
1533
1534         if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
1535                 disable_dsp_nodes(blob);
1536
1537         if (is_imx8mpd())
1538                 disable_cpu_nodes(blob, 2);
1539 #endif
1540
1541         cleanup_nodes_for_efi(blob);
1542
1543         if (fixup_thermal_trips(blob, "cpu-thermal"))
1544                 printf("Failed to update cpu-thermal trip(s)");
1545         if (IS_ENABLED(CONFIG_IMX8MP) &&
1546             fixup_thermal_trips(blob, "soc-thermal"))
1547                 printf("Failed to update soc-thermal trip(s)");
1548
1549         return ft_add_optee_node(blob, bd);
1550 }
1551 #endif
1552
1553 #if !CONFIG_IS_ENABLED(SYSRESET)
1554 void reset_cpu(void)
1555 {
1556         struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
1557
1558         /* Clear WDA to trigger WDOG_B immediately */
1559         writew((SET_WCR_WT(1) | WCR_WDT | WCR_WDE | WCR_SRS), &wdog->wcr);
1560
1561         while (1) {
1562                 /*
1563                  * spin for .5 seconds before reset
1564                  */
1565         }
1566 }
1567 #endif
1568
1569 #if defined(CONFIG_ARCH_MISC_INIT)
1570 int arch_misc_init(void)
1571 {
1572         if (IS_ENABLED(CONFIG_FSL_CAAM)) {
1573                 struct udevice *dev;
1574                 int ret;
1575
1576                 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
1577                 if (ret)
1578                         printf("Failed to initialize caam_jr: %d\n", ret);
1579         }
1580
1581         return 0;
1582 }
1583 #endif
1584
1585 #if defined(CONFIG_SPL_BUILD)
1586 #if defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
1587 bool serror_need_skip = true;
1588
1589 void do_error(struct pt_regs *pt_regs)
1590 {
1591         /*
1592          * If stack is still in ROM reserved OCRAM not switch to SPL,
1593          * it is the ROM SError
1594          */
1595         ulong sp;
1596
1597         asm volatile("mov %0, sp" : "=r"(sp) : );
1598
1599         if (serror_need_skip && sp < 0x910000 && sp >= 0x900000) {
1600                 /* Check for ERR050342, imx8mq HDCP enabled parts */
1601                 if (is_imx8mq() && !(readl(OCOTP_BASE_ADDR + 0x450) & 0x08000000)) {
1602                         serror_need_skip = false;
1603                         return; /* Do nothing skip the SError in ROM */
1604                 }
1605
1606                 /* Check for ERR050350, field return mode for imx8mq, mm and mn */
1607                 if (readl(OCOTP_BASE_ADDR + 0x630) & 0x1) {
1608                         serror_need_skip = false;
1609                         return; /* Do nothing skip the SError in ROM */
1610                 }
1611         }
1612
1613         efi_restore_gd();
1614         printf("\"Error\" handler, esr 0x%08lx\n", pt_regs->esr);
1615         show_regs(pt_regs);
1616         panic("Resetting CPU ...\n");
1617 }
1618 #endif
1619 #endif
1620
1621 #if defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
1622 enum env_location arch_env_get_location(enum env_operation op, int prio)
1623 {
1624         enum boot_device dev = get_boot_device();
1625
1626         if (prio)
1627                 return ENVL_UNKNOWN;
1628
1629         switch (dev) {
1630         case USB_BOOT:
1631                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1632                         return ENVL_SPI_FLASH;
1633                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1634                         return ENVL_NAND;
1635                 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1636                         return ENVL_MMC;
1637                 if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE))
1638                         return ENVL_NOWHERE;
1639                 return ENVL_UNKNOWN;
1640         case QSPI_BOOT:
1641         case SPI_NOR_BOOT:
1642                 if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
1643                         return ENVL_SPI_FLASH;
1644                 return ENVL_NOWHERE;
1645         case NAND_BOOT:
1646                 if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
1647                         return ENVL_NAND;
1648                 return ENVL_NOWHERE;
1649         case SD1_BOOT:
1650         case SD2_BOOT:
1651         case SD3_BOOT:
1652         case MMC1_BOOT:
1653         case MMC2_BOOT:
1654         case MMC3_BOOT:
1655                 if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
1656                         return ENVL_MMC;
1657                 else if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
1658                         return ENVL_EXT4;
1659                 else if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
1660                         return ENVL_FAT;
1661                 return ENVL_NOWHERE;
1662         default:
1663                 return ENVL_NOWHERE;
1664         }
1665 }
1666
1667 #endif
1668
1669 #ifdef CONFIG_IMX_BOOTAUX
1670 const struct rproc_att hostmap[] = {
1671         /* aux core , host core,  size */
1672         { 0x00000000, 0x007e0000, 0x00020000 },
1673         /* OCRAM_S */
1674         { 0x00180000, 0x00180000, 0x00008000 },
1675         /* OCRAM */
1676         { 0x00900000, 0x00900000, 0x00020000 },
1677         /* OCRAM */
1678         { 0x00920000, 0x00920000, 0x00020000 },
1679         /* QSPI Code - alias */
1680         { 0x08000000, 0x08000000, 0x08000000 },
1681         /* DDR (Code) - alias */
1682         { 0x10000000, 0x80000000, 0x0FFE0000 },
1683         /* TCML */
1684         { 0x1FFE0000, 0x007E0000, 0x00040000 },
1685         /* OCRAM_S */
1686         { 0x20180000, 0x00180000, 0x00008000 },
1687         /* OCRAM */
1688         { 0x20200000, 0x00900000, 0x00040000 },
1689         /* DDR (Data) */
1690         { 0x40000000, 0x40000000, 0x80000000 },
1691         { /* sentinel */ }
1692 };
1693
1694 const struct rproc_att *imx_bootaux_get_hostmap(void)
1695 {
1696         return hostmap;
1697 }
1698 #endif
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