Commit | Line | Data |
---|---|---|
46263f2d | 1 | /* |
1b387ef5 | 2 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
46263f2d WD |
3 | * |
4 | * Additions (C) Copyright 2009 Industrie Dial Face S.p.A. | |
5 | */ | |
214ec6bb WD |
6 | /*----------------------------------------------------------------------------+ |
7 | | | |
65bd0e28 | 8 | | File Name: miiphy.h |
214ec6bb | 9 | | |
65bd0e28 | 10 | | Function: Include file defining PHY registers. |
214ec6bb | 11 | | |
65bd0e28 | 12 | | Author: Mark Wisner |
214ec6bb | 13 | | |
214ec6bb WD |
14 | +----------------------------------------------------------------------------*/ |
15 | #ifndef _miiphy_h_ | |
16 | #define _miiphy_h_ | |
17 | ||
5f184715 | 18 | #include <common.h> |
8ef583a0 | 19 | #include <linux/mii.h> |
5f184715 | 20 | #include <linux/list.h> |
63ff004c | 21 | #include <net.h> |
5f184715 AF |
22 | #include <phy.h> |
23 | ||
f915c931 | 24 | int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, |
298035df | 25 | unsigned short *value); |
f915c931 | 26 | int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, |
298035df | 27 | unsigned short value); |
16a53238 | 28 | int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, |
298035df | 29 | unsigned char *model, unsigned char *rev); |
16a53238 AF |
30 | int miiphy_reset(const char *devname, unsigned char addr); |
31 | int miiphy_speed(const char *devname, unsigned char addr); | |
32 | int miiphy_duplex(const char *devname, unsigned char addr); | |
33 | int miiphy_is_1000base_x(const char *devname, unsigned char addr); | |
6d0f6bcf | 34 | #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
16a53238 | 35 | int miiphy_link(const char *devname, unsigned char addr); |
fc3e2165 | 36 | #endif |
214ec6bb | 37 | |
16a53238 | 38 | void miiphy_init(void); |
d9785c14 | 39 | |
16a53238 AF |
40 | int miiphy_set_current_dev(const char *devname); |
41 | const char *miiphy_get_current_dev(void); | |
5f184715 AF |
42 | struct mii_dev *mdio_get_current_dev(void); |
43 | struct mii_dev *miiphy_get_dev_by_name(const char *devname); | |
44 | struct phy_device *mdio_phydev_for_ethname(const char *devname); | |
63ff004c | 45 | |
16a53238 | 46 | void miiphy_listdev(void); |
63ff004c | 47 | |
5f184715 | 48 | struct mii_dev *mdio_alloc(void); |
cb6baca7 | 49 | void mdio_free(struct mii_dev *bus); |
5f184715 | 50 | int mdio_register(struct mii_dev *bus); |
cb6baca7 | 51 | int mdio_unregister(struct mii_dev *bus); |
5f184715 AF |
52 | void mdio_list_devices(void); |
53 | ||
4ba31ab3 LCM |
54 | #ifdef CONFIG_BITBANGMII |
55 | ||
56 | #define BB_MII_DEVNAME "bb_miiphy" | |
57 | ||
58 | struct bb_miiphy_bus { | |
f6add132 | 59 | char name[16]; |
4ba31ab3 LCM |
60 | int (*init)(struct bb_miiphy_bus *bus); |
61 | int (*mdio_active)(struct bb_miiphy_bus *bus); | |
62 | int (*mdio_tristate)(struct bb_miiphy_bus *bus); | |
63 | int (*set_mdio)(struct bb_miiphy_bus *bus, int v); | |
64 | int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); | |
65 | int (*set_mdc)(struct bb_miiphy_bus *bus, int v); | |
66 | int (*delay)(struct bb_miiphy_bus *bus); | |
67 | #ifdef CONFIG_BITBANGMII_MULTI | |
68 | void *priv; | |
69 | #endif | |
70 | }; | |
71 | ||
72 | extern struct bb_miiphy_bus bb_miiphy_buses[]; | |
73 | extern int bb_miiphy_buses_num; | |
63ff004c | 74 | |
16a53238 | 75 | void bb_miiphy_init(void); |
dfcc496e JH |
76 | int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg); |
77 | int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, | |
78 | u16 value); | |
4ba31ab3 | 79 | #endif |
214ec6bb WD |
80 | |
81 | /* phy seed setup */ | |
65bd0e28 | 82 | #define AUTO 99 |
298035df | 83 | #define _1000BASET 1000 |
65bd0e28 WD |
84 | #define _100BASET 100 |
85 | #define _10BASET 10 | |
86 | #define HALF 22 | |
87 | #define FULL 44 | |
214ec6bb WD |
88 | |
89 | /* phy register offsets */ | |
8ef583a0 MF |
90 | #define MII_MIPSCR 0x11 |
91 | ||
92 | /* MII_LPA */ | |
298035df LJ |
93 | #define PHY_ANLPAR_PSB_802_3 0x0001 |
94 | #define PHY_ANLPAR_PSB_802_9 0x0002 | |
95 | ||
8ef583a0 | 96 | /* MII_CTRL1000 masks */ |
71bc6e64 LJ |
97 | #define PHY_1000BTCR_1000FD 0x0200 |
98 | #define PHY_1000BTCR_1000HD 0x0100 | |
99 | ||
8ef583a0 | 100 | /* MII_STAT1000 masks */ |
298035df LJ |
101 | #define PHY_1000BTSR_MSCF 0x8000 |
102 | #define PHY_1000BTSR_MSCR 0x4000 | |
103 | #define PHY_1000BTSR_LRS 0x2000 | |
104 | #define PHY_1000BTSR_RRS 0x1000 | |
105 | #define PHY_1000BTSR_1000FD 0x0800 | |
106 | #define PHY_1000BTSR_1000HD 0x0400 | |
855a496f | 107 | |
71bc6e64 | 108 | /* phy EXSR */ |
8ef583a0 MF |
109 | #define ESTATUS_1000XF 0x8000 |
110 | #define ESTATUS_1000XH 0x4000 | |
71bc6e64 | 111 | |
214ec6bb | 112 | #endif |