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1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * (C) Copyright 2016 Keymile AG | |
4 | * Rainer Boschung <rainer.boschung@keymile.com> | |
5 | * | |
6 | * Copyright 2013 Freescale Semiconductor, Inc. | |
7 | */ | |
8 | ||
42fdcebf | 9 | #include <event.h> |
37bfd9cb NF |
10 | #include <asm/cache.h> |
11 | #include <asm/fsl_fdt.h> | |
12 | #include <asm/fsl_law.h> | |
13 | #include <asm/fsl_liodn.h> | |
14 | #include <asm/fsl_portals.h> | |
15 | #include <asm/fsl_serdes.h> | |
16 | #include <asm/immap_85xx.h> | |
17 | #include <asm/mmu.h> | |
18 | #include <asm/processor.h> | |
19 | #include <fdt_support.h> | |
20 | #include <fm_eth.h> | |
21 | #include <hwconfig.h> | |
22 | #include <image.h> | |
23 | #include <linux/compiler.h> | |
24 | #include <net.h> | |
25 | #include <netdev.h> | |
26 | #include <vsc9953.h> | |
27 | ||
28 | #include "../common/common.h" | |
29 | #include "../common/qrio.h" | |
30 | ||
31 | DECLARE_GLOBAL_DATA_PTR; | |
32 | ||
33 | static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; | |
34 | ||
35 | int checkboard(void) | |
36 | { | |
6f7c936f | 37 | printf("Board: Hitachi Power Grids kmcent2\n"); |
37bfd9cb NF |
38 | |
39 | return 0; | |
40 | } | |
41 | ||
42 | #define RSTRQSR1_WDT_RR 0x00200000 | |
43 | #define RSTRQSR1_SW_RR 0x00100000 | |
44 | ||
45 | int board_early_init_f(void) | |
46 | { | |
65cc0e2a | 47 | struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL}; |
5155207a | 48 | ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); |
37bfd9cb NF |
49 | bool cpuwd_flag = false; |
50 | ||
51 | /* board specific IFC configuration: increased bus turnaround time */ | |
52 | setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); | |
53 | ||
54 | /* configure mode for uP reset request */ | |
55 | qrio_uprstreq(UPREQ_CORE_RST); | |
56 | ||
57 | /* board only uses the DDR_MCK0, so disable the DDR_MCK1 */ | |
58 | setbits_be32(&gur->ddrclkdr, 0x40000000); | |
59 | ||
60 | /* set reset reason according CPU register */ | |
61 | if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == | |
62 | RSTRQSR1_WDT_RR) | |
63 | cpuwd_flag = true; | |
64 | ||
65 | qrio_cpuwd_flag(cpuwd_flag); | |
66 | /* clear CPU bits by writing 1 */ | |
67 | setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); | |
68 | ||
69 | /* configure PRST lines for the application: */ | |
70 | /* | |
71 | * ETHSW_DDR_RST: | |
72 | * reset at power-up and unit reset only and enable WD on it | |
73 | */ | |
74 | qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST); | |
75 | qrio_wdmask(KM_ETHSW_DDR_RST, true); | |
76 | /* | |
77 | * XES_PHY_RST: | |
78 | * reset at power-up and unit reset only and enable WD on it | |
79 | */ | |
80 | qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST); | |
81 | qrio_wdmask(KM_XES_PHY_RST, true); | |
82 | /* | |
83 | * ES_PHY_RST: | |
84 | * reset at power-up and unit reset only and enable WD on it | |
85 | */ | |
86 | qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST); | |
87 | qrio_wdmask(KM_ES_PHY_RST, true); | |
88 | /* | |
89 | * EFE_RST: | |
90 | * reset at power-up and unit reset only and enable WD on it | |
91 | */ | |
92 | qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST); | |
93 | qrio_wdmask(KM_EFE_RST, true); | |
94 | /* | |
95 | * BFTIC4_RST: | |
96 | * reset at power-up and unit reset only and enable WD on it | |
97 | */ | |
98 | qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); | |
99 | qrio_wdmask(KM_BFTIC4_RST, true); | |
100 | /* | |
101 | * DPAXE_RST: | |
102 | * reset at power-up and unit reset only and enable WD on it | |
103 | */ | |
104 | qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST); | |
105 | qrio_wdmask(KM_DPAXE_RST, true); | |
106 | /* | |
107 | * PEXSW_RST: | |
108 | * reset at power-up and unit reset only, deassert reset w/o WD | |
109 | */ | |
110 | qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST); | |
111 | qrio_prst(KM_PEXSW_RST, false, false); | |
112 | /* | |
113 | * PEXSW_NT_RST: | |
114 | * reset at power-up and unit reset only, deassert reset w/o WD | |
115 | */ | |
116 | qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST); | |
117 | qrio_prst(KM_PEXSW_NT_RST, false, false); | |
118 | /* | |
119 | * BOBCAT_RST: | |
120 | * reset at power-up and unit reset only, deassert reset w/o WD | |
121 | */ | |
122 | qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST); | |
123 | qrio_prst(KM_BOBCAT_RST, false, false); | |
124 | /* | |
125 | * FEMT_RST: | |
126 | * reset at power-up and unit reset only and enable WD | |
127 | */ | |
128 | qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST); | |
129 | qrio_wdmask(KM_FEMT_RST, true); | |
130 | /* | |
131 | * FOAM_RST: | |
132 | * reset at power-up and unit reset only and enable WD | |
133 | */ | |
134 | qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST); | |
135 | qrio_wdmask(KM_FOAM_RST, true); | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | int board_early_init_r(void) | |
141 | { | |
142 | int ret = 0; | |
143 | ||
65cc0e2a | 144 | const unsigned int flashbase = CFG_SYS_FLASH_BASE; |
37bfd9cb NF |
145 | int flash_esel = find_tlb_idx((void *)flashbase, 1); |
146 | ||
147 | /* | |
148 | * Remap Boot flash region to caching-inhibited | |
149 | * so that flash can be erased properly. | |
150 | */ | |
151 | ||
152 | /* Flush d-cache and invalidate i-cache of any FLASH data */ | |
153 | flush_dcache(); | |
154 | invalidate_icache(); | |
155 | ||
156 | if (flash_esel == -1) { | |
157 | /* very unlikely unless something is messed up */ | |
158 | puts("Error: Could not find TLB for FLASH BASE\n"); | |
159 | flash_esel = 2; /* give our best effort to continue */ | |
160 | } else { | |
161 | /* invalidate existing TLB entry for flash */ | |
162 | disable_tlb(flash_esel); | |
163 | } | |
164 | ||
65cc0e2a | 165 | set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS, |
37bfd9cb NF |
166 | MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, |
167 | 0, flash_esel, BOOKE_PAGESZ_256M, 1); | |
168 | ||
169 | set_liodns(); | |
170 | setup_qbman_portals(); | |
171 | ||
172 | qrio_set_leds(); | |
173 | ||
174 | /* enable Application Buffer */ | |
175 | qrio_enable_app_buffer(); | |
176 | ||
177 | return ret; | |
178 | } | |
179 | ||
180 | unsigned long get_serial_clock(unsigned long dummy) | |
181 | { | |
182 | return (gd->bus_clk / 2); | |
183 | } | |
184 | ||
f72d0d4a | 185 | static int kmcent2_misc_init_f(void) |
37bfd9cb NF |
186 | { |
187 | /* configure QRIO pis for i2c deblocking */ | |
188 | i2c_deblock_gpio_cfg(); | |
189 | ||
190 | /* | |
191 | * CFE_RST (front phy): | |
192 | * reset at power-up, unit and core reset, deasset reset w/o WD | |
193 | */ | |
194 | qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST); | |
195 | qrio_prst(KM_CFE_RST, false, false); | |
196 | ||
197 | /* | |
198 | * ZL30158_RST (PTP clock generator): | |
199 | * reset at power-up only, deassert reset and enable WD on it | |
200 | */ | |
201 | qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST); | |
202 | qrio_prst(KM_ZL30158_RST, false, false); | |
203 | ||
204 | /* | |
205 | * ZL30364_RST (EEC generator): | |
206 | * reset at power-up only, deassert reset and enable WD on it | |
207 | */ | |
208 | qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST); | |
209 | qrio_prst(KM_ZL30364_RST, false, false); | |
210 | ||
211 | return 0; | |
212 | } | |
f72d0d4a | 213 | EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, kmcent2_misc_init_f); |
37bfd9cb NF |
214 | |
215 | #define USED_SRDS_BANK 0 | |
216 | #define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100 | |
217 | ||
218 | #define BRG01_IOCLK12 0x02000000 | |
219 | #define EC2_GTX_CLK125 0x08000000 | |
220 | ||
221 | int misc_init_r(void) | |
222 | { | |
6cc04547 | 223 | serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; |
5155207a TR |
224 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG; |
225 | ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR; | |
37bfd9cb NF |
226 | |
227 | /* check SERDES bank 0 reference clock */ | |
228 | u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0); | |
229 | ||
230 | if (actual & SRDS_PLLCR0_POFF) | |
231 | printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK); | |
232 | if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) { | |
233 | printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n", | |
234 | USED_SRDS_BANK, | |
235 | serdes_clock_to_string(EXPECTED_SRDS_RFCK), | |
236 | serdes_clock_to_string(actual)); | |
237 | } | |
238 | ||
239 | /* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */ | |
240 | out_be32(&scfg->qeioclkcr, | |
241 | in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12); | |
242 | ||
243 | ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, | |
244 | CONFIG_PIGGY_MAC_ADDRESS_OFFSET); | |
245 | ||
246 | /* Fix polarity of Card Detect and Write Protect */ | |
247 | out_be32(&gur->sdhcpcr, 0xFFFFFFFF); | |
248 | ||
249 | /* | |
250 | * EC1 is disabled in our design, so we must explicitly set GTXCLKSEL | |
251 | * to EC2 | |
252 | */ | |
253 | out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
258 | int hush_init_var(void) | |
259 | { | |
260 | ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); | |
261 | return 0; | |
262 | } | |
263 | ||
264 | int last_stage_init(void) | |
265 | { | |
266 | const char *kmem; | |
267 | /* DIP switch support on BFTIC */ | |
268 | struct bfticu_iomap *bftic4 = | |
269 | (struct bfticu_iomap *)SYS_BFTIC_BASE; | |
270 | u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK; | |
271 | ||
272 | if (dip_switch != 0) { | |
273 | /* start bootloader */ | |
274 | puts("DIP: Enabled\n"); | |
275 | env_set("actual_bank", "0"); | |
276 | } | |
277 | ||
278 | set_km_env(); | |
279 | ||
280 | /* | |
281 | * bootm_size is used to fixup the FDT memory node | |
282 | * set it to kernelmem that has the same value | |
283 | */ | |
284 | kmem = env_get("kernelmem"); | |
285 | if (kmem) | |
286 | env_set("bootm_size", kmem); | |
287 | ||
288 | return 0; | |
289 | } | |
290 | ||
291 | void fdt_fixup_fman_mac_addresses(void *blob) | |
292 | { | |
293 | int node, ret; | |
294 | char path[24]; | |
295 | unsigned char mac_addr[6]; | |
296 | ||
297 | /* | |
298 | * Just the fm1-mac5 must be set by us, u-boot handle the 2 others, | |
299 | * get the mac addr from env | |
300 | */ | |
301 | if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) { | |
302 | printf("eth4addr env variable not defined\n"); | |
303 | return; | |
304 | } | |
305 | ||
306 | /* local management port */ | |
307 | strcpy(path, "/soc/fman/ethernet@e8000"); | |
308 | node = fdt_path_offset(blob, path); | |
309 | if (node < 0) { | |
310 | printf("no %s\n", path); | |
311 | return; | |
312 | } | |
313 | ||
314 | ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); | |
315 | if (ret) { | |
316 | printf("%s\n\terror setting local-mac-address property\n", | |
317 | path); | |
318 | } | |
319 | } | |
320 | ||
321 | int ft_board_setup(void *blob, struct bd_info *bd) | |
322 | { | |
323 | phys_addr_t base; | |
324 | phys_size_t size; | |
325 | ||
326 | ft_cpu_setup(blob, bd); | |
327 | ||
328 | base = env_get_bootm_low(); | |
329 | size = env_get_bootm_size(); | |
330 | ||
331 | fdt_fixup_memory(blob, (u64)base, (u64)size); | |
332 | ||
333 | fdt_fixup_liodn(blob); | |
334 | ||
335 | fdt_fixup_fman_mac_addresses(blob); | |
336 | ||
337 | if (hwconfig("qe-tdm")) | |
338 | fdt_del_diu(blob); | |
339 | return 0; | |
340 | } | |
341 | ||
342 | /* DIC26_SELFTEST GPIO used to start factory test sw */ | |
343 | #define SELFTEST_PORT QRIO_GPIO_A | |
344 | #define SELFTEST_PIN 0 | |
345 | ||
346 | int post_hotkeys_pressed(void) | |
347 | { | |
348 | qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); | |
349 | return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); | |
350 | } |