[J-u-boot.git] / arch / arm / include / asm / arch-kirkwood / config.h

/*
 * (C) Copyright 2011
 * Marvell Semiconductor <www.marvell.com>
 * Written-by: Lei Wen <leiwen@marvell.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301 USA
 */

/*
 * This file should be included in board config header file.
 *
 * It supports common definitions for Kirkwood platform
 */

#ifndef _KW_CONFIG_H
#define _KW_CONFIG_H

#if defined (CONFIG_KW88F6281)
#include <asm/arch/kw88f6281.h>
#elif defined (CONFIG_KW88F6192)
#include <asm/arch/kw88f6192.h>
#else
#error "SOC Name not defined"
#endif /* CONFIG_KW88F6281 */

#include <asm/arch/kirkwood.h>
#define CONFIG_ARM926EJS	1	/* Basic Architecture */
#define CONFIG_SYS_CACHELINE_SIZE	32
				/* default Dcache Line length for kirkwood */
#define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8	/* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT       /* Enable PCIE Port0 for kernel */

/*
 * By default kwbimage.cfg from board specific folder is used
 * If for some board, different configuration file need to be used,
 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
 */
#ifndef CONFIG_SYS_KWD_CONFIG
#define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
#endif /* CONFIG_SYS_KWD_CONFIG */

/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
#define CONFIG_NR_DRAM_BANKS_MAX	2

#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
#define MV_SATA_BASE		KW_SATA_BASE
#define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
#define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET

/*
 * NAND configuration
 */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
#define CONFIG_SYS_NAND_BASE		0xD8000000	/* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL		1
#endif

/*
 * SPI Flash configuration
 */
#ifdef CONFIG_CMD_SF
#define CONFIG_HARD_SPI			1
#define CONFIG_KIRKWOOD_SPI		1
#ifndef CONFIG_ENV_SPI_BUS
# define CONFIG_ENV_SPI_BUS		0
#endif
#ifndef CONFIG_ENV_SPI_CS
# define CONFIG_ENV_SPI_CS		0
#endif
#ifndef CONFIG_ENV_SPI_MAX_HZ
# define CONFIG_ENV_SPI_MAX_HZ		50000000
#endif
#endif

/*
 * Ethernet Driver configuration
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_NETCONSOLE	/* include NetConsole support   */
#define CONFIG_MII		/* expose smi ove miiphy interface */
#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */

/*
 * USB/EHCI
 */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MARVELL
#define CONFIG_EHCI_IS_TDI
#endif /* CONFIG_CMD_USB */

/*
 * IDE Support on SATA ports
 */
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_CMD_EXT2
#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET	(0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE		4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS		2
#define CONFIG_SYS_IDE_MAXDEVICE	2
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR	MV_SATA_BASE
#endif /* CONFIG_CMD_IDE */

/*
 * I2C related stuff
 */
#ifdef CONFIG_CMD_I2C
#ifndef CONFIG_SYS_I2C_SOFT
#define CONFIG_I2C_MVTWSI
#endif
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_SPEED		100000
#endif

#endif /* _KW_CONFIG_H */
Commit	Line	Data
cf946c6d LW	1	/*
	2	* (C) Copyright 2011
	3	* Marvell Semiconductor <www.marvell.com>
	4	* Written-by: Lei Wen <leiwen@marvell.com>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	22	* MA 02110-1301 USA
	23	*/
	24
	25	/*
	26	* This file should be included in board config header file.
	27	*
	28	* It supports common definitions for Kirkwood platform
	29	*/
	30
	31	#ifndef _KW_CONFIG_H
	32	#define _KW_CONFIG_H
	33
	34	#if defined (CONFIG_KW88F6281)
	35	#include <asm/arch/kw88f6281.h>
	36	#elif defined (CONFIG_KW88F6192)
	37	#include <asm/arch/kw88f6192.h>
	38	#else
	39	#error "SOC Name not defined"
	40	#endif /* CONFIG_KW88F6281 */
	41
a7efd719	42	#include <asm/arch/kirkwood.h>
cf946c6d	43	#define CONFIG_ARM926EJS 1 /* Basic Architecture */
f779d739 MW	44	#define CONFIG_SYS_CACHELINE_SIZE 32
f779d739 MW	45	/* default Dcache Line length for kirkwood */
cf946c6d LW	46	#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
	47	#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
	48	#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
	49	#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
	50
	51	/*
	52	* By default kwbimage.cfg from board specific folder is used
	53	* If for some board, different configuration file need to be used,
	54	* CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
	55	*/
	56	#ifndef CONFIG_SYS_KWD_CONFIG
	57	#define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
	58	#endif /* CONFIG_SYS_KWD_CONFIG */
	59
	60	/* Kirkwood has 2k of Security SRAM, use it for SP */
	61	#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
	62	#define CONFIG_NR_DRAM_BANKS_MAX 2
	63
	64	#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
	65	#define MV_UART_CONSOLE_BASE KW_UART0_BASE
	66	#define MV_SATA_BASE KW_SATA_BASE
	67	#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
	68	#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
	69
	70	/*
	71	* NAND configuration
	72	*/
	73	#ifdef CONFIG_CMD_NAND
	74	#define CONFIG_NAND_KIRKWOOD
	75	#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
	76	#define NAND_ALLOW_ERASE_ALL 1
	77	#endif
	78
	79	/*
	80	* SPI Flash configuration
	81	*/
	82	#ifdef CONFIG_CMD_SF
	83	#define CONFIG_HARD_SPI 1
	84	#define CONFIG_KIRKWOOD_SPI 1
dacc8c6f VL	85	#ifndef CONFIG_ENV_SPI_BUS
	86	# define CONFIG_ENV_SPI_BUS 0
	87	#endif
	88	#ifndef CONFIG_ENV_SPI_CS
	89	# define CONFIG_ENV_SPI_CS 0
	90	#endif
	91	#ifndef CONFIG_ENV_SPI_MAX_HZ
	92	# define CONFIG_ENV_SPI_MAX_HZ 50000000
	93	#endif
cf946c6d LW	94	#endif
	95
	96	/*
	97	* Ethernet Driver configuration
	98	*/
	99	#ifdef CONFIG_CMD_NET
	100	#define CONFIG_CMD_MII
	101	#define CONFIG_NETCONSOLE /* include NetConsole support */
cf946c6d LW	102	#define CONFIG_MII /* expose smi ove miiphy interface */
	103	#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
	104	#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
	105	#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
	106	#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
	107	#endif /* CONFIG_CMD_NET */
	108
	109	/*
	110	* USB/EHCI
	111	*/
	112	#ifdef CONFIG_CMD_USB
a14bd417	113	#define CONFIG_USB_EHCI_MARVELL
cf946c6d LW	114	#define CONFIG_EHCI_IS_TDI
	115	#endif /* CONFIG_CMD_USB */
	116
	117	/*
	118	* IDE Support on SATA ports
	119	*/
	120	#ifdef CONFIG_CMD_IDE
	121	#define __io
	122	#define CONFIG_CMD_EXT2
	123	#define CONFIG_MVSATA_IDE
	124	#define CONFIG_IDE_PREINIT
	125	#define CONFIG_MVSATA_IDE_USE_PORT1
	126	/* Needs byte-swapping for ATA data register */
	127	#define CONFIG_IDE_SWAP_IO
	128	/* Data, registers and alternate blocks are at the same offset */
	129	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
	130	#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
	131	#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
	132	/* Each 8-bit ATA register is aligned to a 4-bytes address */
	133	#define CONFIG_SYS_ATA_STRIDE 4
	134	/* Controller supports 48-bits LBA addressing */
	135	#define CONFIG_LBA48
	136	/* CONFIG_CMD_IDE requires some #defines for ATA registers */
	137	#define CONFIG_SYS_IDE_MAXBUS 2
	138	#define CONFIG_SYS_IDE_MAXDEVICE 2
	139	/* ATA registers base is at SATA controller base */
	140	#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
	141	#endif /* CONFIG_CMD_IDE */
	142
	143	/*
	144	* I2C related stuff
	145	*/
	146	#ifdef CONFIG_CMD_I2C
ea818dbb	147	#ifndef CONFIG_SYS_I2C_SOFT
cf946c6d	148	#define CONFIG_I2C_MVTWSI
b31a82e9	149	#endif
cf946c6d LW	150	#define CONFIG_SYS_I2C_SLAVE 0x0
	151	#define CONFIG_SYS_I2C_SPEED 100000
	152	#endif
	153
	154	#endif /* _KW_CONFIG_H */