[J-u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1

/* Open Firmware DTS */
#define CONFIG_OF_CONTROL	1
#define CONFIG_OF_EMBED		1
#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
# define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS16550		1
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
#  define CONFIG_SYS_NS16550_REG_SIZE	-4
# else
#  define CONFIG_SYS_NS16550_REG_SIZE	4
# endif
# define CONFIG_CONS_INDEX		1
# define CONFIG_SYS_NS16550_COM1 \
		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE	115200

/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG	"console=console=ttyS0,115200\0"
#else
# error Undefined uart
#endif

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
# define CONFIG_XILINX_EMACLITE	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_LLTEMAC_BASEADDR)
# define CONFIG_XILINX_LL_TEMAC	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC	1
# define CONFIG_SYS_ENET
#endif

#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# define CONFIG_HW_WATCHDOG
# define CONFIG_XILINX_TB_WATCHDOG
#endif

/*
 * memory layout - Example
 * CONFIG_SYS_TEXT_BASE = 0x1200_0000;	defined in config.mk
 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;	64MB
 *
 * CONFIG_SYS_MONITOR_LEN = 0x40000
 * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
 *
 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
 *
 * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
 *					MEMTEST_AREA	 64kB
 *					FREE
 * 0x1200_0000	CONFIG_SYS_TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13EF_F000	CONFIG_SYS_MALLOC_BASE
 *					MALLOC_AREA	768kB	Alloc
 * 0x13FB_F000	CONFIG_SYS_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)

/* global pointer */
/* start of global data */
#define	CONFIG_SYS_GBL_DATA_OFFSET \
		(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* monitor code */
#define	SIZE				0x40000
#define	CONFIG_SYS_MONITOR_LEN		SIZE
#define	CONFIG_SYS_MONITOR_BASE	\
		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
			- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
#define	CONFIG_SYS_MONITOR_END \
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		(SIZE * 3)
#define	CONFIG_SYS_MALLOC_BASE \
			(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)

/* stack */
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_XILINX_SPI		1
# define CONFIG_SPI			1
# define CONFIG_SPI_FLASH		1
# define CONFIG_SPI_FLASH_STMICRO	1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_GPIO

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#ifndef CONFIG_SYS_ENET
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#else
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif

#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
# define CONFIG_CMD_ECHO
# define CONFIG_CMD_FLASH
# define CONFIG_CMD_IMLS
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_IMLS
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"

#define CONFIG_CMDLINE_EDITING

#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHYLIB		1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
# undef CONFIG_PHYLIB
#endif

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_NOR_SUPPORT

/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT

#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x60000)
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
/* Stack pointer prior relocation, must situated at on-chip RAM */
#define CONFIG_SYS_SPL_MALLOC_END	(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100

/*
 * The main reason to do it in this way is that MALLOC_START
 * can't be defined - common/spl/spl.c
 */
#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
# define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_SPL_MALLOC_END - \
					 CONFIG_SYS_SPL_MALLOC_SIZE)
# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_START
#else
# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_END
#endif

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 GENERATED_GBL_DATA_SIZE - \
					 CONFIG_SYS_SPL_MALLOC_SIZE - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16	14	/* MicroBlaze CPU */
1a50f164	15	#define MICROBLAZE_V5 1
76316a31	16
920c3587 SL	17	/* Open Firmware DTS */
	18	#define CONFIG_OF_CONTROL 1
	19	#define CONFIG_OF_EMBED 1
6697d558	20	#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
920c3587	21
bcec8f49	22	/* linear and spi flash memory */
1fe7e8fa SL	23	#ifdef XILINX_FLASH_START
1fe7e8fa SL	24	#define FLASH
bcec8f49	25	#undef SPIFLASH
1fe7e8fa SL	26	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	27	#else
bcec8f49	28	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	29	#undef FLASH
bcec8f49 SL	30	#define SPIFLASH
	31	#undef RAMENV /* hold environment in flash */
	32	#else
	33	#undef FLASH
	34	#undef SPIFLASH
1fe7e8fa SL	35	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	36	#endif
bcec8f49	37	#endif
1fe7e8fa	38
76316a31	39	/* uart */
af7ae1a4	40	#ifdef XILINX_UARTLITE_BASEADDR
4aecfb16 MS	41	# define CONFIG_XILINX_UARTLITE
	42	# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
	43	# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
	44	# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	45	# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
e7d591e8	46	#elif XILINX_UART16550_BASEADDR
4aecfb16 MS	47	# define CONFIG_SYS_NS16550 1
4aecfb16 MS	48	# define CONFIG_SYS_NS16550_SERIAL
1de55ef1 SL	49	# if defined(__MICROBLAZEEL__)
	50	# define CONFIG_SYS_NS16550_REG_SIZE -4
	51	# else
	52	# define CONFIG_SYS_NS16550_REG_SIZE 4
	53	# endif
4aecfb16 MS	54	# define CONFIG_CONS_INDEX 1
4aecfb16 MS	55	# define CONFIG_SYS_NS16550_COM1 \
1de55ef1	56	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
4aecfb16 MS	57	# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	58	# define CONFIG_BAUDRATE 115200
	59
	60	/* The following table includes the supported baudrates */
	61	# define CONFIG_SYS_BAUDRATE_TABLE \
	62	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	63	# define CONSOLE_ARG "console=console=ttyS0,115200\0"
e7d591e8	64	#else
4aecfb16	65	# error Undefined uart
af7ae1a4	66	#endif
76316a31 MS	67
76316a31 MS	68	/* setting reset address */
14d0a02a	69	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31	70
17980495	71	/* ethernet */
1252df06	72	#undef CONFIG_SYS_ENET
d1d37b5c	73	#if defined(XILINX_EMACLITE_BASEADDR) \|\| defined(CONFIG_OF_CONTROL)
8422a35e	74	# define CONFIG_XILINX_EMACLITE 1
4aecfb16	75	# define CONFIG_SYS_ENET
8422a35e SL	76	#endif
	77	#if defined(XILINX_LLTEMAC_BASEADDR)
	78	# define CONFIG_XILINX_LL_TEMAC 1
4aecfb16	79	# define CONFIG_SYS_ENET
e5845e21	80	#endif
e634138e MS	81	#if defined(XILINX_AXIEMAC_BASEADDR)
	82	# define CONFIG_XILINX_AXIEMAC 1
	83	# define CONFIG_SYS_ENET
	84	#endif
330e5545	85
e5845e21	86	#undef ET_DEBUG
17980495	87
76316a31	88	/* gpio */
4c6a6f02	89	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	90	# define CONFIG_XILINX_GPIO
4aecfb16	91	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	92	#endif
76316a31 MS	93
76316a31 MS	94	/* interrupt controller */
4d49b280	95	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	96	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	97	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	98	#endif
76316a31 MS	99
76316a31 MS	100	/* timer */
bcbb046b	101	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	102	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	103	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	104	#endif
bcbb046b	105
0f21f98d MS	106	/* watchdog */
	107	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	108	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	109	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
	110	# define CONFIG_HW_WATCHDOG
	111	# define CONFIG_XILINX_TB_WATCHDOG
	112	#endif
	113
76316a31 MS	114	/*
76316a31 MS	115	* memory layout - Example
8f371b18	116	* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
6d0f6bcf	117	* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
8f371b18 SL	118	* CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
	119	*
	120	* CONFIG_SYS_MONITOR_LEN = 0x40000
	121	* CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
76316a31	122	*
6d0f6bcf	123	* CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
8f371b18 SL	124	* CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
8f371b18 SL	125	* CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
76316a31	126	*
6d0f6bcf	127	* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
8f371b18	128	* MEMTEST_AREA 64kB
76316a31	129	* FREE
14d0a02a	130	* 0x1200_0000 CONFIG_SYS_TEXT_BASE
76316a31 MS	131	* U-BOOT code
	132	* 0x1202_0000
	133	* FREE
	134	*
	135	* STACK
8f371b18 SL	136	* 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
	137	* MALLOC_AREA 768kB Alloc
	138	* 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
17980495	139	* MONITOR_CODE 256kB Env
6d0f6bcf	140	* 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
853643d8	141	* GLOBAL_DATA 4kB bd, gd
6d0f6bcf	142	* 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
76316a31 MS	143	*/
	144
	145	/* ddr sdram - main memory */
6d0f6bcf JCPV	146	#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	147	#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	148	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	149	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
76316a31 MS	150
76316a31 MS	151	/* global pointer */
32556443	152	/* start of global data */
4aecfb16	153	#define CONFIG_SYS_GBL_DATA_OFFSET \
1020286e	154	(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
76316a31 MS	155
76316a31 MS	156	/* monitor code */
4aecfb16	157	#define SIZE 0x40000
1020286e	158	#define CONFIG_SYS_MONITOR_LEN SIZE
4aecfb16	159	#define CONFIG_SYS_MONITOR_BASE \
1020286e MS	160	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
1020286e MS	161	- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
4aecfb16 MS	162	#define CONFIG_SYS_MONITOR_END \
4aecfb16 MS	163	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
7cfb13a7	164	#define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
4aecfb16 MS	165	#define CONFIG_SYS_MALLOC_BASE \
4aecfb16 MS	166	(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
76316a31 MS	167
76316a31 MS	168	/* stack */
8fe7b29f	169	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
76316a31	170
8f371b18 SL	171	/*
	172	* CFI flash memory layout - Example
	173	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	174	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	175	*
	176	* SECT_SIZE = 0x20000; 128kB is one sector
	177	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	178	*
	179	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	180	* FREE 256kB
	181	* 0x2204_0000 CONFIG_ENV_ADDR
	182	* ENV_AREA 128kB
	183	* 0x2206_0000
	184	* FREE
	185	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	186	*
	187	*/
	188
76316a31	189	#ifdef FLASH
4aecfb16 MS	190	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	191	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	192	# define CONFIG_SYS_FLASH_CFI 1
	193	# define CONFIG_FLASH_CFI_DRIVER 1
	194	/* ?empty sector */
	195	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	196	/* max number of memory banks */
	197	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	198	/* max number of sectors on one chip */
	199	# define CONFIG_SYS_MAX_FLASH_SECT 512
	200	/* hardware flash protection */
	201	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	202	/* use buffered writes (20x faster) */
22ff7f4d MS	203	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16 MS	204	# ifdef RAMENV
	205	# define CONFIG_ENV_IS_NOWHERE 1
	206	# define CONFIG_ENV_SIZE 0x1000
	207	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	208
bcec8f49	209	# else /* FLASH && !RAMENV */
4aecfb16 MS	210	# define CONFIG_ENV_IS_IN_FLASH 1
	211	/* 128K(one sector) for env */
	212	# define CONFIG_ENV_SECT_SIZE 0x20000
	213	# define CONFIG_ENV_ADDR \
	214	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	215	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	216	# endif /* FLASH && !RAMBOOT */
76316a31	217	#else /* !FLASH */
bcec8f49 SL	218
	219	#ifdef SPIFLASH
	220	# define CONFIG_SYS_NO_FLASH 1
	221	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
	222	# define CONFIG_XILINX_SPI 1
	223	# define CONFIG_SPI 1
	224	# define CONFIG_SPI_FLASH 1
	225	# define CONFIG_SPI_FLASH_STMICRO 1
	226	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	227	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	228	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	229
	230	# ifdef RAMENV
	231	# define CONFIG_ENV_IS_NOWHERE 1
	232	# define CONFIG_ENV_SIZE 0x1000
	233	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	234
	235	# else /* SPIFLASH && !RAMENV */
	236	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	237	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	238	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	239	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	240	/* 128K(two sectors) for env */
	241	# define CONFIG_ENV_SECT_SIZE 0x10000
	242	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	243	/* Warning: adjust the offset in respect of other flash content and size */
	244	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	245	# endif /* SPIFLASH && !RAMBOOT */
	246	#else /* !SPIFLASH */
	247
4aecfb16 MS	248	/* ENV in RAM */
	249	# define CONFIG_SYS_NO_FLASH 1
	250	# define CONFIG_ENV_IS_NOWHERE 1
	251	# define CONFIG_ENV_SIZE 0x1000
	252	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	253	#endif /* !SPIFLASH */
76316a31 MS	254	#endif /* !FLASH */
76316a31 MS	255
853643d8 MS	256	/* system ace */
853643d8 MS	257	#ifdef XILINX_SYSACE_BASEADDR
4aecfb16 MS	258	# define CONFIG_SYSTEMACE
	259	/* #define DEBUG_SYSTEMACE */
	260	# define SYSTEMACE_CONFIG_FPGA
	261	# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	262	# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	263	# define CONFIG_DOS_PARTITION
853643d8 MS	264	#endif
853643d8 MS	265
e9b737de	266	#if defined(XILINX_USE_ICACHE)
4aecfb16	267	# define CONFIG_ICACHE
e9b737de	268	#else
4aecfb16	269	# undef CONFIG_ICACHE
e9b737de MS	270	#endif
	271
	272	#if defined(XILINX_USE_DCACHE)
4aecfb16	273	# define CONFIG_DCACHE
e9b737de	274	#else
4aecfb16	275	# undef CONFIG_DCACHE
e9b737de MS	276	#endif
e9b737de MS	277
5811830f MS	278	#ifndef XILINX_DCACHE_BYTE_SIZE
	279	#define XILINX_DCACHE_BYTE_SIZE 32768
	280	#endif
	281
079a136c JL	282	/*
	283	* BOOTP options
	284	*/
	285	#define CONFIG_BOOTP_BOOTFILESIZE
	286	#define CONFIG_BOOTP_BOOTPATH
	287	#define CONFIG_BOOTP_GATEWAY
	288	#define CONFIG_BOOTP_HOSTNAME
76316a31	289
5dc11a51 JL	290	/*
	291	* Command line configuration.
	292	*/
	293	#include <config_cmd_default.h>
	294
	295	#define CONFIG_CMD_ASKENV
5dc11a51	296	#define CONFIG_CMD_IRQ
5dc11a51	297	#define CONFIG_CMD_MFSL
330e5545	298	#define CONFIG_CMD_ECHO
4e779ad2	299	#define CONFIG_CMD_GPIO
4d49b280	300
e9b737de	301	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	302	# define CONFIG_CMD_CACHE
e9b737de	303	#else
4aecfb16	304	# undef CONFIG_CMD_CACHE
e9b737de MS	305	#endif
e9b737de MS	306
6d0f6bcf	307	#ifndef CONFIG_SYS_ENET
4aecfb16	308	# undef CONFIG_CMD_NET
1252df06	309	# undef CONFIG_CMD_NFS
4d49b280	310	#else
4aecfb16 MS	311	# define CONFIG_CMD_PING
4aecfb16 MS	312	# define CONFIG_CMD_DHCP
4eb29cf0	313	# define CONFIG_CMD_TFTPPUT
4d49b280	314	#endif
853643d8 MS	315
853643d8 MS	316	#if defined(CONFIG_SYSTEMACE)
4aecfb16 MS	317	# define CONFIG_CMD_EXT2
4aecfb16 MS	318	# define CONFIG_CMD_FAT
853643d8	319	#endif
5dc11a51 JL	320
5dc11a51 JL	321	#if defined(FLASH)
4aecfb16 MS	322	# define CONFIG_CMD_ECHO
	323	# define CONFIG_CMD_FLASH
	324	# define CONFIG_CMD_IMLS
	325	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	326	# define CONFIG_CMD_UBI
7cfb13a7 SL	327	# undef CONFIG_CMD_UBIFS
4aecfb16	328
bcec8f49 SL	329	# if !defined(RAMENV)
	330	# define CONFIG_CMD_SAVEENV
	331	# define CONFIG_CMD_SAVES
	332	# endif
	333
	334	#else
	335	#if defined(SPIFLASH)
	336	# define CONFIG_CMD_SF
	337
4aecfb16 MS	338	# if !defined(RAMENV)
	339	# define CONFIG_CMD_SAVEENV
	340	# define CONFIG_CMD_SAVES
	341	# endif
853643d8	342	#else
4aecfb16 MS	343	# undef CONFIG_CMD_IMLS
	344	# undef CONFIG_CMD_FLASH
	345	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	346	# undef CONFIG_CMD_UBI
2cce2d32 SL	347	# undef CONFIG_CMD_UBIFS
5dc11a51	348	#endif
bcec8f49	349	#endif
76316a31	350
5dc11a51	351	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	352	# define CONFIG_MTD_PARTITIONS
	353	#endif
	354
	355	#if defined(CONFIG_CMD_UBIFS)
	356	# define CONFIG_CMD_UBI
	357	# define CONFIG_LZO
	358	#endif
	359
	360	#if defined(CONFIG_CMD_UBI)
	361	# define CONFIG_MTD_PARTITIONS
	362	# define CONFIG_RBTREE
	363	#endif
	364
	365	#if defined(CONFIG_MTD_PARTITIONS)
	366	/* MTD partitions */
68d7d651	367	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	368	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	369	#define CONFIG_FLASH_CFI_MTD
c82a541d	370	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	371
144876a3 MS	372	/* default mtd partition table */
c82a541d	373	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	374	"256k(env),3m(kernel),1m(romfs),"\
	375	"1m(cramfs),-(jffs2)"
	376	#endif
	377
76316a31	378	/* Miscellaneous configurable options */
6d0f6bcf	379	#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
4aecfb16 MS	380	/* size of console buffer */
	381	#define CONFIG_SYS_CBSIZE 512
	382	/* print buffer size */
	383	#define CONFIG_SYS_PBSIZE \
	384	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	385	/* max number of command args */
	386	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	387	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	388	/* default load address */
4aecfb16 MS	389	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	390
330e5545	391	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	392	#define CONFIG_BOOTARGS "root=romfs"
330e5545	393	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	394	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	395	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	396	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	397	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	398	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	399
	400	/* architecture dependent code */
6d0f6bcf	401	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	402
0900bee9	403	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	404
4aecfb16	405	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	406	"nor0=flash-0\0"\
c82a541d SL	407	"mtdparts=mtdparts=flash-0:"\
144876a3	408	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	409	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	410	"nc=setenv stdout nc;"\
	411	"setenv stdin nc\0" \
	412	"serial=setenv stdout serial;"\
	413	"setenv stdin serial\0"
144876a3	414
188dc16b	415	#define CONFIG_CMDLINE_EDITING
188dc16b	416
78376452 MS	417	#define CONFIG_NETCONSOLE
	418	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	419
0900bee9 MS	420	/* Use the HUSH parser */
0900bee9 MS	421	#define CONFIG_SYS_HUSH_PARSER
0900bee9	422
37e892d9 MS	423	/* Enable flat device tree support */
	424	#define CONFIG_LMB 1
	425	#define CONFIG_FIT 1
	426	#define CONFIG_OF_LIBFDT 1
	427
8422a35e	428	#if defined(CONFIG_XILINX_LL_TEMAC) \|\| defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	429	# define CONFIG_MII 1
	430	# define CONFIG_CMD_MII 1
	431	# define CONFIG_PHY_GIGE 1
	432	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
	433	# define CONFIG_PHYLIB 1
	434	# define CONFIG_PHY_ATHEROS 1
	435	# define CONFIG_PHY_BROADCOM 1
	436	# define CONFIG_PHY_DAVICOM 1
	437	# define CONFIG_PHY_LXT 1
	438	# define CONFIG_PHY_MARVELL 1
	439	# define CONFIG_PHY_MICREL 1
	440	# define CONFIG_PHY_NATSEMI 1
	441	# define CONFIG_PHY_REALTEK 1
	442	# define CONFIG_PHY_VITESSE 1
	443	#else
	444	# undef CONFIG_MII
	445	# undef CONFIG_CMD_MII
	446	# undef CONFIG_PHYLIB
	447	#endif
	448
9d242745	449	/* SPL part */
9d242745 MS	450	#define CONFIG_CMD_SPL
	451	#define CONFIG_SPL_FRAMEWORK
	452	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	453	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	454	#define CONFIG_SPL_SERIAL_SUPPORT
	455	#define CONFIG_SPL_BOARD_INIT
	456
	457	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	458
	459	#define CONFIG_SPL_RAM_DEVICE
	460	#define CONFIG_SPL_NOR_SUPPORT
	461
	462	/* for booting directly linux */
	463	#define CONFIG_SPL_OS_BOOT
	464
	465	#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	466	0x60000)
	467	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	468	0x40000)
	469	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	470	0x1000000)
	471
	472	/* SP location before relocation, must use scratch RAM */
	473	/* BRAM start */
	474	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	475	/* BRAM size - will be generated */
	476	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	477	/* Stack pointer prior relocation, must situated at on-chip RAM */
	478	#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
	479	CONFIG_SYS_INIT_RAM_SIZE - \
	480	GENERATED_GBL_DATA_SIZE)
	481
	482	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
	483
	484	/*
	485	* The main reason to do it in this way is that MALLOC_START
	486	* can't be defined - common/spl/spl.c
	487	*/
	488	#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
	489	# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
	490	CONFIG_SYS_SPL_MALLOC_SIZE)
	491	# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
	492	#else
	493	# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
	494	#endif
	495
	496	/* Just for sure that there is a space for stack */
	497	#define CONFIG_SPL_STACK_SIZE 0x100
	498
	499	#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	500	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	501
	502	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	503	CONFIG_SYS_INIT_RAM_ADDR - \
	504	GENERATED_GBL_DATA_SIZE - \
	505	CONFIG_SYS_SPL_MALLOC_SIZE - \
	506	CONFIG_SPL_STACK_SIZE)
	507
76316a31	508	#endif /* __CONFIG_H */