projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 26749582 AB |
1 | /* |
| 2 | * (C) Copyright 2011 | |
| 3 | * eInfochips Ltd. <www.einfochips.com> | |
| 4 | * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com> | |
| 5 | * | |
| 6 | * Based on Aspenite: | |
| 7 | * (C) Copyright 2010 | |
| 8 | * Marvell Semiconductor <www.marvell.com> | |
| 9 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
| 10 | * Contributor: Mahavir Jain <mjain@marvell.com> | |
| 11 | * | |
| 12 | * See file CREDITS for list of people who contributed to this | |
| 13 | * project. | |
| 14 | * | |
| 15 | * This program is free software; you can redistribute it and/or | |
| 16 | * modify it under the terms of the GNU General Public License as | |
| 17 | * published by the Free Software Foundation; either version 2 of | |
| 18 | * the License, or (at your option) any later version. | |
| 19 | * | |
| 20 | * This program is distributed in the hope that it will be useful, | |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 23 | * GNU General Public License for more details. | |
| 24 | * | |
| 25 | * You should have received a copy of the GNU General Public License | |
| 26 | * along with this program; if not, write to the Free Software | |
| 27 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
| 28 | * MA 02110-1301 USA | |
| 29 | */ | |
| 30 | ||
| 31 | #include <common.h> | |
| 32 | #include <mvmfp.h> | |
| 33 | #include <asm/arch/mfp.h> | |
| 34 | #include <asm/arch/armada100.h> | |
| 47e75d72 AB |
35 | #include <asm/gpio.h> |
| 36 | #include <miiphy.h> | |
| 26749582 | 37 | |
| aa0ecfeb AB |
38 | #ifdef CONFIG_ARMADA100_FEC |
| 39 | #include <net.h> | |
| 40 | #include <netdev.h> | |
| 41 | #endif /* CONFIG_ARMADA100_FEC */ | |
| 42 | ||
| 26749582 AB |
43 | DECLARE_GLOBAL_DATA_PTR; |
| 44 | ||
| 45 | int board_early_init_f(void) | |
| 46 | { | |
| 47 | u32 mfp_cfg[] = { | |
| 48 | /* I2C */ | |
| 49 | MFP105_CI2C_SDA, | |
| 50 | MFP106_CI2C_SCL, | |
| 51 | ||
| 52 | /* Enable Console on UART3 */ | |
| 53 | MFPO8_UART3_TXD, | |
| 54 | MFPO9_UART3_RXD, | |
| aa0ecfeb AB |
55 | |
| 56 | /* Ethernet PHY Interface */ | |
| 57 | MFP086_ETH_TXCLK, | |
| 58 | MFP087_ETH_TXEN, | |
| 59 | MFP088_ETH_TXDQ3, | |
| 60 | MFP089_ETH_TXDQ2, | |
| 61 | MFP090_ETH_TXDQ1, | |
| 62 | MFP091_ETH_TXDQ0, | |
| 63 | MFP092_ETH_CRS, | |
| 64 | MFP093_ETH_COL, | |
| 65 | MFP094_ETH_RXCLK, | |
| 66 | MFP095_ETH_RXER, | |
| 67 | MFP096_ETH_RXDQ3, | |
| 68 | MFP097_ETH_RXDQ2, | |
| 69 | MFP098_ETH_RXDQ1, | |
| 70 | MFP099_ETH_RXDQ0, | |
| 71 | MFP100_ETH_MDC, | |
| 72 | MFP101_ETH_MDIO, | |
| 73 | MFP103_ETH_RXDV, | |
| 74 | ||
| daa4b2f7 AB |
75 | /* SSP2 */ |
| 76 | MFP107_SSP2_RXD, | |
| 77 | MFP108_SSP2_TXD, | |
| 78 | MFP110_SSP2_CS, | |
| 79 | MFP111_SSP2_CLK, | |
| 80 | ||
| 26749582 AB |
81 | MFP_EOC /*End of configuration*/ |
| 82 | }; | |
| 83 | /* configure MFP's */ | |
| 84 | mfp_config(mfp_cfg); | |
| 85 | return 0; | |
| 86 | } | |
| 87 | ||
| 88 | int board_init(void) | |
| 89 | { | |
| daa4b2f7 AB |
90 | struct armd1apb2_registers *apb2_regs = |
| 91 | (struct armd1apb2_registers *)ARMD1_APBC2_BASE; | |
| 92 | ||
| 26749582 AB |
93 | /* arch number of Board */ |
| 94 | gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD; | |
| 95 | /* adress of boot parameters */ | |
| 96 | gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100; | |
| 47e75d72 AB |
97 | /* Assert PHY_RST# */ |
| 98 | gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW); | |
| 99 | udelay(10); | |
| 100 | /* Deassert PHY_RST# */ | |
| 101 | gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH); | |
| daa4b2f7 AB |
102 | |
| 103 | /* Enable SSP2 clock */ | |
| 104 | writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst); | |
| 26749582 AB |
105 | return 0; |
| 106 | } | |
| aa0ecfeb AB |
107 | |
| 108 | #ifdef CONFIG_ARMADA100_FEC | |
| 109 | int board_eth_init(bd_t *bis) | |
| 110 | { | |
| 111 | struct armd1apmu_registers *apmu_regs = | |
| 112 | (struct armd1apmu_registers *)ARMD1_APMU_BASE; | |
| 113 | ||
| 114 | /* Enable clock of ethernet controller */ | |
| 115 | writel(FE_CLK_RST | FE_CLK_ENA, &apmu_regs->fecrc); | |
| 116 | ||
| 117 | return armada100_fec_register(ARMD1_FEC_BASE); | |
| 118 | } | |
| 47e75d72 AB |
119 | |
| 120 | #ifdef CONFIG_RESET_PHY_R | |
| 121 | /* Configure and initialize PHY chip 88E3015 */ | |
| 122 | void reset_phy(void) | |
| 123 | { | |
| 124 | u16 phy_adr; | |
| 125 | const char *name = "armd-fec0"; | |
| 126 | ||
| 127 | if (miiphy_set_current_dev(name)) | |
| 128 | return; | |
| 129 | ||
| 130 | /* command to read PHY dev address */ | |
| 131 | if (miiphy_read(name, 0xff, 0xff, &phy_adr)) { | |
| 132 | printf("Err..%s could not read PHY dev address\n", __func__); | |
| 133 | return; | |
| 134 | } | |
| 135 | ||
| 136 | /* Set Ethernet LED in TX blink mode */ | |
| 137 | miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00); | |
| 138 | miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL); | |
| 139 | ||
| 140 | /* reset the phy */ | |
| 141 | miiphy_reset(name, phy_adr); | |
| 142 | debug("88E3015 Initialized on %s\n", name); | |
| 143 | } | |
| 144 | #endif /* CONFIG_RESET_PHY_R */ | |
| aa0ecfeb | 145 | #endif /* CONFIG_ARMADA100_FEC */ |