[J-u-boot.git] / include / configs / KUP4K.h

/*
  * (C) Copyright 2000-2010
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 * Derived from ../tqm8xx/tqm8xx.c
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC855		1	/* This is a MPC855 CPU		*/
#define CONFIG_KUP4K		1	/* ...on a KUP4K module */

#define	CONFIG_SYS_TEXT_BASE	0x40000000

#define CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
#define CONFIG_BOOTDELAY	1	/* autoboot after 1 second	*/

#define CONFIG_BOARD_TYPES	1	/* support board types		*/

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS						\
"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;"				\
 "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0"		\
"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;"				\
 "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0"		\
"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0"	\
"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw;		\
 bootm 400000 \0"								\
"panic_boot=echo No Bootdevice !!! reset\0"					\
"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0"		\
"ramargs=setenv bootargs root=/dev/ram rw\0"					\
"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}"			\
 ":${netmask}:${hostname}:${netdev}:off\0"					\
"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug}	\
 hw=${hw} key1=${key1} panic=1 mem=${mem}\0"					\
"console=ttyCPM0,115200\0"							\
"netdev=eth0\0"									\
"contrast=20\0"									\
"silent=1\0"									\
"mtdparts=" MTDPARTS_DEFAULT "\0"						\
"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"		\
"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};"		\
 "cp.b 200000 40050000 14000\0"

#define CONFIG_BOOTCOMMAND  \
    "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"

#define CONFIG_PREBOOT	"setenv preboot; saveenv"

#define CONFIG_MISC_INIT_R	1
#define CONFIG_MISC_INIT_F	1

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE	/* don't allow baudrate change	*/

#define	CONFIG_WATCHDOG	1		/* watchdog enabled		*/

#define CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/*
 * enable I2C and select the hardware/software driver
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */

/*-----------------------------------------------------------------------
 * I2C Configuration
 */

#define CONFIG_SYS_I2C_PICIO_ADDR	0x21	/* PCF8574 IO Expander */
#define CONFIG_SYS_I2C_RTC_ADDR		0x51	/* PCF8563 RTC */

/* List of I2C addresses to be verified by POST */

#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_PICIO_ADDR,	\
					 CONFIG_SYS_I2C_RTC_ADDR,	\
					}

#define CONFIG_RTC_PCF8563		/* use Philips PCF8563 RTC	*/

#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII

/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_FAT
#define CONFIG_CMD_SNTP

#ifdef CONFIG_POST
    #define CONFIG_CMD_DIAG
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size	*/
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x000400000	/* memtest works on     */
#define CONFIG_SYS_MEMTEST_END		0x005C00000	/* 4 ... 92 MB in DRAM  */
#define CONFIG_SYS_ALT_MEMTEST 1
#define CONFIG_SYS_MEMTEST_SCRATCH	0x90000200	/* using latch as scratch register */

#define CONFIG_SYS_LOAD_ADDR		0x400000	/* default load address */

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 115200 }

#define CONFIG_SYS_CONSOLE_INFO_QUIET 1

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	19	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		0x40000 /*   Offset   of Environment Sector	*/
#define CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	0x10000

/*-----------------------------------------------------------------------
 * Dynamic MTD partition support
 */
#define MTDPARTS_DEFAULT	"mtdparts=40000000.flash:256k(u-boot),"	\
						"64k(env),"		\
						"128k(splash),"		\
						"512k(etc),"		\
						"64k(hw-info)"

/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x000F0000	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000100	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x4B26500D		/* 'K&P<CR>' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 */
#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF00
#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_EBDF01 |  \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */

/* KUP4K use both slots, SLOT_A as "primary". */
#define CONFIG_PCMCIA_SLOT_A 1

#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

#define PCMCIA_SOCKETS_NO 2
#define PCMCIA_MEM_WIN_NO 8
/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#define CONFIG_IDE_LED		1	/* LED	 for ide supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		2
#define CONFIG_SYS_IDE_MAXDEVICE	4

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_IDE1_OFFSET	(4 * CONFIG_SYS_PCMCIA_MEM_SIZE)

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */
#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV2  | OR_CSNT_SAM | \
				 OR_SCY_5_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP \
	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM \
	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM \
	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )


/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096	 Rows from SDRAM example configuration
 * 1000	 factor s -> ms
 *   32	 PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4	 Number of refresh cycles per period
 *   64	 Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#if   defined(CONFIG_80MHz)
#define CONFIG_SYS_MAMR_PTA		156
#elif defined(CONFIG_66MHz)
#define CONFIG_SYS_MAMR_PTA		129
#else		/*   50 MHz */
#define CONFIG_SYS_MAMR_PTA		 98
#endif	/*CONFIG_??MHz */

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR 0x400

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL 0x68802114
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL 0x68904114

/*
 * Chip Selects
 */
#define CONFIG_SYS_OR0
#define CONFIG_SYS_BR0

#define CONFIG_SYS_OR1_8COL 0xFF000A00
#define CONFIG_SYS_BR1_8COL 0x00000081
#define CONFIG_SYS_OR2_8COL 0xFE000A00
#define CONFIG_SYS_BR2_8COL 0x01000081
#define CONFIG_SYS_OR3_8COL 0xFC000A00
#define CONFIG_SYS_BR3_8COL 0x02000081

#define CONFIG_SYS_OR1_9COL 0xFE000A00
#define CONFIG_SYS_BR1_9COL 0x00000081
#define CONFIG_SYS_OR2_9COL 0xFE000A00
#define CONFIG_SYS_BR2_9COL 0x02000081
#define CONFIG_SYS_OR3_9COL 0xFE000A00
#define CONFIG_SYS_BR3_9COL 0x04000081

#define CONFIG_SYS_OR4 0xFFFF8926
#define CONFIG_SYS_BR4 0x90000401

#define CONFIG_SYS_OR5 0xFFC007F0  /* EPSON: 4 MB  17 WS or externel TA */
#define CONFIG_SYS_BR5 0x80080801  /* Start at 0x80080000 */

#define LATCH_ADDR 0x90000200

#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
#define CONFIG_AUTOBOOT_STOP_STR	"."
#define CONFIG_SILENT_CONSOLE		1
#define CONFIG_SYS_DEVICE_NULLDEV	1       /* enble null device		*/
#define CONFIG_VERSION_VARIABLE		1

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1

#endif	/* __CONFIG_H */
Commit	Line	Data
56f94be3	1	/*
e604e409	2	* (C) Copyright 2000-2010
56f94be3 WD	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
56f94be3 WD	7	*/
	8
	9	/*
	10	* board/config.h - configuration options, board specific
	11	* Derived from ../tqm8xx/tqm8xx.c
	12	*/
	13
	14	#ifndef __CONFIG_H
	15	#define __CONFIG_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
	21
	22	#define CONFIG_MPC855 1 /* This is a MPC855 CPU */
	23	#define CONFIG_KUP4K 1 /* ...on a KUP4K module */
	24
2ae18241 WD	25	#define CONFIG_SYS_TEXT_BASE 0x40000000
2ae18241 WD	26
0608e04d	27	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
56f94be3 WD	28	#undef CONFIG_8xx_CONS_SMC2
56f94be3 WD	29	#undef CONFIG_8xx_CONS_NONE
682011ff	30	#define CONFIG_BAUDRATE 115200 /* console baudrate */
682011ff	31	#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
56f94be3	32
56f94be3 WD	33	#define CONFIG_BOARD_TYPES 1 /* support board types */
56f94be3 WD	34
56f94be3 WD	35	#undef CONFIG_BOOTARGS
56f94be3 WD	36
0608e04d	37	#define CONFIG_EXTRA_ENV_SETTINGS \
e604e409	38	"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
2d941de9	39	"run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
e604e409	40	"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
2d941de9	41	"run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
e604e409 HS	42	"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
	43	"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
	44	bootm 400000 \0" \
0608e04d	45	"panic_boot=echo No Bootdevice !!! reset\0" \
e604e409	46	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
0608e04d	47	"ramargs=setenv bootargs root=/dev/ram rw\0" \
e604e409	48	"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
fe126d8b	49	":${netmask}:${hostname}:${netdev}:off\0" \
e604e409 HS	50	"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
	51	hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
	52	"console=ttyCPM0,115200\0" \
0608e04d	53	"netdev=eth0\0" \
e604e409	54	"contrast=20\0" \
0608e04d	55	"silent=1\0" \
e604e409	56	"mtdparts=" MTDPARTS_DEFAULT "\0" \
0608e04d	57	"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
e604e409	58	"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
02b11f8e	59	"cp.b 200000 40050000 14000\0"
682011ff WD	60
682011ff WD	61	#define CONFIG_BOOTCOMMAND \
e604e409	62	"run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
56f94be3	63
e604e409	64	#define CONFIG_PREBOOT "setenv preboot; saveenv"
56f94be3	65
0608e04d WD	66	#define CONFIG_MISC_INIT_R 1
0608e04d WD	67	#define CONFIG_MISC_INIT_F 1
56f94be3 WD	68
56f94be3 WD	69	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
e604e409	70	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
56f94be3	71
02b11f8e	72	#define CONFIG_WATCHDOG 1 /* watchdog enabled */
56f94be3	73
0608e04d	74	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
56f94be3 WD	75
	76	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	77
7be044e4 JL	78	/*
	79	* BOOTP options
	80	*/
	81	#define CONFIG_BOOTP_SUBNETMASK
	82	#define CONFIG_BOOTP_GATEWAY
	83	#define CONFIG_BOOTP_HOSTNAME
	84	#define CONFIG_BOOTP_BOOTPATH
	85	#define CONFIG_BOOTP_BOOTFILESIZE
	86
56f94be3 WD	87	#define CONFIG_MAC_PARTITION
	88	#define CONFIG_DOS_PARTITION
	89
02b11f8e WD	90	/*
	91	* enable I2C and select the hardware/software driver
	92	*/
ea818dbb HS	93	#define CONFIG_SYS_I2C
	94	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	95	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	96	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
02b11f8e	97
02b11f8e WD	98	/*
	99	* Software (bit-bang) I2C driver configuration
	100	*/
	101	#define PB_SCL 0x00000020 /* PB 26 */
	102	#define PB_SDA 0x00000010 /* PB 27 */
	103
	104	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	105	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	106	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	107	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	108	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
	109	else immr->im_cpm.cp_pbdat &= ~PB_SDA
	110	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
	111	else immr->im_cpm.cp_pbdat &= ~PB_SCL
	112	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
02b11f8e	113
02b11f8e WD	114	/*-----------------------------------------------------------------------
	115	* I2C Configuration
	116	*/
	117
e604e409 HS	118	#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
e604e409 HS	119	#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
0608e04d	120
02b11f8e WD	121	/* List of I2C addresses to be verified by POST */
02b11f8e WD	122
60aaaa07 PT	123	#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
	124	CONFIG_SYS_I2C_RTC_ADDR, \
	125	}
02b11f8e	126
02b11f8e WD	127	#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
02b11f8e WD	128
6d0f6bcf	129	#define CONFIG_SYS_DISCOVER_PHY
63ff004c	130	#define CONFIG_MII
02b11f8e	131
56f94be3 WD	132	/* Define to allow the user to overwrite serial and ethaddr */
56f94be3 WD	133	#define CONFIG_ENV_OVERWRITE
348f258f JL	134
	135	/*
	136	* Command line configuration.
	137	*/
	138	#include <config_cmd_default.h>
	139
	140	#define CONFIG_CMD_DATE
	141	#define CONFIG_CMD_DHCP
	142	#define CONFIG_CMD_I2C
	143	#define CONFIG_CMD_IDE
e604e409	144	#define CONFIG_CMD_MII
348f258f	145	#define CONFIG_CMD_NFS
e604e409	146	#define CONFIG_CMD_FAT
348f258f JL	147	#define CONFIG_CMD_SNTP
348f258f JL	148
af075ee9 JL	149	#ifdef CONFIG_POST
	150	#define CONFIG_CMD_DIAG
	151	#endif
56f94be3 WD	152
	153	/*
	154	* Miscellaneous configurable options
	155	*/
6d0f6bcf	156	#define CONFIG_SYS_LONGHELP /* undef to save memory */
348f258f	157	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	158	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
56f94be3	159	#else
e604e409	160	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
56f94be3	161	#endif
e604e409 HS	162	/* Print Buffer Size */
e604e409 HS	163	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
6d0f6bcf JCPV	164	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
6d0f6bcf JCPV	165	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
56f94be3	166
e604e409 HS	167	#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */
	168	#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */
	169	#define CONFIG_SYS_ALT_MEMTEST 1
	170	#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */
56f94be3	171
e604e409	172	#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
56f94be3	173
6d0f6bcf	174	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
56f94be3	175
6d0f6bcf	176	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
682011ff	177
56f94be3 WD	178	/*
	179	* Low Level Configuration Settings
	180	* (address mappings, register initial values, etc.)
	181	* You should know what you are doing if you make changes here.
	182	*/
	183	/*-----------------------------------------------------------------------
	184	* Internal Memory Mapped Register
	185	*/
6d0f6bcf	186	#define CONFIG_SYS_IMMR 0xFFF00000
56f94be3 WD	187
	188	/*-----------------------------------------------------------------------
	189	* Definitions for initial stack pointer and data area (in DPRAM)
	190	*/
6d0f6bcf	191	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	192	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	193	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	194	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
56f94be3 WD	195
	196	/*-----------------------------------------------------------------------
	197	* Start addresses for the final memory configuration
	198	* (Set up by the startup code)
6d0f6bcf	199	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
56f94be3	200	*/
6d0f6bcf JCPV	201	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	202	#define CONFIG_SYS_FLASH_BASE 0x40000000
	203	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	204	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	205	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
56f94be3 WD	206
	207	/*
	208	* For booting Linux, the board info and command line data
	209	* have to be in the first 8 MB of memory, since this is
	210	* the maximum mapped by the Linux kernel during initialization.
	211	*/
6d0f6bcf	212	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
56f94be3 WD	213
	214	/*-----------------------------------------------------------------------
	215	* FLASH organization
	216	*/
6d0f6bcf JCPV	217	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	218	#define CONFIG_SYS_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
56f94be3	219
6d0f6bcf JCPV	220	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	221	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
56f94be3	222
5a1aceb0	223	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	224	#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
	225	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
	226	#define CONFIG_ENV_SECT_SIZE 0x10000
56f94be3	227
e604e409 HS	228	/*-----------------------------------------------------------------------
	229	* Dynamic MTD partition support
	230	*/
	231	#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
2d941de9 WD	232	"64k(env)," \
	233	"128k(splash)," \
	234	"512k(etc)," \
	235	"64k(hw-info)"
e604e409	236
56f94be3 WD	237	/*-----------------------------------------------------------------------
	238	* Hardware Information Block
	239	*/
6d0f6bcf JCPV	240	#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
6d0f6bcf JCPV	241	#define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */
e604e409 HS	242	#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
e604e409 HS	243
56f94be3 WD	244	/*-----------------------------------------------------------------------
	245	* Cache Configuration
	246	*/
6d0f6bcf	247	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	248	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	249	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
56f94be3 WD	250	#endif
	251
	252	/*-----------------------------------------------------------------------
	253	* SYPCR - System Protection Control 11-9
	254	* SYPCR can only be written once after reset!
	255	*-----------------------------------------------------------------------
	256	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
56f94be3 WD	259
	260	/*-----------------------------------------------------------------------
	261	* SIUMCR - SIU Module Configuration 11-6
	262	*-----------------------------------------------------------------------
	263	* PCMCIA config., multi-function pin tri-state
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC00)
56f94be3 WD	266
	267	/*-----------------------------------------------------------------------
	268	* TBSCR - Time Base Status and Control 11-26
	269	*-----------------------------------------------------------------------
	270	* Clear Reference Interrupt Status, Timebase freezing enabled
	271	*/
6d0f6bcf	272	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
56f94be3 WD	273
	274	/*-----------------------------------------------------------------------
	275	* RTCSC - Real-Time Clock Status and Control Register 11-27
	276	*-----------------------------------------------------------------------
	277	*/
6d0f6bcf	278	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
56f94be3 WD	279
	280	/*-----------------------------------------------------------------------
	281	* PISCR - Periodic Interrupt Status and Control 11-31
	282	*-----------------------------------------------------------------------
	283	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	284	*/
6d0f6bcf	285	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
56f94be3 WD	286
	287	/*-----------------------------------------------------------------------
	288	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	289	*-----------------------------------------------------------------------
	290	* Reset PLL lock status sticky bit, timer expired status bit and timer
	291	* interrupt status bit
	292	*
	293	* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
	294	*/
6d0f6bcf	295	#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT \| PLPRCR_TEXPS \| PLPRCR_TMIST )
56f94be3 WD	296
	297	/*-----------------------------------------------------------------------
	298	* SCCR - System Clock and reset Control Register 15-27
	299	*-----------------------------------------------------------------------
	300	* Set clock output, timebase and RTC source and divider,
	301	* power management and some other internal clocks
	302	*/
	303	#define SCCR_MASK SCCR_EBDF00
6d0f6bcf	304	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_EBDF01 \| \
56f94be3 WD	305	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	306	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	307	SCCR_DFALCD00)
	308
	309	/*-----------------------------------------------------------------------
	310	* PCMCIA stuff
	311	*-----------------------------------------------------------------------
	312	*
	313	*/
	314
ea909b76	315	/* KUP4K use both slots, SLOT_A as "primary". */
0608e04d	316	#define CONFIG_PCMCIA_SLOT_A 1
56f94be3	317
6d0f6bcf JCPV	318	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	319	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	320	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	321	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	322	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	323	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	324	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	325	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
56f94be3	326
ea909b76 WD	327	#define PCMCIA_SOCKETS_NO 2
ea909b76 WD	328	#define PCMCIA_MEM_WIN_NO 8
56f94be3 WD	329	/*-----------------------------------------------------------------------
	330	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	331	*-----------------------------------------------------------------------
	332	*/
	333
8d1165e1	334	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
0608e04d	335	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
56f94be3	336
0608e04d WD	337	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
0608e04d WD	338	#define CONFIG_IDE_LED 1 /* LED for ide supported */
56f94be3 WD	339	#undef CONFIG_IDE_RESET /* reset for ide not supported */
56f94be3 WD	340
6d0f6bcf JCPV	341	#define CONFIG_SYS_IDE_MAXBUS 2
6d0f6bcf JCPV	342	#define CONFIG_SYS_IDE_MAXDEVICE 4
56f94be3	343
6d0f6bcf	344	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
56f94be3	345
6d0f6bcf	346	#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
ea909b76	347
6d0f6bcf	348	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
56f94be3 WD	349
56f94be3 WD	350	/* Offset for data I/O */
6d0f6bcf	351	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
56f94be3 WD	352
56f94be3 WD	353	/* Offset for normal register accesses */
6d0f6bcf	354	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
56f94be3 WD	355
56f94be3 WD	356	/* Offset for alternate registers */
6d0f6bcf	357	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
56f94be3	358
56f94be3 WD	359	/*-----------------------------------------------------------------------
	360	*
	361	*-----------------------------------------------------------------------
	362	*
	363	*/
6d0f6bcf	364	#define CONFIG_SYS_DER 0
56f94be3 WD	365
	366	/*
	367	* Init Memory Controller:
	368	*
	369	* BR0/1 and OR0/1 (FLASH)
	370	*/
	371	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	372
	373	/* used to re-map FLASH both when starting from SRAM or FLASH:
	374	* restrict access enough to keep SRAM working (if any)
	375	* but not too much to meddle with FLASH accesses
	376	*/
6d0f6bcf JCPV	377	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	378	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
56f94be3 WD	379
	380	/*
	381	* FLASH timing:
	382	*/
e604e409 HS	383	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 \| OR_CSNT_SAM \| \
e604e409 HS	384	OR_SCY_5_CLK \| OR_EHTR \| OR_BI)
56f94be3	385
e604e409 HS	386	#define CONFIG_SYS_OR0_REMAP \
	387	(CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	388	#define CONFIG_SYS_OR0_PRELIM \
	389	(CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	390	#define CONFIG_SYS_BR0_PRELIM \
	391	((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
56f94be3 WD	392
56f94be3 WD	393
56f94be3	394	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	395	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
56f94be3	396
56f94be3 WD	397	/*
	398	* Memory Periodic Timer Prescaler
	399	*
	400	* The Divider for PTA (refresh timer) configuration is based on an
	401	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	402	* the number of chip selects (NCS) and the actually needed refresh
	403	* rate is done by setting MPTPR.
	404	*
	405	* PTA is calculated from
	406	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	407	*
	408	* gclk CPU clock (not bus clock!)
	409	* Trefresh Refresh cycle * 4 (four word bursts used)
	410	*
0608e04d WD	411	* 4096 Rows from SDRAM example configuration
	412	* 1000 factor s -> ms
	413	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	414	* 4 Number of refresh cycles per period
	415	* 64 Refresh cycle in ms per number of rows
56f94be3 WD	416	* --------------------------------------------
	417	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	418	*
	419	* 50 MHz => 50.000.000 / Divider = 98
	420	* 66 Mhz => 66.000.000 / Divider = 129
	421	* 80 Mhz => 80.000.000 / Divider = 156
	422	*/
	423	#if defined(CONFIG_80MHz)
6d0f6bcf	424	#define CONFIG_SYS_MAMR_PTA 156
56f94be3	425	#elif defined(CONFIG_66MHz)
6d0f6bcf	426	#define CONFIG_SYS_MAMR_PTA 129
56f94be3	427	#else /* 50 MHz */
6d0f6bcf	428	#define CONFIG_SYS_MAMR_PTA 98
56f94be3 WD	429	#endif /CONFIG_??MHz /
	430
	431	/*
	432	* For 16 MBit, refresh rates could be 31.3 us
	433	* (= 64 ms / 2K = 125 / quad bursts).
	434	* For a simpler initialization, 15.6 us is used instead.
	435	*
6d0f6bcf JCPV	436	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	437	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
56f94be3	438	*/
6d0f6bcf	439	#define CONFIG_SYS_MPTPR 0x400
56f94be3 WD	440
	441	/*
	442	* MAMR settings for SDRAM
	443	*/
e604e409 HS	444
	445	/* 8 column SDRAM */
	446	#define CONFIG_SYS_MAMR_8COL 0x68802114
	447	/* 9 column SDRAM */
	448	#define CONFIG_SYS_MAMR_9COL 0x68904114
	449
	450	/*
	451	* Chip Selects
	452	*/
	453	#define CONFIG_SYS_OR0
	454	#define CONFIG_SYS_BR0
	455
	456	#define CONFIG_SYS_OR1_8COL 0xFF000A00
	457	#define CONFIG_SYS_BR1_8COL 0x00000081
	458	#define CONFIG_SYS_OR2_8COL 0xFE000A00
	459	#define CONFIG_SYS_BR2_8COL 0x01000081
	460	#define CONFIG_SYS_OR3_8COL 0xFC000A00
	461	#define CONFIG_SYS_BR3_8COL 0x02000081
	462
	463	#define CONFIG_SYS_OR1_9COL 0xFE000A00
	464	#define CONFIG_SYS_BR1_9COL 0x00000081
	465	#define CONFIG_SYS_OR2_9COL 0xFE000A00
	466	#define CONFIG_SYS_BR2_9COL 0x02000081
	467	#define CONFIG_SYS_OR3_9COL 0xFE000A00
	468	#define CONFIG_SYS_BR3_9COL 0x04000081
	469
	470	#define CONFIG_SYS_OR4 0xFFFF8926
	471	#define CONFIG_SYS_BR4 0x90000401
	472
	473	#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */
	474	#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */
	475
	476	#define LATCH_ADDR 0x90000200
56f94be3	477
56f94be3	478	#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
e604e409 HS	479	#define CONFIG_AUTOBOOT_STOP_STR "."
e604e409 HS	480	#define CONFIG_SILENT_CONSOLE 1
2d941de9	481	#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */
e604e409	482	#define CONFIG_VERSION_VARIABLE 1
56f94be3	483
8011ec63 HS	484	/* pass open firmware flat tree */
	485	#define CONFIG_OF_LIBFDT 1
	486	#define CONFIG_OF_BOARD_SETUP 1
	487
56f94be3	488	#endif /* __CONFIG_H */