Commit | Line | Data |
---|---|---|
695693b2 | 1 | CONFIG_ARM=y |
a2ac2b96 | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
abf8d963 | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
695693b2 | 4 | CONFIG_ARCH_ROCKCHIP=y |
695693b2 | 5 | CONFIG_NR_DRAM_BANKS=2 |
54c5c2b8 | 6 | CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" |
695693b2 | 7 | CONFIG_ROCKCHIP_RK3568=y |
daec31e5 | 8 | CONFIG_SPL_SERIAL=y |
695693b2 JC |
9 | CONFIG_DEBUG_UART_BASE=0xFE660000 |
10 | CONFIG_DEBUG_UART_CLOCK=24000000 | |
49c8ef0e | 11 | CONFIG_SYS_LOAD_ADDR=0xc00800 |
d46e86d2 | 12 | CONFIG_DEBUG_UART=y |
daec31e5 NC |
13 | CONFIG_FIT=y |
14 | CONFIG_FIT_VERBOSE=y | |
703c170b | 15 | CONFIG_SPL_FIT_SIGNATURE=y |
daec31e5 | 16 | CONFIG_SPL_LOAD_FIT=y |
e3765084 | 17 | CONFIG_LEGACY_IMAGE_FORMAT=y |
695693b2 JC |
18 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" |
19 | # CONFIG_DISPLAY_CPUINFO is not set | |
20 | CONFIG_DISPLAY_BOARDINFO_LATE=y | |
703c170b | 21 | CONFIG_SPL_MAX_SIZE=0x40000 |
ca8a329a | 22 | CONFIG_SPL_PAD_TO=0x7f8000 |
daec31e5 | 23 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
daec31e5 | 24 | CONFIG_SPL_ATF=y |
703c170b | 25 | CONFIG_CMD_GPIO=y |
695693b2 | 26 | CONFIG_CMD_GPT=y |
703c170b | 27 | CONFIG_CMD_I2C=y |
695693b2 JC |
28 | CONFIG_CMD_MMC=y |
29 | # CONFIG_CMD_SETEXPR is not set | |
703c170b JK |
30 | CONFIG_CMD_PMIC=y |
31 | CONFIG_CMD_REGULATOR=y | |
daec31e5 NC |
32 | # CONFIG_SPL_DOS_PARTITION is not set |
33 | CONFIG_SPL_OF_CONTROL=y | |
34 | CONFIG_OF_LIVE=y | |
703c170b | 35 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
25f56459 | 36 | CONFIG_SPL_DM_SEQ_ALIAS=y |
daec31e5 NC |
37 | CONFIG_SPL_REGMAP=y |
38 | CONFIG_SPL_SYSCON=y | |
39 | CONFIG_SPL_CLK=y | |
695693b2 JC |
40 | CONFIG_ROCKCHIP_GPIO=y |
41 | CONFIG_SYS_I2C_ROCKCHIP=y | |
42 | CONFIG_MISC=y | |
d5bfef2f | 43 | CONFIG_SUPPORT_EMMC_RPMB=y |
695693b2 JC |
44 | CONFIG_MMC_DW=y |
45 | CONFIG_MMC_DW_ROCKCHIP=y | |
46 | CONFIG_MMC_SDHCI=y | |
47 | CONFIG_MMC_SDHCI_SDMA=y | |
48 | CONFIG_MMC_SDHCI_ROCKCHIP=y | |
25f56459 JK |
49 | CONFIG_PHY_REALTEK=y |
50 | CONFIG_DWC_ETH_QOS=y | |
51 | CONFIG_DWC_ETH_QOS_ROCKCHIP=y | |
703c170b JK |
52 | CONFIG_DM_PMIC=y |
53 | CONFIG_PMIC_RK8XX=y | |
54 | CONFIG_REGULATOR_RK8XX=y | |
695693b2 | 55 | CONFIG_PWM_ROCKCHIP=y |
daec31e5 | 56 | CONFIG_SPL_RAM=y |
695693b2 JC |
57 | CONFIG_BAUDRATE=1500000 |
58 | CONFIG_DEBUG_UART_SHIFT=2 | |
9591b635 | 59 | CONFIG_SYS_NS16550_MEM32=y |
695693b2 JC |
60 | CONFIG_SYSRESET=y |
61 | CONFIG_ERRNO_STR=y |