Commit | Line | Data |
---|---|---|
149e80f7 PF |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Copyright 2022 NXP | |
4 | */ | |
5 | ||
6 | #include <phy_interface.h> | |
7 | #include <linux/bitops.h> | |
8 | ||
9 | /* Core registers */ | |
10 | ||
11 | #define EQOS_MAC_REGS_BASE 0x000 | |
12 | struct eqos_mac_regs { | |
13 | u32 configuration; /* 0x000 */ | |
14 | u32 unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ | |
15 | u32 q0_tx_flow_ctrl; /* 0x070 */ | |
16 | u32 unused_070[(0x090 - 0x074) / 4]; /* 0x074 */ | |
17 | u32 rx_flow_ctrl; /* 0x090 */ | |
18 | u32 unused_094; /* 0x094 */ | |
19 | u32 txq_prty_map0; /* 0x098 */ | |
20 | u32 unused_09c; /* 0x09c */ | |
21 | u32 rxq_ctrl0; /* 0x0a0 */ | |
22 | u32 unused_0a4; /* 0x0a4 */ | |
23 | u32 rxq_ctrl2; /* 0x0a8 */ | |
24 | u32 unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */ | |
25 | u32 us_tic_counter; /* 0x0dc */ | |
26 | u32 unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */ | |
27 | u32 hw_feature0; /* 0x11c */ | |
28 | u32 hw_feature1; /* 0x120 */ | |
29 | u32 hw_feature2; /* 0x124 */ | |
30 | u32 unused_128[(0x200 - 0x128) / 4]; /* 0x128 */ | |
31 | u32 mdio_address; /* 0x200 */ | |
32 | u32 mdio_data; /* 0x204 */ | |
33 | u32 unused_208[(0x300 - 0x208) / 4]; /* 0x208 */ | |
34 | u32 address0_high; /* 0x300 */ | |
35 | u32 address0_low; /* 0x304 */ | |
36 | }; | |
37 | ||
38 | #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23) | |
39 | #define EQOS_MAC_CONFIGURATION_CST BIT(21) | |
40 | #define EQOS_MAC_CONFIGURATION_ACS BIT(20) | |
41 | #define EQOS_MAC_CONFIGURATION_WD BIT(19) | |
42 | #define EQOS_MAC_CONFIGURATION_JD BIT(17) | |
43 | #define EQOS_MAC_CONFIGURATION_JE BIT(16) | |
44 | #define EQOS_MAC_CONFIGURATION_PS BIT(15) | |
45 | #define EQOS_MAC_CONFIGURATION_FES BIT(14) | |
46 | #define EQOS_MAC_CONFIGURATION_DM BIT(13) | |
47 | #define EQOS_MAC_CONFIGURATION_LM BIT(12) | |
48 | #define EQOS_MAC_CONFIGURATION_TE BIT(1) | |
49 | #define EQOS_MAC_CONFIGURATION_RE BIT(0) | |
50 | ||
51 | #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16 | |
52 | #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff | |
53 | #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1) | |
54 | ||
55 | #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0) | |
56 | ||
57 | #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0 | |
58 | #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff | |
59 | ||
60 | #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0 | |
61 | #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3 | |
62 | #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0 | |
63 | #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2 | |
64 | #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1 | |
65 | ||
66 | #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0 | |
67 | #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff | |
68 | ||
69 | #define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8 | |
70 | #define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2 | |
71 | #define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1 | |
72 | #define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0 | |
73 | ||
74 | #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6 | |
75 | #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f | |
76 | #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0 | |
77 | #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f | |
78 | ||
79 | #define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28 | |
80 | #define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3 | |
81 | ||
151b8857 PO |
82 | #define EQOS_MAC_MDIO_ADDRESS_PA_MASK GENMASK(25, 21) |
83 | #define EQOS_MAC_MDIO_ADDRESS_RDA_MASK GENMASK(20, 16) | |
84 | #define EQOS_MAC_MDIO_ADDRESS_CR_MASK GENMASK(11, 8) | |
8e76ff61 | 85 | #define EQOS_MAC_MDIO_ADDRESS_CR_100_150 1 |
149e80f7 PF |
86 | #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2 |
87 | #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5 | |
88 | #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4) | |
151b8857 | 89 | #define EQOS_MAC_MDIO_ADDRESS_GOC_MASK GENMASK(3, 2) |
149e80f7 PF |
90 | #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3 |
91 | #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1 | |
92 | #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1) | |
93 | #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0) | |
94 | ||
151b8857 | 95 | #define EQOS_MAC_MDIO_DATA_RA_MASK GENMASK(31, 16) |
149e80f7 PF |
96 | #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff |
97 | ||
98 | #define EQOS_MTL_REGS_BASE 0xd00 | |
99 | struct eqos_mtl_regs { | |
100 | u32 txq0_operation_mode; /* 0xd00 */ | |
101 | u32 unused_d04; /* 0xd04 */ | |
102 | u32 txq0_debug; /* 0xd08 */ | |
103 | u32 unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */ | |
104 | u32 txq0_quantum_weight; /* 0xd18 */ | |
105 | u32 unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */ | |
106 | u32 rxq0_operation_mode; /* 0xd30 */ | |
107 | u32 unused_d34; /* 0xd34 */ | |
108 | u32 rxq0_debug; /* 0xd38 */ | |
109 | }; | |
110 | ||
111 | #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16 | |
112 | #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff | |
113 | #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2 | |
114 | #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3 | |
115 | #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2 | |
116 | #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1) | |
117 | #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0) | |
118 | ||
119 | #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4) | |
120 | #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1 | |
121 | #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3 | |
122 | ||
123 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20 | |
124 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff | |
125 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14 | |
126 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f | |
127 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8 | |
128 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f | |
129 | #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7) | |
130 | #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5) | |
131 | ||
132 | #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16 | |
133 | #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff | |
134 | #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4 | |
135 | #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3 | |
136 | ||
137 | #define EQOS_DMA_REGS_BASE 0x1000 | |
138 | struct eqos_dma_regs { | |
139 | u32 mode; /* 0x1000 */ | |
140 | u32 sysbus_mode; /* 0x1004 */ | |
141 | u32 unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */ | |
142 | u32 ch0_control; /* 0x1100 */ | |
143 | u32 ch0_tx_control; /* 0x1104 */ | |
144 | u32 ch0_rx_control; /* 0x1108 */ | |
145 | u32 unused_110c; /* 0x110c */ | |
146 | u32 ch0_txdesc_list_haddress; /* 0x1110 */ | |
147 | u32 ch0_txdesc_list_address; /* 0x1114 */ | |
148 | u32 ch0_rxdesc_list_haddress; /* 0x1118 */ | |
149 | u32 ch0_rxdesc_list_address; /* 0x111c */ | |
150 | u32 ch0_txdesc_tail_pointer; /* 0x1120 */ | |
151 | u32 unused_1124; /* 0x1124 */ | |
152 | u32 ch0_rxdesc_tail_pointer; /* 0x1128 */ | |
153 | u32 ch0_txdesc_ring_length; /* 0x112c */ | |
154 | u32 ch0_rxdesc_ring_length; /* 0x1130 */ | |
155 | }; | |
156 | ||
157 | #define EQOS_DMA_MODE_SWR BIT(0) | |
158 | ||
159 | #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16 | |
160 | #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf | |
161 | #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11) | |
162 | #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3) | |
163 | #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2) | |
164 | #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1) | |
165 | ||
166 | #define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18 | |
e9d3fc7e | 167 | #define EQOS_DMA_CH0_CONTROL_DSL_MASK 0x7 |
149e80f7 PF |
168 | #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16) |
169 | ||
170 | #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16 | |
171 | #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f | |
172 | #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4) | |
173 | #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0) | |
174 | ||
175 | #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16 | |
176 | #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f | |
177 | #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1 | |
178 | #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff | |
179 | #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0) | |
180 | ||
181 | /* These registers are Tegra186-specific */ | |
182 | #define EQOS_TEGRA186_REGS_BASE 0x8800 | |
183 | struct eqos_tegra186_regs { | |
184 | u32 sdmemcomppadctrl; /* 0x8800 */ | |
185 | u32 auto_cal_config; /* 0x8804 */ | |
186 | u32 unused_8808; /* 0x8808 */ | |
187 | u32 auto_cal_status; /* 0x880c */ | |
188 | }; | |
189 | ||
190 | #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31) | |
191 | ||
192 | #define EQOS_AUTO_CAL_CONFIG_START BIT(31) | |
193 | #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29) | |
194 | ||
195 | #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31) | |
196 | ||
197 | /* Descriptors */ | |
198 | #define EQOS_DESCRIPTORS_TX 4 | |
199 | #define EQOS_DESCRIPTORS_RX 4 | |
200 | #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX) | |
201 | #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN | |
202 | #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN) | |
203 | #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE) | |
204 | ||
205 | struct eqos_desc { | |
206 | u32 des0; | |
207 | u32 des1; | |
208 | u32 des2; | |
209 | u32 des3; | |
210 | }; | |
211 | ||
212 | #define EQOS_DESC3_OWN BIT(31) | |
213 | #define EQOS_DESC3_FD BIT(29) | |
214 | #define EQOS_DESC3_LD BIT(28) | |
215 | #define EQOS_DESC3_BUF1V BIT(24) | |
216 | ||
217 | #define EQOS_AXI_WIDTH_32 4 | |
218 | #define EQOS_AXI_WIDTH_64 8 | |
219 | #define EQOS_AXI_WIDTH_128 16 | |
220 | ||
221 | struct eqos_config { | |
222 | bool reg_access_always_ok; | |
223 | int mdio_wait; | |
224 | int swr_wait; | |
225 | int config_mac; | |
226 | int config_mac_mdio; | |
227 | unsigned int axi_bus_width; | |
228 | phy_interface_t (*interface)(const struct udevice *dev); | |
229 | struct eqos_ops *ops; | |
230 | }; | |
231 | ||
232 | struct eqos_ops { | |
233 | void (*eqos_inval_desc)(void *desc); | |
234 | void (*eqos_flush_desc)(void *desc); | |
235 | void (*eqos_inval_buffer)(void *buf, size_t size); | |
236 | void (*eqos_flush_buffer)(void *buf, size_t size); | |
237 | int (*eqos_probe_resources)(struct udevice *dev); | |
238 | int (*eqos_remove_resources)(struct udevice *dev); | |
239 | int (*eqos_stop_resets)(struct udevice *dev); | |
240 | int (*eqos_start_resets)(struct udevice *dev); | |
241 | int (*eqos_stop_clks)(struct udevice *dev); | |
242 | int (*eqos_start_clks)(struct udevice *dev); | |
243 | int (*eqos_calibrate_pads)(struct udevice *dev); | |
244 | int (*eqos_disable_calibration)(struct udevice *dev); | |
245 | int (*eqos_set_tx_clk_speed)(struct udevice *dev); | |
a6242514 | 246 | int (*eqos_get_enetaddr)(struct udevice *dev); |
149e80f7 PF |
247 | ulong (*eqos_get_tick_clk_rate)(struct udevice *dev); |
248 | }; | |
249 | ||
250 | struct eqos_priv { | |
251 | struct udevice *dev; | |
252 | const struct eqos_config *config; | |
253 | fdt_addr_t regs; | |
254 | struct eqos_mac_regs *mac_regs; | |
255 | struct eqos_mtl_regs *mtl_regs; | |
256 | struct eqos_dma_regs *dma_regs; | |
257 | struct eqos_tegra186_regs *tegra186_regs; | |
d382025d | 258 | void *eqos_qcom_rgmii_regs; |
149e80f7 PF |
259 | struct reset_ctl reset_ctl; |
260 | struct gpio_desc phy_reset_gpio; | |
261 | struct clk clk_master_bus; | |
262 | struct clk clk_rx; | |
263 | struct clk clk_ptp_ref; | |
264 | struct clk clk_tx; | |
265 | struct clk clk_ck; | |
266 | struct clk clk_slave_bus; | |
267 | struct mii_dev *mii; | |
268 | struct phy_device *phy; | |
a6acf955 | 269 | ofnode phy_of_node; |
149e80f7 | 270 | u32 max_speed; |
f94d008a MV |
271 | void *tx_descs; |
272 | void *rx_descs; | |
149e80f7 PF |
273 | int tx_desc_idx, rx_desc_idx; |
274 | unsigned int desc_size; | |
e9d3fc7e | 275 | unsigned int desc_per_cacheline; |
149e80f7 PF |
276 | void *tx_dma_buf; |
277 | void *rx_dma_buf; | |
149e80f7 PF |
278 | bool started; |
279 | bool reg_access_ok; | |
280 | bool clk_ck_enabled; | |
a962b7cf | 281 | unsigned int tx_fifo_sz, rx_fifo_sz; |
d382025d | 282 | u32 reset_delays[3]; |
149e80f7 PF |
283 | }; |
284 | ||
285 | void eqos_inval_desc_generic(void *desc); | |
286 | void eqos_flush_desc_generic(void *desc); | |
287 | void eqos_inval_buffer_generic(void *buf, size_t size); | |
288 | void eqos_flush_buffer_generic(void *buf, size_t size); | |
289 | int eqos_null_ops(struct udevice *dev); | |
5fc783b5 PF |
290 | |
291 | extern struct eqos_config eqos_imx_config; | |
8e76ff61 | 292 | extern struct eqos_config eqos_rockchip_config; |
d382025d | 293 | extern struct eqos_config eqos_qcom_config; |
882b2287 | 294 | extern struct eqos_config eqos_stm32mp13_config; |
85d1de9a | 295 | extern struct eqos_config eqos_stm32mp15_config; |
736733b4 | 296 | extern struct eqos_config eqos_jh7110_config; |