[J-u-boot.git] / include / configs / SIMPC8313.h

/*
 * Copyright (C) Sheldon Instruments, Inc. 2008
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * simpc8313 board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_NAND_U_BOOT

#define CONFIG_E300			1
#define CONFIG_MPC83xx			1
#define CONFIG_MPC831x			1
#define CONFIG_MPC8313			1

#define CONFIG_PCI
#define CONFIG_FSL_ELBC			1

#define CONFIG_MISC_INIT_R

/*
 * On-board devices
 *
 * TSEC1 is Marvell PHY 88E1118
 */

#define CONFIG_SYS_33MHZ

#define CONFIG_83XX_CLKIN		33333333	/* in Hz */

#define CONFIG_SYS_CLK_FREQ		CONFIG_83XX_CLKIN

#define CONFIG_SYS_IMMR			0xE0000000

#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DEFAULT_IMMR		CONFIG_SYS_IMMR
#endif

#define CONFIG_SYS_MEMTEST_START	0x00001000
#define CONFIG_SYS_MEMTEST_END		0x07f00000

#define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */

/*
 * Device configurations
 */
#define CONFIG_TSEC1

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED		(512 << 20)

#define CONFIG_SYS_DDRCDR		( DDRCDR_EN \
					| DDRCDR_PZ_NOMZ \
					| DDRCDR_NZ_NOMZ \
					| DDRCDR_M_ODR )
					/* 0x73000002 TODO ODR & DRN ? */

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_NO_FLASH

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END		0x1000		/* End of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */

/*
 * Local Bus LCRR and LBCR regs
 */
#define CONFIG_SYS_LCRR_DBYP	LCRR_DBYP
#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_1
#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR	(0x00040000 /* TODO */ \
				| (0xFF << LBCR_BMT_SHIFT) \
				| 0xF )	/* 0x0004ff0f */

#define CONFIG_SYS_LBC_MRTPR	0x20000000	/* LB refresh timer prescal, 266MHz/32 */

/* drivers/mtd/nand/nand.c */
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE		0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE		0xE2800000
#endif
#define CONFIG_SYS_FPGA_BASE		0xFF000000

#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS			1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_CMD_NAND 		1
#define CONFIG_NAND_FSL_ELBC		1

#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST	0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START	0x00100100
#define CONFIG_SYS_NAND_U_BOOT_RELOC	0x00010000
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)

#define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
					| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
					| BR_PS_8		/* Port Size = 8 bit */ \
					| BR_MS_FCM		/* MSEL = FCM */ \
					| BR_V )		/* valid */

#ifdef CONFIG_NAND_SP
#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFF8000	/* length 32K */ \
					| OR_FCM_CSCT \
					| OR_FCM_CST \
					| OR_FCM_CHT \
					| OR_FCM_SCY_1 \
					| OR_FCM_TRLX \
					| OR_FCM_EHTR )
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000000E	/* 32KB */
#define CONFIG_SYS_NAND_PAGE_SIZE	(512)		/* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 << 10)	/* NAND chip block size */
#define NAND_CACHE_PAGES		32
#elif defined(CONFIG_NAND_LP)
#define CONFIG_SYS_NAND_OR_PRELIM	( 0xFFFC0000	/* length 256K */ \
					| OR_FCM_PGS \
					| OR_FCM_CSCT \
					| OR_FCM_CST \
					| OR_FCM_CHT \
					| OR_FCM_SCY_1 \
					| OR_FCM_TRLX \
					| OR_FCM_EHTR )
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000011	/* 256KB */
#define CONFIG_SYS_NAND_PAGE_SIZE	(2048)		/* NAND chip page size */
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 << 10)	/* NAND chip block size */
#define NAND_CACHE_PAGES		64
#else
#error Page size of NAND not defined.
#endif /* CONFIG_NAND_SP */

#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SYS_NAND_BLOCK_SIZE

#define CONFIG_SYS_BR0_PRELIM		CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM		CONFIG_SYS_NAND_OR_PRELIM

#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_NAND_BASE

#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM

#define CONFIG_SYS_BR1_PRELIM		( CONFIG_SYS_FPGA_BASE \
					| BR_PS_16 \
					| BR_MS_UPMA \
					| BR_V )
#define CONFIG_SYS_OR1_PRELIM		( OR_AM_2MB \
					| OR_UPM_BCTLD)

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_2MB)

/*
 * JFFS2 configuration
 */
#define CONFIG_JFFS2_NAND
#define CONFIG_JFFS2_DEV	"nand0"

/* mtdparts command line support */
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define MTDIDS_DEFAULT		"nand0=nand0"
#define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#ifdef CONFIG_NAND_SPL
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1		(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2		(CONFIG_SYS_IMMR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

/* I2C */
#define CONFIG_HARD_I2C			/* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES		{{0,0x69}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE2000000
#define CONFIG_SYS_PCI1_IO_SIZE		0x00100000	/* 1M */

#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1057	/* Motorola */

/*
 * TSEC
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */

#define CONFIG_NET_MULTI
#define CONFIG_GMII			/* MII PHY management */

#ifdef CONFIG_TSEC1
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC1_NAME		"TSEC0"
#define CONFIG_SYS_TSEC1_OFFSET		0x24000
#define TSEC1_PHY_ADDR			0x0
#define TSEC1_FLAGS			TSEC_GIGABIT
#define TSEC1_PHYIDX			0
#endif

#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC2_NAME		"TSEC1"
#define CONFIG_SYS_TSEC2_OFFSET		0x25000
#define TSEC2_PHY_ADDR			4
#define TSEC2_FLAGS			TSEC_GIGABIT
#define TSEC2_PHYIDX			0
#endif


/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC1"

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C_RTC_ADDR		0x68

/*
 * Environment
 */
#if defined(CONFIG_NAND_U_BOOT)
	#define CONFIG_ENV_IS_IN_NAND		1
	#define CONFIG_ENV_OFFSET		(768 * 1024)
	#define CONFIG_ENV_SECT_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
	#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
	#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
	#define CONFIG_ENV_RANGE		(CONFIG_ENV_SECT_SIZE * 4)
	#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
#elif !defined(CONFIG_SYS_RAMBOOT)
	#define CONFIG_ENV_IS_IN_FLASH		1
	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE		0x10000	/* 64K(one sector) for env */
	#define CONFIG_ENV_SIZE			0x2000

/* Address and size of Redundant Environment Sector */
#else
	#define CONFIG_ENV_IS_NOWHERE		1	/* Store ENV in memory only */
	#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE			0x2000
#endif

#define CONFIG_LOADS_ECHO			1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH

#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_JFFS2

#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
	#undef CONFIG_CMD_SAVEENV
	#undef CONFIG_CMD_LOADS
#endif

#define CONFIG_CMDLINE_EDITING		1
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP				/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR		0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT		"=> "		/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size */

#define CONFIG_SYS_PBSIZE		( CONFIG_SYS_CBSIZE		\
					+ sizeof(CONFIG_SYS_PROMPT)	\
					+ 16 )	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)	/* Initial Memory map for Linux*/

#define CONFIG_SYS_RCWH_PCIHOST		0x80000000	/* PCIHOST */

#define CONFIG_SYS_HRCW_LOW		( HRCWL_LCL_BUS_TO_SCB_CLK_1X1	\
					| 0x20000000 /* reserved */	\
					| HRCWL_DDR_TO_SCB_CLK_2X1	\
					| HRCWL_CSB_TO_CLKIN_4X1	\
					| HRCWL_CORE_TO_CSB_2_5X1 )

#define CONFIG_SYS_NS16550_CLK		(CONFIG_83XX_CLKIN * 4)

#define CONFIG_SYS_HRCW_HIGH_BASE	( HRCWH_PCI_HOST		\
					| HRCWH_PCI1_ARBITER_ENABLE	\
					| HRCWH_CORE_ENABLE		\
					| HRCWH_BOOTSEQ_DISABLE		\
					| HRCWH_SW_WATCHDOG_DISABLE	\
					| HRCWH_TSEC1M_IN_RGMII		\
					| HRCWH_TSEC2M_IN_RGMII		\
					| HRCWH_BIG_ENDIAN		\
					| HRCWH_LALE_NORMAL )

#ifdef CONFIG_NAND_LP
#define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
				| HRCWH_FROM_0XFFF00100			\
				| HRCWH_ROM_LOC_NAND_LP_8BIT		\
				| HRCWH_RL_EXT_NAND)
#else
#define CONFIG_SYS_HRCW_HIGH	( CONFIG_SYS_HRCW_HIGH_BASE		\
				| HRCWH_FROM_0XFFF00100			\
				| HRCWH_ROM_LOC_NAND_SP_8BIT		\
				| HRCWH_RL_EXT_NAND )
#endif

/* System IO Config */
#define CONFIG_SYS_SICRH	( SICRH_ETSEC2_B	\
				| SICRH_ETSEC2_C	\
				| SICRH_ETSEC2_D	\
				| SICRH_ETSEC2_E	\
				| SICRH_ETSEC2_F	\
				| SICRH_ETSEC2_G	\
				| SICRH_TSOBI1		\
				| SICRH_TSOBI2 )
#define CONFIG_SYS_SICRL	( SICRL_LBC		\
				| SICRL_USBDR_10	\
				| SICRL_ETSEC2_A )

#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )

#define CONFIG_SYS_HID2		HID2_HBE

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR @ 0x00000000 */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT1L	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10)
#define CONFIG_SYS_IBAT1U	((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP)

/* PCI @ 0x80000000 */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* PCI2 not supported on 8313 */
#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)

/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)

#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02	/* Software reboot */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_NETDEV		eth1

#define CONFIG_HOSTNAME		simpc8313
#define CONFIG_ROOTPATH		/tftpboot/
#define CONFIG_BOOTFILE		/tftpboot/uImage
#define CONFIG_UBOOTPATH	u-boot-nand.bin	/* U-Boot image on TFTP server */
#define CONFIG_FDTFILE		simpc8313.dtb

#define CONFIG_LOADADDR		500000	/* default location for tftp and bootm */
#define CONFIG_BOOTDELAY	5	/* 5 second delay */
#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTCOMMAND	"nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"

#define XMK_STR(x)	#x
#define MK_STR(x)	XMK_STR(x)

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
	"ethprime=TSEC1\0"						\
	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
		"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
		"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
	"fdtaddr=ae0000\0"						\
	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	 \
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"	\
	"load_uboot=tftp 100000 u-boot-nand.bin\0"			\
	"burn_uboot=nand erase u-boot 80000; "				\
		"nand write 100000 u-boot $filesize\0"			\
	"update_uboot=run load_uboot;run burn_uboot\0"			\
	"mtdids=nand0=nand0\0"						\
	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0"	\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"	\
	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw "		\
		"console=ttyS0,115200\0"				\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#undef MK_STR
#undef XMK_STR

#endif	/* __CONFIG_H */
Commit	Line	Data
5bb907a4 RM	1	/*
	2	* Copyright (C) Sheldon Instruments, Inc. 2008
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22	/*
	23	* simpc8313 board configuration file
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	*/
	32	#define CONFIG_NAND_U_BOOT
	33
	34	#define CONFIG_E300 1
0f898604	35	#define CONFIG_MPC83xx 1
2c7920af	36	#define CONFIG_MPC831x 1
5bb907a4 RM	37	#define CONFIG_MPC8313 1
	38
	39	#define CONFIG_PCI
0914f483	40	#define CONFIG_FSL_ELBC 1
5bb907a4 RM	41
	42	#define CONFIG_MISC_INIT_R
	43
	44	/*
	45	* On-board devices
	46	*
	47	* TSEC1 is Marvell PHY 88E1118
	48	*/
	49
	50	#define CONFIG_SYS_33MHZ
	51
	52	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	53
	54	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	55
	56	#define CONFIG_SYS_IMMR 0xE0000000
	57
	58	#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	59	#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
	60	#endif
	61
	62	#define CONFIG_SYS_MEMTEST_START 0x00001000
	63	#define CONFIG_SYS_MEMTEST_END 0x07f00000
	64
	65	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
	66	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
	67
	68	/*
	69	* Device configurations
	70	*/
	71	#define CONFIG_TSEC1
	72
	73	/*
	74	* DDR Setup
	75	*/
	76	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
	77	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	78	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	79
	80	#define CONFIG_VERY_BIG_RAM
	81	#define CONFIG_MAX_MEM_MAPPED (512 << 20)
	82
	83	#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
	84	\| DDRCDR_PZ_NOMZ \
	85	\| DDRCDR_NZ_NOMZ \
	86	\| DDRCDR_M_ODR )
	87	/* 0x73000002 TODO ODR & DRN ? */
	88
	89	/*
	90	* FLASH on the Local Bus
	91	*/
	92	#define CONFIG_SYS_NO_FLASH
	93
	94	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
	95
	96	#if !defined(CONFIG_NAND_SPL)
	97	#define CONFIG_SYS_RAMBOOT
	98	#endif
	99
	100	#define CONFIG_SYS_INIT_RAM_LOCK 1
	101	#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
	102	#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
	103
	104	#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
105	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
106	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
107
108	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
109	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
110	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
111
112	/*
113	* Local Bus LCRR and LBCR regs
114	*/
c7190f02 KP	115	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
	116	#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
	117	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
5bb907a4 RM	118	#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
	119	\| (0xFF << LBCR_BMT_SHIFT) \
	120	\| 0xF ) /* 0x0004ff0f */
	121
	122	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
	123
	124	/* drivers/mtd/nand/nand.c */
	125	#ifdef CONFIG_NAND_SPL
	126	#define CONFIG_SYS_NAND_BASE 0xFFF00000
	127	#else
	128	#define CONFIG_SYS_NAND_BASE 0xE2800000
	129	#endif
3b439792	130	#define CONFIG_SYS_FPGA_BASE 0xFF000000
5bb907a4 RM	131
	132	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	133	#define NAND_MAX_CHIPS 1
	134	#define CONFIG_MTD_NAND_VERIFY_WRITE
	135	#define CONFIG_CMD_NAND 1
	136	#define CONFIG_NAND_FSL_ELBC 1
	137
	138	#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
	139	#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
	140	#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
	141	#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
6e1385d5	142	#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
5bb907a4 RM	143
	144	#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
	145	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	146	\| BR_PS_8 /* Port Size = 8 bit */ \
	147	\| BR_MS_FCM /* MSEL = FCM */ \
	148	\| BR_V ) /* valid */
	149
	150	#ifdef CONFIG_NAND_SP
	151	#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
	152	\| OR_FCM_CSCT \
	153	\| OR_FCM_CST \
	154	\| OR_FCM_CHT \
	155	\| OR_FCM_SCY_1 \
	156	\| OR_FCM_TRLX \
	157	\| OR_FCM_EHTR )
	158	#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */
	159	#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */
	160	#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
	161	#define NAND_CACHE_PAGES 32
	162	#elif defined(CONFIG_NAND_LP)
	163	#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \
	164	\| OR_FCM_PGS \
	165	\| OR_FCM_CSCT \
	166	\| OR_FCM_CST \
	167	\| OR_FCM_CHT \
	168	\| OR_FCM_SCY_1 \
	169	\| OR_FCM_TRLX \
	170	\| OR_FCM_EHTR )
	171	#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */
	172	#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */
	173	#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
	174	#define NAND_CACHE_PAGES 64
	175	#else
	176	#error Page size of NAND not defined.
	177	#endif /* CONFIG_NAND_SP */
	178
	179	#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
	180
	181	#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
	182	#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
	183
	184	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
	185
	186	#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
	187	#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
	188
3b439792 RM	189	#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_FPGA_BASE \
	190	\| BR_PS_16 \
	191	\| BR_MS_UPMA \
	192	\| BR_V )
	193	#define CONFIG_SYS_OR1_PRELIM ( OR_AM_2MB \
	194	\| OR_UPM_BCTLD)
	195
	196	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
	197	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_2MB)
	198
5bb907a4 RM	199	/*
	200	* JFFS2 configuration
	201	*/
	202	#define CONFIG_JFFS2_NAND
	203	#define CONFIG_JFFS2_DEV "nand0"
	204
	205	/* mtdparts command line support */
68d7d651	206	#define CONFIG_CMD_MTDPARTS
942556a9	207	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
5bb907a4 RM	208	#define MTDIDS_DEFAULT "nand0=nand0"
	209	#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
	210
	211	/* pass open firmware flat tree */
	212	#define CONFIG_OF_LIBFDT 1
	213	#define CONFIG_OF_BOARD_SETUP 1
	214	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	215
	216	/*
	217	* Serial Port
	218	*/
	219	#define CONFIG_CONS_INDEX 1
	220	#define CONFIG_SYS_NS16550
	221	#define CONFIG_SYS_NS16550_SERIAL
	222	#define CONFIG_SYS_NS16550_REG_SIZE 1
f5675aa5 RM	223	#ifdef CONFIG_NAND_SPL
	224	#define CONFIG_NS16550_MIN_FUNCTIONS
	225	#endif
5bb907a4 RM	226
	227	#define CONFIG_SYS_BAUDRATE_TABLE \
	228	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	229
	230	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	231	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
	232
	233	/* Use the HUSH parser */
	234	#define CONFIG_SYS_HUSH_PARSER
	235	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	236
	237	/* I2C */
	238	#define CONFIG_HARD_I2C /* I2C with hardware support*/
	239	#define CONFIG_FSL_I2C
	240	#define CONFIG_I2C_MULTI_BUS
5bb907a4 RM	241	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	242	#define CONFIG_SYS_I2C_SLAVE 0x7F
	243	#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
	244	#define CONFIG_SYS_I2C_OFFSET 0x3000
	245	#define CONFIG_SYS_I2C2_OFFSET 0x3100
	246
	247	/*
	248	* General PCI
	249	* Addresses are mapped 1-1.
	250	*/
	251	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	252	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	253	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	254	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	255	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	256	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	257	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	258	#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
	259	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	260
	261	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	262	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	263
	264	/*
	265	* TSEC
	266	*/
	267	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	268
	269	#define CONFIG_NET_MULTI
	270	#define CONFIG_GMII /* MII PHY management */
	271
	272	#ifdef CONFIG_TSEC1
	273	#define CONFIG_HAS_ETH0
	274	#define CONFIG_TSEC1_NAME "TSEC0"
	275	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	276	#define TSEC1_PHY_ADDR 0x0
	277	#define TSEC1_FLAGS TSEC_GIGABIT
	278	#define TSEC1_PHYIDX 0
	279	#endif
	280
	281	#ifdef CONFIG_TSEC2
	282	#define CONFIG_HAS_ETH1
	283	#define CONFIG_TSEC2_NAME "TSEC1"
	284	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	285	#define TSEC2_PHY_ADDR 4
	286	#define TSEC2_FLAGS TSEC_GIGABIT
	287	#define TSEC2_PHYIDX 0
	288	#endif
	289
	290
	291	/* Options are: TSEC[0-1] */
	292	#define CONFIG_ETHPRIME "TSEC1"
	293
	294	/*
	295	* Configure on-board RTC
	296	*/
	297	#define CONFIG_RTC_DS1337
	298	#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	299
	300	/*
	301	* Environment
	302	*/
	303	#if defined(CONFIG_NAND_U_BOOT)
	304	#define CONFIG_ENV_IS_IN_NAND 1
305	#define CONFIG_ENV_OFFSET (768 * 1024)
306	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
307	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
308	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
309	#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
310	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
311	#elif !defined(CONFIG_SYS_RAMBOOT)
312	#define CONFIG_ENV_IS_IN_FLASH 1
313	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
314	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
315	#define CONFIG_ENV_SIZE 0x2000
316
317	/* Address and size of Redundant Environment Sector */
318	#else
319	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
320	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
321	#define CONFIG_ENV_SIZE 0x2000
322	#endif
323
324	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
325	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
326
327	/*
328	* BOOTP options
329	*/
330	#define CONFIG_BOOTP_BOOTFILESIZE
331	#define CONFIG_BOOTP_BOOTPATH
332	#define CONFIG_BOOTP_GATEWAY
333	#define CONFIG_BOOTP_HOSTNAME
334
335
336	/*
337	* Command line configuration.
338	*/
339	#include <config_cmd_default.h>
340	#undef CONFIG_CMD_IMLS
341	#undef CONFIG_CMD_FLASH
342
343	#define CONFIG_CMD_PING
344	#define CONFIG_CMD_DHCP
345	#define CONFIG_CMD_I2C
346	#define CONFIG_CMD_MII
347	#define CONFIG_CMD_DATE
348	#define CONFIG_CMD_PCI
349	#define CONFIG_CMD_JFFS2
350
351	#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
bdab39d3	352	#undef CONFIG_CMD_SAVEENV
5bb907a4 RM	353	#undef CONFIG_CMD_LOADS
	354	#endif
	355
	356	#define CONFIG_CMDLINE_EDITING 1
a059e90e	357	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
5bb907a4 RM	358
	359	/*
	360	* Miscellaneous configurable options
	361	*/
	362	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	363	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	364	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	365	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	366
	367	#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \
	368	+ sizeof(CONFIG_SYS_PROMPT) \
	369	+ 16 ) /* Print Buffer Size */
	370	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	371	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	372	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
	373
	374	/*
	375	* For booting Linux, the board info and command line data
9f530d59	376	* have to be in the first 256 MB of memory, since this is
5bb907a4 RM	377	* the maximum mapped by the Linux kernel during initialization.
5bb907a4 RM	378	*/
9f530d59	379	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
5bb907a4 RM	380
	381	#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
	382
	383	#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
	384	\| 0x20000000 /* reserved */ \
	385	\| HRCWL_DDR_TO_SCB_CLK_2X1 \
	386	\| HRCWL_CSB_TO_CLKIN_4X1 \
	387	\| HRCWL_CORE_TO_CSB_2_5X1 )
	388
	389	#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
	390
	391	#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \
	392	\| HRCWH_PCI1_ARBITER_ENABLE \
	393	\| HRCWH_CORE_ENABLE \
	394	\| HRCWH_BOOTSEQ_DISABLE \
	395	\| HRCWH_SW_WATCHDOG_DISABLE \
	396	\| HRCWH_TSEC1M_IN_RGMII \
	397	\| HRCWH_TSEC2M_IN_RGMII \
	398	\| HRCWH_BIG_ENDIAN \
	399	\| HRCWH_LALE_NORMAL )
	400
	401	#ifdef CONFIG_NAND_LP
	402	#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
	403	\| HRCWH_FROM_0XFFF00100 \
	404	\| HRCWH_ROM_LOC_NAND_LP_8BIT \
	405	\| HRCWH_RL_EXT_NAND)
	406	#else
	407	#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \
	408	\| HRCWH_FROM_0XFFF00100 \
	409	\| HRCWH_ROM_LOC_NAND_SP_8BIT \
	410	\| HRCWH_RL_EXT_NAND )
	411	#endif
	412
	413	/* System IO Config */
	414	#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \
	415	\| SICRH_ETSEC2_C \
	416	\| SICRH_ETSEC2_D \
	417	\| SICRH_ETSEC2_E \
	418	\| SICRH_ETSEC2_F \
	419	\| SICRH_ETSEC2_G \
	420	\| SICRH_TSOBI1 \
	421	\| SICRH_TSOBI2 )
b1e1a42b	422	#define CONFIG_SYS_SICRL ( SICRL_LBC \
f986325d	423	\| SICRL_USBDR_10 \
5bb907a4 RM	424	\| SICRL_ETSEC2_A )
	425
	426	#define CONFIG_SYS_HID0_INIT 0x000000000
1a2e203b KP	427	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	428	HID0_ENABLE_INSTRUCTION_CACHE \| \
	429	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT )
5bb907a4 RM	430
	431	#define CONFIG_SYS_HID2 HID2_HBE
	432
	433	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
	434
	435	/* DDR @ 0x00000000 */
	436	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10)
	437	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	438	#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \| BATL_PP_10)
	439	#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	440
	441	/* PCI @ 0x80000000 */
	442	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE \| BATL_PP_10)
	443	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	444	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	445	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	446
	447	/* PCI2 not supported on 8313 */
	448	#define CONFIG_SYS_IBAT4L (0)
	449	#define CONFIG_SYS_IBAT4U (0)
	450
	451	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
	452	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	453	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	454
	455	/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
c1230980	456	#define CONFIG_SYS_IBAT6L (0xF0000000 \| BATL_PP_10 \| BATL_GUARDEDSTORAGE)
5bb907a4 RM	457	#define CONFIG_SYS_IBAT6U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	458
	459	#define CONFIG_SYS_IBAT7L (0)
	460	#define CONFIG_SYS_IBAT7U (0)
	461
	462	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	463	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	464	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	465	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	466	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
	467	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	468	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	469	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	470	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	471	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
	472	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	473	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	474	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	475	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	476	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	477	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
	478
	479	/*
	480	* Internal Definitions
	481	*
	482	* Boot Flags
	483	*/
	484	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	485	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	486
	487	/*
	488	* Environment Configuration
	489	*/
	490	#define CONFIG_ENV_OVERWRITE
	491
	492	#define CONFIG_NETDEV eth1
	493
	494	#define CONFIG_HOSTNAME simpc8313
	495	#define CONFIG_ROOTPATH /tftpboot/
	496	#define CONFIG_BOOTFILE /tftpboot/uImage
	497	#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */
	498	#define CONFIG_FDTFILE simpc8313.dtb
	499
	500	#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
	501	#define CONFIG_BOOTDELAY 5 /* 5 second delay */
	502	#define CONFIG_BAUDRATE 115200
	503
	504	#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr"
	505
	506	#define XMK_STR(x) #x
	507	#define MK_STR(x) XMK_STR(x)
	508
	509	#define CONFIG_EXTRA_ENV_SETTINGS \
	510	"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
	511	"ethprime=TSEC1\0" \
	512	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
	513	"tftpflash=tftpboot $loadaddr $uboot; " \
	514	"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
	515	"erase " MK_STR(TEXT_BASE) " +$filesize; " \
	516	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
	517	"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
	518	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
	519	"fdtaddr=ae0000\0" \
	520	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
521	"console=ttyS0\0" \
522	"setbootargs=setenv bootargs " \
523	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
524	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
525	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
526	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
527	"load_uboot=tftp 100000 u-boot-nand.bin\0" \
528	"burn_uboot=nand erase u-boot 80000; " \
529	"nand write 100000 u-boot $filesize\0" \
530	"update_uboot=run load_uboot;run burn_uboot\0" \
531	"mtdids=nand0=nand0\0" \
532	"mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
533	"nfsargs=setenv bootargs root=/dev/nfs rw " \
534	"nfsroot=${serverip}:${rootpath}\0" \
535	"ramargs=setenv bootargs root=/dev/ram rw\0" \
536	"addip=setenv bootargs ${bootargs} " \
537	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
538	":${hostname}:${netdev}:off panic=1\0" \
539	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
540	"bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
541	"console=ttyS0,115200\0" \
542	""
543
544	#define CONFIG_NFSBOOTCOMMAND \
545	"setenv rootdev /dev/nfs;" \
546	"run setbootargs;" \
547	"run setipargs;" \
548	"tftp $loadaddr $bootfile;" \
549	"tftp $fdtaddr $fdtfile;" \
550	"bootm $loadaddr - $fdtaddr"
551
552	#define CONFIG_RAMBOOTCOMMAND \
553	"setenv rootdev /dev/ram;" \
554	"run setbootargs;" \
555	"tftp $ramdiskaddr $ramdiskfile;" \
556	"tftp $loadaddr $bootfile;" \
557	"tftp $fdtaddr $fdtfile;" \
558	"bootm $loadaddr $ramdiskaddr $fdtaddr"
559
560	#undef MK_STR
561	#undef XMK_STR
562
563	#endif /* __CONFIG_H */