[J-u-boot.git] / include / configs / atc.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC8260		1	/* This is an MPC8260 CPU		*/
#define CONFIG_ATC		1	/* ...on a ATC board	*/
#define CONFIG_CPM2		1	/* Has a CPM2 */

/*
 * select serial console configuration
 *
 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 * for SCC).
 *
 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 * defined elsewhere (for example, on the cogent platform, there are serial
 * ports on the motherboard which are used for the serial console - see
 * cogent/cma101/serial.[ch]).
 */
#define  CONFIG_CONS_ON_SMC		/* define if console on SMC */
#undef CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else*/
#define CONFIG_CONS_INDEX	2	/* which serial channel for console */

#define CONFIG_BAUDRATE		115200

/*
 * select ethernet configuration
 *
 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 * for FCC)
 *
 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
 * from CONFIG_COMMANDS to remove support for networking.
 *
 */
#undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC       */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_ON_FCC

#define	CONFIG_NET_MULTI
#define CONFIG_ETHER_ON_FCC2

/*
 * - Rx-CLK is CLK13
 * - Tx-CLK is CLK14
 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 * - Enable Full Duplex in FSMR
 */
# define CFG_CMXFCR_MASK2	(CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
# define CFG_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
# define CFG_CPMFCR_RAMTYPE	0
# define CFG_FCC_PSMR		(FCC_PSMR_FDE|FCC_PSMR_LPB)

#define CONFIG_ETHER_ON_FCC3

/*
 * - Rx-CLK is CLK15
 * - Tx-CLK is CLK16
 * - RAM for BD/Buffers is on the local Bus (see 28-13)
 * - Enable Half Duplex in FSMR
 */
# define CFG_CMXFCR_MASK3	(CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
# define CFG_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)

/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
#define CONFIG_8260_CLKIN	64000000	/* in Hz */

#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#undef	CONFIG_CLOCKS_IN_MHZ		/* clocks passsed to Linux in Hz */

#define CONFIG_PREBOOT							\
	"echo;"								\
	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
	"echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND						\
	"bootp;"							\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$(serverip):$(rootpath) " 				\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
	"bootm"

/*-----------------------------------------------------------------------
 * Miscellaneous configuration options
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)

#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
				 CFG_CMD_EEPROM | \
				 CFG_CMD_PCI | \
				 CFG_CMD_PCMCIA | \
				 CFG_CMD_DATE | \
				 CFG_CMD_IDE)


#define CONFIG_DOS_PARTITION

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END	0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CFG_LOAD_ADDR	0x100000	/* default load address	*/

#define CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_RESET_ADDRESS 0xFFF00100	/* "bad" address		*/

#define CFG_ALLOC_DPRAM

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SPI

#define CONFIG_RTC_DS12887

#define RTC_BASE_ADDR 		0xF5000000
#define RTC_PORT_ADDR 		RTC_BASE_ADDR + 0x800
#define RTC_PORT_DATA 		RTC_BASE_ADDR + 0x808

#define CONFIG_MISC_INIT_R

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * Flash configuration
 */

#define CFG_FLASH_BASE		0xFF000000
#define CFG_FLASH_SIZE		0x00800000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
#define CFG_MAX_FLASH_SECT	128	/* max num of sects on one chip */

#define CFG_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)  */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)  */

#define CONFIG_FLASH_16BIT

/*-----------------------------------------------------------------------
 * Hard Reset Configuration Words
 *
 * if you change bits in the HRCW, you must also change the CFG_*
 * defines for the various registers affected by the HRCW e.g. changing
 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 */
#define CFG_HRCW_MASTER		(HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
				 HRCW_BPS10 |\
				 HRCW_APPC10)

/* no slaves so just fill with zeros */
#define CFG_HRCW_SLAVE1		0
#define CFG_HRCW_SLAVE2		0
#define CFG_HRCW_SLAVE3		0
#define CFG_HRCW_SLAVE4		0
#define CFG_HRCW_SLAVE5		0
#define CFG_HRCW_SLAVE6		0
#define CFG_HRCW_SLAVE7		0

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00  /* End of used area in DPRAM    */
#define CFG_GBL_DATA_SIZE	128 /* size in bytes reserved for initial data*/
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 *
 * 60x SDRAM is mapped at CFG_SDRAM_BASE.
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_SDRAM_MAX_SIZE	0x08000000	/* max. 128 MB		*/
#define CFG_MONITOR_BASE	TEXT_BASE
#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor */
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()*/

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT
#endif

#define	CONFIG_PCI
#define	CONFIG_PCI_PNP
#define	CFG_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */

#if 1
/* environment is in Flash */
#define CFG_ENV_IS_IN_FLASH	1
# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x30000)
# define CFG_ENV_SIZE		0x10000
# define CFG_ENV_SECT_SIZE	0x10000
#else
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_ENV_OFFSET		0
#define CFG_ENV_SIZE		2048
#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/
#endif
/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/
#define BOOTFLAG_WARM		0x02	/* Software reboot                 */


/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * HIDx - Hardware Implementation-dependent Registers                    2-11
 *-----------------------------------------------------------------------
 * HID0 also contains cache control - initially enable both caches and
 * invalidate contents, then the final state leaves only the instruction
 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 * but Soft reset does not.
 *
 * HID1 has only read-only information - nothing to set.
 */
#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\
			 HID0_DCI|HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)
#define CFG_HID2        0

/*-----------------------------------------------------------------------
 * RMR - Reset Mode Register                                     5-5
 *-----------------------------------------------------------------------
 * turn on Checkstop Reset Enable
 */
#define CFG_RMR         RMR_CSRE

/*-----------------------------------------------------------------------
 * BCR - Bus Configuration                                       4-25
 *-----------------------------------------------------------------------
 */
#define BCR_APD01	0x10000000
#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration                             4-31
 *-----------------------------------------------------------------------
 */
#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\
			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control                             4-35
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
			 SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * TMCNTSC - Time Counter Status and Control                     4-40
 *-----------------------------------------------------------------------
 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 * and enable Time Counter
 */
#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control                 4-42
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 * Periodic timer
 */
#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock Control                                   9-8
 *-----------------------------------------------------------------------
 * Ensure DFBRG is Divide by 16
 */
#define CFG_SCCR        SCCR_DFBRG01

/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration                         13-7
 *-----------------------------------------------------------------------
 */
#define CFG_RCCR        0

#define CFG_MIN_AM_MASK	0xC0000000
/*-----------------------------------------------------------------------
 * MPTPR - Memory Refresh Timer Prescaler Register              10-18
 *-----------------------------------------------------------------------
 */
#define CFG_MPTPR       0x1F00

/*-----------------------------------------------------------------------
 * PSRT - Refresh Timer Register                                10-16
 *-----------------------------------------------------------------------
 */
#define CFG_PSRT        0x0f

/*-----------------------------------------------------------------------
 * PSRT - SDRAM Mode Register                                   10-10
 *-----------------------------------------------------------------------
 */

	/* SDRAM initialization values for 8-column chips
	 */
#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A7		|\
			 ORxS_NUMR_12)

#define CFG_PSDMR_8COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A15_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A7		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

	/* SDRAM initialization values for 9-column chips
	 */
#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\
			 ORxS_BPD_4			|\
			 ORxS_ROWST_PBI1_A6		|\
			 ORxS_NUMR_12)

#define CFG_PSDMR_9COL	(PSDMR_PBI			|\
			 PSDMR_SDAM_A16_IS_A5		|\
			 PSDMR_BSMA_A15_A17		|\
			 PSDMR_SDA10_PBI1_A6		|\
			 PSDMR_RFRC_7_CLK		|\
			 PSDMR_PRETOACT_3W		|\
			 PSDMR_ACTTORW_2W		|\
			 PSDMR_LDOTOPRE_1C		|\
			 PSDMR_WRC_1C			|\
			 PSDMR_CL_2)

/*
 * Init Memory Controller:
 *
 * Bank Bus     Machine PortSz  Device
 * ---- ---     ------- ------  ------
 *  0   60x     GPCM    8  bit  Boot ROM
 *  1   60x     GPCM    64 bit  FLASH
 *  2   60x     SDRAM   64 bit  SDRAM
 *
 */

#define CFG_MRS_OFFS	0x00000000

/* Bank 0 - FLASH
 */
#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
			 BRx_PS_16                      |\
			 BRx_MS_GPCM_P                  |\
			 BRx_V)

#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\
			 ORxG_CSNT                      |\
			 ORxG_ACS_DIV1                  |\
			 ORxG_SCY_3_CLK                 |\
			 ORxU_EHTR_8IDLE)


/* Bank 2 - 60x bus SDRAM
 */
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
			 BRx_PS_64                      |\
			 BRx_MS_SDRAM_P                 |\
			 BRx_V)

#define CFG_OR2_PRELIM	 CFG_OR2_8COL

#define CFG_PSDMR	 CFG_PSDMR_8COL
#endif /* CFG_RAMBOOT */

#define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\
			 BRx_PS_8                       |\
			 BRx_MS_UPMA                    |\
			 BRx_V)

#define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_I82365

#define CFG_PCMCIA_MEM_ADDR	0x81000000
#define CFG_PCMCIA_MEM_SIZE	0x1000

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_BASE_ADDR	0xa0000000

/* Offset for data I/O			*/
#define CFG_ATA_DATA_OFFSET	0x100

/* Offset for normal register accesses	*/
#define CFG_ATA_REG_OFFSET	0x100

/* Offset for alternate registers	*/
#define CFG_ATA_ALT_OFFSET	0x108

#endif	/* __CONFIG_H */
Commit	Line	Data
7aa78614 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
	37	#define CONFIG_ATC 1 /* ...on a ATC board */
9c4c5ae3	38	#define CONFIG_CPM2 1 /* Has a CPM2 */
7aa78614 WD	39
	40	/*
	41	* select serial console configuration
	42	*
	43	* if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
	44	* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
	45	* for SCC).
	46	*
	47	* if CONFIG_CONS_NONE is defined, then the serial console routines must
	48	* defined elsewhere (for example, on the cogent platform, there are serial
	49	* ports on the motherboard which are used for the serial console - see
	50	* cogent/cma101/serial.[ch]).
	51	*/
	52	#define CONFIG_CONS_ON_SMC /* define if console on SMC */
	53	#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
	54	#undef CONFIG_CONS_NONE /* define if console on something else*/
	55	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
	56
	57	#define CONFIG_BAUDRATE 115200
	58
	59	/*
	60	* select ethernet configuration
	61	*
	62	* if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
	63	* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
	64	* for FCC)
	65	*
	66	* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
	67	* defined elsewhere (as for the console), or CFG_CMD_NET must be removed
	68	* from CONFIG_COMMANDS to remove support for networking.
	69	*
	70	*/
	71	#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
	72	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	73	#define CONFIG_ETHER_ON_FCC
	74
	75	#define CONFIG_NET_MULTI
	76	#define CONFIG_ETHER_ON_FCC2
	77
	78	/*
	79	* - Rx-CLK is CLK13
	80	* - Tx-CLK is CLK14
	81	* - RAM for BD/Buffers is on the 60x Bus (see 28-13)
	82	* - Enable Full Duplex in FSMR
	83	*/
	84	# define CFG_CMXFCR_MASK2 (CMXFCR_FC2\|CMXFCR_RF2CS_MSK\|CMXFCR_TF2CS_MSK)
	85	# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13\|CMXFCR_TF2CS_CLK14)
	86	# define CFG_CPMFCR_RAMTYPE 0
	87	# define CFG_FCC_PSMR (FCC_PSMR_FDE\|FCC_PSMR_LPB)
	88
	89	#define CONFIG_ETHER_ON_FCC3
	90
	91	/*
	92	* - Rx-CLK is CLK15
	93	* - Tx-CLK is CLK16
	94	* - RAM for BD/Buffers is on the local Bus (see 28-13)
	95	* - Enable Half Duplex in FSMR
	96	*/
	97	# define CFG_CMXFCR_MASK3 (CMXFCR_FC3\|CMXFCR_RF3CS_MSK\|CMXFCR_TF3CS_MSK)
	98	# define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15\|CMXFCR_TF3CS_CLK16)
	99
	100	/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
	101	#define CONFIG_8260_CLKIN 64000000 /* in Hz */
	102
103	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
104
105	#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
106
107	#define CONFIG_PREBOOT \
108	"echo;" \
109	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;"\
110	"echo"
111
112	#undef CONFIG_BOOTARGS
113	#define CONFIG_BOOTCOMMAND \
114	"bootp;" \
115	"setenv bootargs root=/dev/nfs rw " \
116	"nfsroot=$(serverip):$(rootpath) " \
117	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"\
118	"bootm"
119
120	/*-----------------------------------------------------------------------
121	* Miscellaneous configuration options
122	*/
123
124	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
125	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
126
127	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT\|CONFIG_BOOTP_BOOTFILESIZE)
128
66fd3d1c WD	129	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
	130	CFG_CMD_EEPROM \| \
	131	CFG_CMD_PCI \| \
	132	CFG_CMD_PCMCIA \| \
15ef8a5d	133	CFG_CMD_DATE \| \
66fd3d1c	134	CFG_CMD_IDE)
15ef8a5d WD	135
15ef8a5d WD	136
66fd3d1c	137	#define CONFIG_DOS_PARTITION
7aa78614 WD	138
	139	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	140	#include <cmd_confdefs.h>
	141
	142	/*
	143	* Miscellaneous configurable options
	144	*/
	145	#define CFG_LONGHELP /* undef to save memory */
	146	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	147	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	148	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	149	#else
	150	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	151	#endif
	152	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	153	#define CFG_MAXARGS 16 /* max number of command args */
	154	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	155
	156	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	157	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	158
	159	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	160
66fd3d1c WD	161	#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
66fd3d1c WD	162
7aa78614 WD	163	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	164
	165	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	166
	167	#define CFG_RESET_ADDRESS 0xFFF00100 /* "bad" address */
	168
	169	#define CFG_ALLOC_DPRAM
	170
	171	#undef CONFIG_WATCHDOG /* watchdog disabled */
	172
	173	#define CONFIG_SPI
	174
15ef8a5d WD	175	#define CONFIG_RTC_DS12887
15ef8a5d WD	176
9a0e21a3	177	#define RTC_BASE_ADDR 0xF5000000
15ef8a5d WD	178	#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
	179	#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
	180
	181	#define CONFIG_MISC_INIT_R
	182
7aa78614 WD	183	/*
	184	* For booting Linux, the board info and command line data
	185	* have to be in the first 8 MB of memory, since this is
	186	* the maximum mapped by the Linux kernel during initialization.
	187	*/
	188	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	189
	190	/*-----------------------------------------------------------------------
	191	* Flash configuration
	192	*/
	193
7aa78614 WD	194	#define CFG_FLASH_BASE 0xFF000000
	195	#define CFG_FLASH_SIZE 0x00800000
	196
	197	/*-----------------------------------------------------------------------
	198	* FLASH organization
	199	*/
	200	#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
	201	#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
	202
	203	#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
	204	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
	205
	206	#define CONFIG_FLASH_16BIT
	207
	208	/*-----------------------------------------------------------------------
	209	* Hard Reset Configuration Words
	210	*
	211	* if you change bits in the HRCW, you must also change the CFG_*
	212	* defines for the various registers affected by the HRCW e.g. changing
	213	* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
	214	*/
	215	#define CFG_HRCW_MASTER (HRCW_CIP \| HRCW_ISB100 \| HRCW_BMS \| \
9a0e21a3	216	HRCW_BPS10 \|\
7aa78614 WD	217	HRCW_APPC10)
	218
	219	/* no slaves so just fill with zeros */
	220	#define CFG_HRCW_SLAVE1 0
	221	#define CFG_HRCW_SLAVE2 0
	222	#define CFG_HRCW_SLAVE3 0
	223	#define CFG_HRCW_SLAVE4 0
	224	#define CFG_HRCW_SLAVE5 0
	225	#define CFG_HRCW_SLAVE6 0
	226	#define CFG_HRCW_SLAVE7 0
	227
	228	/*-----------------------------------------------------------------------
	229	* Internal Memory Mapped Register
	230	*/
	231	#define CFG_IMMR 0xF0000000
	232
	233	/*-----------------------------------------------------------------------
	234	* Definitions for initial stack pointer and data area (in DPRAM)
	235	*/
	236	#define CFG_INIT_RAM_ADDR CFG_IMMR
	237	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	238	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
	239	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	240	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	241
	242	/*-----------------------------------------------------------------------
	243	* Start addresses for the final memory configuration
	244	* (Set up by the startup code)
	245	* Please note that CFG_SDRAM_BASE _must_ start at 0
	246	*
	247	* 60x SDRAM is mapped at CFG_SDRAM_BASE.
	248	*/
	249	#define CFG_SDRAM_BASE 0x00000000
	250	#define CFG_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
	251	#define CFG_MONITOR_BASE TEXT_BASE
e6009629	252	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
7aa78614 WD	253	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
	254
	255	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	256	# define CFG_RAMBOOT
	257	#endif
	258
66fd3d1c WD	259	#define CONFIG_PCI
66fd3d1c WD	260	#define CONFIG_PCI_PNP
5d232d0e	261	#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
66fd3d1c	262
7aa78614 WD	263	#if 1
	264	/* environment is in Flash */
	265	#define CFG_ENV_IS_IN_FLASH 1
e6009629	266	# define CFG_ENV_ADDR (CFG_FLASH_BASE+0x30000)
7aa78614 WD	267	# define CFG_ENV_SIZE 0x10000
	268	# define CFG_ENV_SECT_SIZE 0x10000
	269	#else
	270	#define CFG_ENV_IS_IN_EEPROM 1
	271	#define CFG_ENV_OFFSET 0
	272	#define CFG_ENV_SIZE 2048
	273	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
	274	#endif
	275	/*
	276	* Internal Definitions
	277	*
	278	* Boot Flags
	279	*/
	280	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
	281	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	282
	283
	284	/*-----------------------------------------------------------------------
	285	* Cache Configuration
	286	*/
	287	#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
	288	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	289	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	290	#endif
	291
	292	/*-----------------------------------------------------------------------
	293	* HIDx - Hardware Implementation-dependent Registers 2-11
	294	*-----------------------------------------------------------------------
	295	* HID0 also contains cache control - initially enable both caches and
	296	* invalidate contents, then the final state leaves only the instruction
	297	* cache enabled. Note that Power-On and Hard reset invalidate the caches,
	298	* but Soft reset does not.
	299	*
	300	* HID1 has only read-only information - nothing to set.
	301	*/
	302	#define CFG_HID0_INIT (HID0_ICE\|HID0_DCE\|HID0_ICFI\|\
8bde7f77	303	HID0_DCI\|HID0_IFEM\|HID0_ABE)
7aa78614 WD	304	#define CFG_HID0_FINAL (HID0_IFEM\|HID0_ABE)
	305	#define CFG_HID2 0
	306
	307	/*-----------------------------------------------------------------------
	308	* RMR - Reset Mode Register 5-5
	309	*-----------------------------------------------------------------------
	310	* turn on Checkstop Reset Enable
	311	*/
	312	#define CFG_RMR RMR_CSRE
	313
	314	/*-----------------------------------------------------------------------
	315	* BCR - Bus Configuration 4-25
	316	*-----------------------------------------------------------------------
	317	*/
	318	#define BCR_APD01 0x10000000
	319	#define CFG_BCR (BCR_APD01\|BCR_ETM\|BCR_LETM) /* 8260 mode */
	320
	321	/*-----------------------------------------------------------------------
	322	* SIUMCR - SIU Module Configuration 4-31
	323	*-----------------------------------------------------------------------
	324	*/
9a0e21a3	325	#define CFG_SIUMCR (SIUMCR_BBD\|SIUMCR_APPC10\|\
7aa78614 WD	326	SIUMCR_CS10PC00\|SIUMCR_BCTLC10)
	327
	328	/*-----------------------------------------------------------------------
	329	* SYPCR - System Protection Control 4-35
	330	* SYPCR can only be written once after reset!
	331	*-----------------------------------------------------------------------
	332	* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
	333	*/
	334	#if defined(CONFIG_WATCHDOG)
	335	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	336	SYPCR_SWRI\|SYPCR_SWP\|SYPCR_SWE)
7aa78614 WD	337	#else
7aa78614 WD	338	#define CFG_SYPCR (SYPCR_SWTC\|SYPCR_BMT\|SYPCR_PBME\|SYPCR_LBME\|\
8bde7f77	339	SYPCR_SWRI\|SYPCR_SWP)
7aa78614 WD	340	#endif /* CONFIG_WATCHDOG */
	341
	342	/*-----------------------------------------------------------------------
	343	* TMCNTSC - Time Counter Status and Control 4-40
	344	*-----------------------------------------------------------------------
	345	* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
	346	* and enable Time Counter
	347	*/
	348	#define CFG_TMCNTSC (TMCNTSC_SEC\|TMCNTSC_ALR\|TMCNTSC_TCF\|TMCNTSC_TCE)
	349
	350	/*-----------------------------------------------------------------------
	351	* PISCR - Periodic Interrupt Status and Control 4-42
	352	*-----------------------------------------------------------------------
	353	* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
	354	* Periodic timer
	355	*/
	356	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
	357
	358	/*-----------------------------------------------------------------------
	359	* SCCR - System Clock Control 9-8
	360	*-----------------------------------------------------------------------
	361	* Ensure DFBRG is Divide by 16
	362	*/
	363	#define CFG_SCCR SCCR_DFBRG01
	364
	365	/*-----------------------------------------------------------------------
	366	* RCCR - RISC Controller Configuration 13-7
	367	*-----------------------------------------------------------------------
	368	*/
	369	#define CFG_RCCR 0
	370
	371	#define CFG_MIN_AM_MASK 0xC0000000
	372	/*-----------------------------------------------------------------------
	373	* MPTPR - Memory Refresh Timer Prescaler Register 10-18
	374	*-----------------------------------------------------------------------
	375	*/
	376	#define CFG_MPTPR 0x1F00
	377
	378	/*-----------------------------------------------------------------------
	379	* PSRT - Refresh Timer Register 10-16
	380	*-----------------------------------------------------------------------
	381	*/
	382	#define CFG_PSRT 0x0f
	383
	384	/*-----------------------------------------------------------------------
	385	* PSRT - SDRAM Mode Register 10-10
	386	*-----------------------------------------------------------------------
	387	*/
	388
	389	/* SDRAM initialization values for 8-column chips
	390	*/
	391	#define CFG_OR2_8COL (CFG_MIN_AM_MASK \|\
	392	ORxS_BPD_4 \|\
f7de16ae WD	393	ORxS_ROWST_PBI1_A7 \|\
f7de16ae WD	394	ORxS_NUMR_12)
7aa78614	395
f7de16ae WD	396	#define CFG_PSDMR_8COL (PSDMR_PBI \|\
	397	PSDMR_SDAM_A15_IS_A5 \|\
	398	PSDMR_BSMA_A15_A17 \|\
	399	PSDMR_SDA10_PBI1_A7 \|\
7aa78614	400	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	401	PSDMR_PRETOACT_3W \|\
f7de16ae WD	402	PSDMR_ACTTORW_2W \|\
7aa78614 WD	403	PSDMR_LDOTOPRE_1C \|\
	404	PSDMR_WRC_1C \|\
	405	PSDMR_CL_2)
	406
	407	/* SDRAM initialization values for 9-column chips
	408	*/
	409	#define CFG_OR2_9COL (CFG_MIN_AM_MASK \|\
	410	ORxS_BPD_4 \|\
f7de16ae WD	411	ORxS_ROWST_PBI1_A6 \|\
f7de16ae WD	412	ORxS_NUMR_12)
7aa78614	413
f7de16ae WD	414	#define CFG_PSDMR_9COL (PSDMR_PBI \|\
	415	PSDMR_SDAM_A16_IS_A5 \|\
	416	PSDMR_BSMA_A15_A17 \|\
	417	PSDMR_SDA10_PBI1_A6 \|\
7aa78614	418	PSDMR_RFRC_7_CLK \|\
f7de16ae WD	419	PSDMR_PRETOACT_3W \|\
f7de16ae WD	420	PSDMR_ACTTORW_2W \|\
7aa78614 WD	421	PSDMR_LDOTOPRE_1C \|\
	422	PSDMR_WRC_1C \|\
	423	PSDMR_CL_2)
	424
	425	/*
	426	* Init Memory Controller:
	427	*
	428	* Bank Bus Machine PortSz Device
	429	* ---- --- ------- ------ ------
	430	* 0 60x GPCM 8 bit Boot ROM
	431	* 1 60x GPCM 64 bit FLASH
	432	* 2 60x SDRAM 64 bit SDRAM
	433	*
	434	*/
	435
	436	#define CFG_MRS_OFFS 0x00000000
	437
	438	/* Bank 0 - FLASH
	439	*/
	440	#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	441	BRx_PS_16 \|\
	442	BRx_MS_GPCM_P \|\
	443	BRx_V)
7aa78614 WD	444
7aa78614 WD	445	#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) \|\
8bde7f77 WD	446	ORxG_CSNT \|\
	447	ORxG_ACS_DIV1 \|\
	448	ORxG_SCY_3_CLK \|\
	449	ORxU_EHTR_8IDLE)
7aa78614 WD	450
	451
	452	/* Bank 2 - 60x bus SDRAM
	453	*/
	454	#ifndef CFG_RAMBOOT
	455	#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) \|\
8bde7f77 WD	456	BRx_PS_64 \|\
	457	BRx_MS_SDRAM_P \|\
	458	BRx_V)
7aa78614 WD	459
	460	#define CFG_OR2_PRELIM CFG_OR2_8COL
	461
	462	#define CFG_PSDMR CFG_PSDMR_8COL
	463	#endif /* CFG_RAMBOOT */
	464
15ef8a5d	465	#define CFG_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) \|\
8bde7f77 WD	466	BRx_PS_8 \|\
	467	BRx_MS_UPMA \|\
	468	BRx_V)
15ef8a5d WD	469
15ef8a5d WD	470	#define CFG_OR4_PRELIM (ORxU_AM_MSK \| ORxU_BI)
8bde7f77	471
66fd3d1c WD	472	/*-----------------------------------------------------------------------
	473	* PCMCIA stuff
	474	*-----------------------------------------------------------------------
	475	*
	476	*/
	477	#define CONFIG_I82365
	478
	479	#define CFG_PCMCIA_MEM_ADDR 0x81000000
	480	#define CFG_PCMCIA_MEM_SIZE 0x1000
	481
	482	/*-----------------------------------------------------------------------
	483	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	484	*-----------------------------------------------------------------------
	485	*/
	486
	487	#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
	488
	489	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	490	#undef CONFIG_IDE_LED /* LED for ide not supported */
	491	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	492
	493	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
	494	#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
	495
	496	#define CFG_ATA_IDE0_OFFSET 0x0000
	497
	498	#define CFG_ATA_BASE_ADDR 0xa0000000
	499
	500	/* Offset for data I/O */
	501	#define CFG_ATA_DATA_OFFSET 0x100
	502
	503	/* Offset for normal register accesses */
	504	#define CFG_ATA_REG_OFFSET 0x100
	505
	506	/* Offset for alternate registers */
	507	#define CFG_ATA_ALT_OFFSET 0x108
	508
7aa78614	509	#endif /* __CONFIG_H */