Commit | Line | Data |
---|---|---|
83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
3df619ec LW |
2 | /* |
3 | * (C) Copyright 2011 | |
4 | * Marvell Inc, <www.marvell.com> | |
3df619ec LW |
5 | */ |
6 | ||
7 | #ifndef _MV_I2C_H_ | |
8 | #define _MV_I2C_H_ | |
9 | extern void i2c_clk_enable(void); | |
10 | ||
11 | /* Shall the current transfer have a start/stop condition? */ | |
12 | #define I2C_COND_NORMAL 0 | |
13 | #define I2C_COND_START 1 | |
14 | #define I2C_COND_STOP 2 | |
15 | ||
16 | /* Shall the current transfer be ack/nacked or being waited for it? */ | |
17 | #define I2C_ACKNAK_WAITACK 1 | |
18 | #define I2C_ACKNAK_SENDACK 2 | |
19 | #define I2C_ACKNAK_SENDNAK 4 | |
20 | ||
21 | /* Specify who shall transfer the data (master or slave) */ | |
22 | #define I2C_READ 0 | |
23 | #define I2C_WRITE 1 | |
24 | ||
3df619ec | 25 | #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) |
3df619ec LW |
26 | |
27 | #define I2C_ISR_INIT 0x7FF | |
28 | /* ----- Control register bits ---------------------------------------- */ | |
29 | ||
30 | #define ICR_START 0x1 /* start bit */ | |
31 | #define ICR_STOP 0x2 /* stop bit */ | |
32 | #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ | |
33 | #define ICR_TB 0x8 /* transfer byte bit */ | |
34 | #define ICR_MA 0x10 /* master abort */ | |
35 | #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ | |
36 | #define ICR_IUE 0x40 /* unit enable */ | |
37 | #define ICR_GCD 0x80 /* general call disable */ | |
38 | #define ICR_ITEIE 0x100 /* enable tx interrupts */ | |
39 | #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ | |
40 | #define ICR_BEIE 0x400 /* enable bus error ints */ | |
41 | #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ | |
42 | #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ | |
43 | #define ICR_SADIE 0x2000 /* slave address detected int enable */ | |
44 | #define ICR_UR 0x4000 /* unit reset */ | |
9ad5a007 SR |
45 | #ifdef CONFIG_ARMADA_3700 |
46 | #define ICR_SM 0x00000 /* Standard Mode */ | |
47 | #define ICR_FM 0x10000 /* Fast Mode */ | |
48 | #define ICR_MODE_MASK 0x30000 /* Mode mask */ | |
49 | #else | |
50 | #define ICR_SM 0x00000 /* Standard Mode */ | |
51 | #define ICR_FM 0x08000 /* Fast Mode */ | |
52 | #define ICR_MODE_MASK 0x18000 /* Mode mask */ | |
53 | #endif | |
3df619ec LW |
54 | |
55 | /* ----- Status register bits ----------------------------------------- */ | |
56 | ||
57 | #define ISR_RWM 0x1 /* read/write mode */ | |
58 | #define ISR_ACKNAK 0x2 /* ack/nak status */ | |
59 | #define ISR_UB 0x4 /* unit busy */ | |
60 | #define ISR_IBB 0x8 /* bus busy */ | |
61 | #define ISR_SSD 0x10 /* slave stop detected */ | |
62 | #define ISR_ALD 0x20 /* arbitration loss detected */ | |
63 | #define ISR_ITE 0x40 /* tx buffer empty */ | |
64 | #define ISR_IRF 0x80 /* rx buffer full */ | |
65 | #define ISR_GCAD 0x100 /* general call address detected */ | |
66 | #define ISR_SAD 0x200 /* slave address detected */ | |
67 | #define ISR_BED 0x400 /* bus error no ACK/NAK */ | |
68 | ||
69 | #endif |