[J-u-boot.git] / include / configs / microblaze-generic.h

/*
 * (C) Copyright 2007-2010 Michal Simek
 *
 * Michal SIMEK <monstr@monstr.eu>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/xilinx/microblaze-generic/xparameters.h"

/* MicroBlaze CPU */
#define	MICROBLAZE_V5		1

/* Open Firmware DTS */
#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic

/* linear and spi flash memory */
#ifdef XILINX_FLASH_START
#define	FLASH
#undef	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#ifdef XILINX_SPI_FLASH_BASEADDR
#undef	FLASH
#define	SPIFLASH
#undef	RAMENV	/* hold environment in flash */
#else
#undef	FLASH
#undef	SPIFLASH
#define	RAMENV	/* hold environment in RAM */
#endif
#endif

/* uart */
#ifdef XILINX_UARTLITE_BASEADDR
# define CONFIG_XILINX_UARTLITE
# define CONFIG_SERIAL_BASE	XILINX_UARTLITE_BASEADDR
# define CONFIG_BAUDRATE	XILINX_UARTLITE_BAUDRATE
# define CONFIG_SYS_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
# define CONSOLE_ARG	"console=console=ttyUL0,115200\0"
#elif XILINX_UART16550_BASEADDR
# define CONFIG_SYS_NS16550		1
# define CONFIG_SYS_NS16550_SERIAL
# if defined(__MICROBLAZEEL__)
#  define CONFIG_SYS_NS16550_REG_SIZE	-4
# else
#  define CONFIG_SYS_NS16550_REG_SIZE	4
# endif
# define CONFIG_CONS_INDEX		1
# define CONFIG_SYS_NS16550_COM1 \
		((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
# define CONFIG_SYS_NS16550_CLK	XILINX_UART16550_CLOCK_HZ
# define CONFIG_BAUDRATE	115200

/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
# define CONSOLE_ARG	"console=console=ttyS0,115200\0"
#else
# error Undefined uart
#endif

/* setting reset address */
/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/

/* ethernet */
#undef CONFIG_SYS_ENET
#if defined(XILINX_EMACLITE_BASEADDR) || defined(CONFIG_OF_CONTROL)
# define CONFIG_XILINX_EMACLITE	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_LLTEMAC_BASEADDR)
# define CONFIG_XILINX_LL_TEMAC	1
# define CONFIG_SYS_ENET
#endif
#if defined(XILINX_AXIEMAC_BASEADDR)
# define CONFIG_XILINX_AXIEMAC	1
# define CONFIG_SYS_ENET
#endif

#undef ET_DEBUG

/* gpio */
#ifdef XILINX_GPIO_BASEADDR
# define CONFIG_XILINX_GPIO
# define CONFIG_SYS_GPIO_0_ADDR		XILINX_GPIO_BASEADDR
#endif

/* interrupt controller */
#ifdef XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_ADDR		XILINX_INTC_BASEADDR
# define CONFIG_SYS_INTC_0_NUM		XILINX_INTC_NUM_INTR_INPUTS
#endif

/* timer */
#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
#  define CONFIG_SYS_TIMER_0_ADDR	XILINX_TIMER_BASEADDR
#  define CONFIG_SYS_TIMER_0_IRQ	XILINX_TIMER_IRQ
#endif

/* watchdog */
#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
# define CONFIG_WATCHDOG_BASEADDR	XILINX_WATCHDOG_BASEADDR
# define CONFIG_WATCHDOG_IRQ		XILINX_WATCHDOG_IRQ
# define CONFIG_HW_WATCHDOG
# define CONFIG_XILINX_TB_WATCHDOG
#endif

/*
 * memory layout - Example
 * CONFIG_SYS_TEXT_BASE = 0x1200_0000;	defined in config.mk
 * CONFIG_SYS_SRAM_BASE = 0x1000_0000;
 * CONFIG_SYS_SRAM_SIZE = 0x0400_0000;	64MB
 *
 * CONFIG_SYS_MONITOR_LEN = 0x40000
 * CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
 *
 * CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
 * CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
 * CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
 *
 * 0x1000_0000	CONFIG_SYS_SDRAM_BASE
 *					MEMTEST_AREA	 64kB
 *					FREE
 * 0x1200_0000	CONFIG_SYS_TEXT_BASE
 *		U-BOOT code
 * 0x1202_0000
 *					FREE
 *
 *					STACK
 * 0x13EF_F000	CONFIG_SYS_MALLOC_BASE
 *					MALLOC_AREA	768kB	Alloc
 * 0x13FB_F000	CONFIG_SYS_MONITOR_BASE
 *					MONITOR_CODE	256kB	Env
 * 0x13FF_F000	CONFIG_SYS_GBL_DATA_OFFSET
 *					GLOBAL_DATA	4kB	bd, gd
 * 0x1400_0000	CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
 */

/* ddr sdram - main memory */
#define	CONFIG_SYS_SDRAM_BASE		XILINX_RAM_START
#define	CONFIG_SYS_SDRAM_SIZE		XILINX_RAM_SIZE
#define	CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define	CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x1000)

/* global pointer */
/* start of global data */
#define	CONFIG_SYS_GBL_DATA_OFFSET \
		(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)

/* monitor code */
#define	SIZE				0x40000
#define	CONFIG_SYS_MONITOR_LEN		SIZE
#define	CONFIG_SYS_MONITOR_BASE	\
		(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
			- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
#define	CONFIG_SYS_MONITOR_END \
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define	CONFIG_SYS_MALLOC_LEN		(SIZE * 3)
#define	CONFIG_SYS_MALLOC_BASE \
			(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)

/* stack */
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_MALLOC_BASE

/*
 * CFI flash memory layout - Example
 * CONFIG_SYS_FLASH_BASE = 0x2200_0000;
 * CONFIG_SYS_FLASH_SIZE = 0x0080_0000;	  8MB
 *
 * SECT_SIZE = 0x20000;			128kB is one sector
 * CONFIG_ENV_SIZE = SECT_SIZE;		128kB environment store
 *
 * 0x2200_0000	CONFIG_SYS_FLASH_BASE
 *					FREE		256kB
 * 0x2204_0000	CONFIG_ENV_ADDR
 *					ENV_AREA	128kB
 * 0x2206_0000
 *					FREE
 * 0x2280_0000	CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
 *
 */

#ifdef FLASH
# define CONFIG_SYS_FLASH_BASE		XILINX_FLASH_START
# define CONFIG_SYS_FLASH_SIZE		XILINX_FLASH_SIZE
# define CONFIG_SYS_FLASH_CFI		1
# define CONFIG_FLASH_CFI_DRIVER	1
/* ?empty sector */
# define CONFIG_SYS_FLASH_EMPTY_INFO	1
/* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_BANKS	1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT	512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define	CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* FLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_FLASH	1
/* 128K(one sector) for env */
#  define CONFIG_ENV_SECT_SIZE	0x20000
#  define CONFIG_ENV_ADDR \
			(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
#  define CONFIG_ENV_SIZE	0x20000
# endif /* FLASH && !RAMBOOT */
#else /* !FLASH */

#ifdef SPIFLASH
# define CONFIG_SYS_NO_FLASH		1
# define CONFIG_SYS_SPI_BASE		XILINX_SPI_FLASH_BASEADDR
# define CONFIG_XILINX_SPI		1
# define CONFIG_SPI			1
# define CONFIG_SPI_FLASH		1
# define CONFIG_SPI_FLASH_STMICRO	1
# define CONFIG_SF_DEFAULT_MODE		SPI_MODE_3
# define CONFIG_SF_DEFAULT_SPEED	XILINX_SPI_FLASH_MAX_FREQ
# define CONFIG_SF_DEFAULT_CS		XILINX_SPI_FLASH_CS

# ifdef	RAMENV
#  define CONFIG_ENV_IS_NOWHERE	1
#  define CONFIG_ENV_SIZE	0x1000
#  define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)

# else	/* SPIFLASH && !RAMENV */
#  define CONFIG_ENV_IS_IN_SPI_FLASH	1
#  define CONFIG_ENV_SPI_MODE		SPI_MODE_3
#  define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
#  define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
/* 128K(two sectors) for env */
#  define CONFIG_ENV_SECT_SIZE	0x10000
#  define CONFIG_ENV_SIZE	(2 * CONFIG_ENV_SECT_SIZE)
/* Warning: adjust the offset in respect of other flash content and size */
#  define CONFIG_ENV_OFFSET	(128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
# endif /* SPIFLASH && !RAMBOOT */
#else /* !SPIFLASH */

/* ENV in RAM */
# define CONFIG_SYS_NO_FLASH	1
# define CONFIG_ENV_IS_NOWHERE	1
# define CONFIG_ENV_SIZE	0x1000
# define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
#endif /* !SPIFLASH */
#endif /* !FLASH */

/* system ace */
#ifdef XILINX_SYSACE_BASEADDR
# define CONFIG_SYSTEMACE
/* #define DEBUG_SYSTEMACE */
# define SYSTEMACE_CONFIG_FPGA
# define CONFIG_SYS_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
# define CONFIG_SYS_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
# define CONFIG_DOS_PARTITION
#endif

#if defined(XILINX_USE_ICACHE)
# define CONFIG_ICACHE
#else
# undef CONFIG_ICACHE
#endif

#if defined(XILINX_USE_DCACHE)
# define CONFIG_DCACHE
#else
# undef CONFIG_DCACHE
#endif

#ifndef XILINX_DCACHE_BYTE_SIZE
#define XILINX_DCACHE_BYTE_SIZE	32768
#endif

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_MFSL
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_GPIO

#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE)
# define CONFIG_CMD_CACHE
#else
# undef CONFIG_CMD_CACHE
#endif

#ifndef CONFIG_SYS_ENET
# undef CONFIG_CMD_NET
# undef CONFIG_CMD_NFS
#else
# define CONFIG_CMD_PING
# define CONFIG_CMD_DHCP
# define CONFIG_CMD_TFTPPUT
#endif

#if defined(CONFIG_SYSTEMACE)
# define CONFIG_CMD_EXT2
# define CONFIG_CMD_FAT
#endif

#if defined(FLASH)
# define CONFIG_CMD_ECHO
# define CONFIG_CMD_FLASH
# define CONFIG_CMD_IMLS
# define CONFIG_CMD_JFFS2
# define CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif

#else
#if defined(SPIFLASH)
# define CONFIG_CMD_SF

# if !defined(RAMENV)
#  define CONFIG_CMD_SAVEENV
#  define CONFIG_CMD_SAVES
# endif
#else
# undef CONFIG_CMD_IMLS
# undef CONFIG_CMD_FLASH
# undef CONFIG_CMD_JFFS2
# undef CONFIG_CMD_UBI
# undef CONFIG_CMD_UBIFS
#endif
#endif

#if defined(CONFIG_CMD_JFFS2)
# define CONFIG_MTD_PARTITIONS
#endif

#if defined(CONFIG_CMD_UBIFS)
# define CONFIG_CMD_UBI
# define CONFIG_LZO
#endif

#if defined(CONFIG_CMD_UBI)
# define CONFIG_MTD_PARTITIONS
# define CONFIG_RBTREE
#endif

#if defined(CONFIG_MTD_PARTITIONS)
/* MTD partitions */
#define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=flash-0"

/* default mtd partition table */
#define MTDPARTS_DEFAULT	"mtdparts=flash-0:256k(u-boot),"\
				"256k(env),3m(kernel),1m(romfs),"\
				"1m(cramfs),-(jffs2)"
#endif

/* Miscellaneous configurable options */
#define	CONFIG_SYS_PROMPT	"U-Boot-mONStR> "
/* size of console buffer */
#define	CONFIG_SYS_CBSIZE	512
 /* print buffer size */
#define	CONFIG_SYS_PBSIZE \
		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* max number of command args */
#define	CONFIG_SYS_MAXARGS	15
#define	CONFIG_SYS_LONGHELP
/* default load address */
#define	CONFIG_SYS_LOAD_ADDR	XILINX_RAM_START

#define	CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define	CONFIG_BOOTARGS		"root=romfs"
#define	CONFIG_HOSTNAME		XILINX_BOARD_NAME
#define	CONFIG_BOOTCOMMAND	"base 0;tftp 11000000 image.img;bootm"
#define	CONFIG_IPADDR		192.168.0.3
#define	CONFIG_SERVERIP		192.168.0.5
#define	CONFIG_GATEWAYIP	192.168.0.1
#define	CONFIG_ETHADDR		00:E0:0C:00:00:FD

/* architecture dependent code */
#define	CONFIG_SYS_USR_EXCEP	/* user exception */

#define	CONFIG_PREBOOT	"echo U-BOOT for ${hostname};setenv preboot;echo"

#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" \
					"nor0=flash-0\0"\
					"mtdparts=mtdparts=flash-0:"\
					"256k(u-boot),256k(env),3m(kernel),"\
					"1m(romfs),1m(cramfs),-(jffs2)\0"\
					"nc=setenv stdout nc;"\
					"setenv stdin nc\0" \
					"serial=setenv stdout serial;"\
					"setenv stdin serial\0"

#define CONFIG_CMDLINE_EDITING

#define CONFIG_NETCONSOLE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER

/* Enable flat device tree support */
#define CONFIG_LMB		1
#define CONFIG_FIT		1
#define CONFIG_OF_LIBFDT	1

#if defined(CONFIG_XILINX_LL_TEMAC) || defined(CONFIG_XILINX_AXIEMAC)
# define CONFIG_MII		1
# define CONFIG_CMD_MII		1
# define CONFIG_PHY_GIGE	1
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	1
# define CONFIG_PHYLIB		1
# define CONFIG_PHY_ATHEROS	1
# define CONFIG_PHY_BROADCOM	1
# define CONFIG_PHY_DAVICOM	1
# define CONFIG_PHY_LXT		1
# define CONFIG_PHY_MARVELL	1
# define CONFIG_PHY_MICREL	1
# define CONFIG_PHY_NATSEMI	1
# define CONFIG_PHY_REALTEK	1
# define CONFIG_PHY_VITESSE	1
#else
# undef CONFIG_MII
# undef CONFIG_CMD_MII
# undef CONFIG_PHYLIB
#endif

/* SPL part */
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT

#define CONFIG_SPL_LDSCRIPT	"arch/microblaze/cpu/u-boot-spl.lds"

#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_NOR_SUPPORT

/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT

#define CONFIG_SYS_OS_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x60000)
#define CONFIG_SYS_FDT_BASE		(CONFIG_SYS_FLASH_BASE + \
					 0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_TEXT_BASE + \
					 0x1000000)

/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
/* Stack pointer prior relocation, must situated at on-chip RAM */
#define CONFIG_SYS_SPL_MALLOC_END	(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100

/*
 * The main reason to do it in this way is that MALLOC_START
 * can't be defined - common/spl/spl.c
 */
#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
# define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_SPL_MALLOC_END - \
					 CONFIG_SYS_SPL_MALLOC_SIZE)
# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_START
#else
# define CONFIG_SPL_STACK_ADDR		CONFIG_SYS_SPL_MALLOC_END
#endif

/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE		0x100

#define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_UBOOT_START		CONFIG_SYS_TEXT_BASE

#define CONFIG_SPL_MAX_FOOTPRINT	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_INIT_RAM_ADDR - \
					 GENERATED_GBL_DATA_SIZE - \
					 CONFIG_SYS_SPL_MALLOC_SIZE - \
					 CONFIG_SPL_STACK_SIZE)

#endif	/* __CONFIG_H */
Commit	Line	Data
76316a31	1	/*
4aecfb16	2	* (C) Copyright 2007-2010 Michal Simek
76316a31	3	*
cb1bc63b	4	* Michal SIMEK <monstr@monstr.eu>
76316a31	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
76316a31 MS	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
52a822ed	12	#include "../board/xilinx/microblaze-generic/xparameters.h"
76316a31	13
4aecfb16	14	/* MicroBlaze CPU */
1a50f164	15	#define MICROBLAZE_V5 1
76316a31	16
920c3587	17	/* Open Firmware DTS */
6697d558	18	#define CONFIG_DEFAULT_DEVICE_TREE microblaze-generic
920c3587	19
bcec8f49	20	/* linear and spi flash memory */
1fe7e8fa SL	21	#ifdef XILINX_FLASH_START
1fe7e8fa SL	22	#define FLASH
bcec8f49	23	#undef SPIFLASH
1fe7e8fa SL	24	#undef RAMENV /* hold environment in flash */
1fe7e8fa SL	25	#else
bcec8f49	26	#ifdef XILINX_SPI_FLASH_BASEADDR
1fe7e8fa	27	#undef FLASH
bcec8f49 SL	28	#define SPIFLASH
	29	#undef RAMENV /* hold environment in flash */
	30	#else
	31	#undef FLASH
	32	#undef SPIFLASH
1fe7e8fa SL	33	#define RAMENV /* hold environment in RAM */
1fe7e8fa SL	34	#endif
bcec8f49	35	#endif
1fe7e8fa	36
76316a31	37	/* uart */
af7ae1a4	38	#ifdef XILINX_UARTLITE_BASEADDR
4aecfb16 MS	39	# define CONFIG_XILINX_UARTLITE
	40	# define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR
	41	# define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE
	42	# define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
	43	# define CONSOLE_ARG "console=console=ttyUL0,115200\0"
e7d591e8	44	#elif XILINX_UART16550_BASEADDR
4aecfb16 MS	45	# define CONFIG_SYS_NS16550 1
4aecfb16 MS	46	# define CONFIG_SYS_NS16550_SERIAL
1de55ef1 SL	47	# if defined(__MICROBLAZEEL__)
	48	# define CONFIG_SYS_NS16550_REG_SIZE -4
	49	# else
	50	# define CONFIG_SYS_NS16550_REG_SIZE 4
	51	# endif
4aecfb16 MS	52	# define CONFIG_CONS_INDEX 1
4aecfb16 MS	53	# define CONFIG_SYS_NS16550_COM1 \
1de55ef1	54	((XILINX_UART16550_BASEADDR & ~0xF) + 0x1000)
4aecfb16 MS	55	# define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ
	56	# define CONFIG_BAUDRATE 115200
	57
	58	/* The following table includes the supported baudrates */
	59	# define CONFIG_SYS_BAUDRATE_TABLE \
	60	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
	61	# define CONSOLE_ARG "console=console=ttyS0,115200\0"
e7d591e8	62	#else
4aecfb16	63	# error Undefined uart
af7ae1a4	64	#endif
76316a31 MS	65
76316a31 MS	66	/* setting reset address */
14d0a02a	67	/#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE/
76316a31	68
17980495	69	/* ethernet */
1252df06	70	#undef CONFIG_SYS_ENET
d1d37b5c	71	#if defined(XILINX_EMACLITE_BASEADDR) \|\| defined(CONFIG_OF_CONTROL)
8422a35e	72	# define CONFIG_XILINX_EMACLITE 1
4aecfb16	73	# define CONFIG_SYS_ENET
8422a35e SL	74	#endif
	75	#if defined(XILINX_LLTEMAC_BASEADDR)
	76	# define CONFIG_XILINX_LL_TEMAC 1
4aecfb16	77	# define CONFIG_SYS_ENET
e5845e21	78	#endif
e634138e MS	79	#if defined(XILINX_AXIEMAC_BASEADDR)
	80	# define CONFIG_XILINX_AXIEMAC 1
	81	# define CONFIG_SYS_ENET
	82	#endif
330e5545	83
e5845e21	84	#undef ET_DEBUG
17980495	85
76316a31	86	/* gpio */
4c6a6f02	87	#ifdef XILINX_GPIO_BASEADDR
4e779ad2	88	# define CONFIG_XILINX_GPIO
4aecfb16	89	# define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR
4c6a6f02	90	#endif
76316a31 MS	91
76316a31 MS	92	/* interrupt controller */
4d49b280	93	#ifdef XILINX_INTC_BASEADDR
4aecfb16 MS	94	# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR
4aecfb16 MS	95	# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
4d49b280	96	#endif
76316a31 MS	97
76316a31 MS	98	/* timer */
bcbb046b	99	#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ)
4aecfb16 MS	100	# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR
4aecfb16 MS	101	# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ
4d49b280	102	#endif
bcbb046b	103
0f21f98d MS	104	/* watchdog */
	105	#if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ)
	106	# define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR
	107	# define CONFIG_WATCHDOG_IRQ XILINX_WATCHDOG_IRQ
	108	# define CONFIG_HW_WATCHDOG
	109	# define CONFIG_XILINX_TB_WATCHDOG
	110	#endif
	111
76316a31 MS	112	/*
76316a31 MS	113	* memory layout - Example
8f371b18	114	* CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk
6d0f6bcf	115	* CONFIG_SYS_SRAM_BASE = 0x1000_0000;
8f371b18 SL	116	* CONFIG_SYS_SRAM_SIZE = 0x0400_0000; 64MB
	117	*
	118	* CONFIG_SYS_MONITOR_LEN = 0x40000
	119	* CONFIG_SYS_MALLOC_LEN = 3 * CONFIG_SYS_MONITOR_LEN = 0xC0000
76316a31	120	*
6d0f6bcf	121	* CONFIG_SYS_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
8f371b18 SL	122	* CONFIG_SYS_MONITOR_BASE = 0x13FF_F000 - CONFIG_SYS_MONITOR_LEN = 0x13FB_F000
8f371b18 SL	123	* CONFIG_SYS_MALLOC_BASE = 0x13FB_F000 - CONFIG_SYS_MALLOC_LEN = 0x13EF_F000
76316a31	124	*
6d0f6bcf	125	* 0x1000_0000 CONFIG_SYS_SDRAM_BASE
8f371b18	126	* MEMTEST_AREA 64kB
76316a31	127	* FREE
14d0a02a	128	* 0x1200_0000 CONFIG_SYS_TEXT_BASE
76316a31 MS	129	* U-BOOT code
	130	* 0x1202_0000
	131	* FREE
	132	*
	133	* STACK
8f371b18 SL	134	* 0x13EF_F000 CONFIG_SYS_MALLOC_BASE
	135	* MALLOC_AREA 768kB Alloc
	136	* 0x13FB_F000 CONFIG_SYS_MONITOR_BASE
17980495	137	* MONITOR_CODE 256kB Env
6d0f6bcf	138	* 0x13FF_F000 CONFIG_SYS_GBL_DATA_OFFSET
853643d8	139	* GLOBAL_DATA 4kB bd, gd
6d0f6bcf	140	* 0x1400_0000 CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE
76316a31 MS	141	*/
	142
	143	/* ddr sdram - main memory */
6d0f6bcf JCPV	144	#define CONFIG_SYS_SDRAM_BASE XILINX_RAM_START
	145	#define CONFIG_SYS_SDRAM_SIZE XILINX_RAM_SIZE
	146	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	147	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000)
76316a31 MS	148
76316a31 MS	149	/* global pointer */
32556443	150	/* start of global data */
4aecfb16	151	#define CONFIG_SYS_GBL_DATA_OFFSET \
1020286e	152	(CONFIG_SYS_SDRAM_SIZE - GENERATED_GBL_DATA_SIZE)
76316a31 MS	153
76316a31 MS	154	/* monitor code */
4aecfb16	155	#define SIZE 0x40000
1020286e	156	#define CONFIG_SYS_MONITOR_LEN SIZE
4aecfb16	157	#define CONFIG_SYS_MONITOR_BASE \
1020286e MS	158	(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_GBL_DATA_OFFSET \
1020286e MS	159	- CONFIG_SYS_MONITOR_LEN - GENERATED_BD_INFO_SIZE)
4aecfb16 MS	160	#define CONFIG_SYS_MONITOR_END \
4aecfb16 MS	161	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
7cfb13a7	162	#define CONFIG_SYS_MALLOC_LEN (SIZE * 3)
4aecfb16 MS	163	#define CONFIG_SYS_MALLOC_BASE \
4aecfb16 MS	164	(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
76316a31 MS	165
76316a31 MS	166	/* stack */
8fe7b29f	167	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_MALLOC_BASE
76316a31	168
8f371b18 SL	169	/*
	170	* CFI flash memory layout - Example
	171	* CONFIG_SYS_FLASH_BASE = 0x2200_0000;
	172	* CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB
	173	*
	174	* SECT_SIZE = 0x20000; 128kB is one sector
	175	* CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store
	176	*
	177	* 0x2200_0000 CONFIG_SYS_FLASH_BASE
	178	* FREE 256kB
	179	* 0x2204_0000 CONFIG_ENV_ADDR
	180	* ENV_AREA 128kB
	181	* 0x2206_0000
	182	* FREE
	183	* 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE
	184	*
	185	*/
	186
76316a31	187	#ifdef FLASH
4aecfb16 MS	188	# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START
	189	# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE
	190	# define CONFIG_SYS_FLASH_CFI 1
	191	# define CONFIG_FLASH_CFI_DRIVER 1
	192	/* ?empty sector */
	193	# define CONFIG_SYS_FLASH_EMPTY_INFO 1
	194	/* max number of memory banks */
	195	# define CONFIG_SYS_MAX_FLASH_BANKS 1
	196	/* max number of sectors on one chip */
	197	# define CONFIG_SYS_MAX_FLASH_SECT 512
	198	/* hardware flash protection */
	199	# define CONFIG_SYS_FLASH_PROTECTION
22ff7f4d MS	200	/* use buffered writes (20x faster) */
22ff7f4d MS	201	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
4aecfb16 MS	202	# ifdef RAMENV
	203	# define CONFIG_ENV_IS_NOWHERE 1
	204	# define CONFIG_ENV_SIZE 0x1000
	205	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	206
bcec8f49	207	# else /* FLASH && !RAMENV */
4aecfb16 MS	208	# define CONFIG_ENV_IS_IN_FLASH 1
	209	/* 128K(one sector) for env */
	210	# define CONFIG_ENV_SECT_SIZE 0x20000
	211	# define CONFIG_ENV_ADDR \
	212	(CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
	213	# define CONFIG_ENV_SIZE 0x20000
bcec8f49	214	# endif /* FLASH && !RAMBOOT */
76316a31	215	#else /* !FLASH */
bcec8f49 SL	216
	217	#ifdef SPIFLASH
	218	# define CONFIG_SYS_NO_FLASH 1
	219	# define CONFIG_SYS_SPI_BASE XILINX_SPI_FLASH_BASEADDR
	220	# define CONFIG_XILINX_SPI 1
	221	# define CONFIG_SPI 1
	222	# define CONFIG_SPI_FLASH 1
	223	# define CONFIG_SPI_FLASH_STMICRO 1
	224	# define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
	225	# define CONFIG_SF_DEFAULT_SPEED XILINX_SPI_FLASH_MAX_FREQ
	226	# define CONFIG_SF_DEFAULT_CS XILINX_SPI_FLASH_CS
	227
	228	# ifdef RAMENV
	229	# define CONFIG_ENV_IS_NOWHERE 1
	230	# define CONFIG_ENV_SIZE 0x1000
	231	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
	232
	233	# else /* SPIFLASH && !RAMENV */
	234	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
	235	# define CONFIG_ENV_SPI_MODE SPI_MODE_3
	236	# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
	237	# define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
	238	/* 128K(two sectors) for env */
	239	# define CONFIG_ENV_SECT_SIZE 0x10000
	240	# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE)
	241	/* Warning: adjust the offset in respect of other flash content and size */
	242	# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */
	243	# endif /* SPIFLASH && !RAMBOOT */
	244	#else /* !SPIFLASH */
	245
4aecfb16 MS	246	/* ENV in RAM */
	247	# define CONFIG_SYS_NO_FLASH 1
	248	# define CONFIG_ENV_IS_NOWHERE 1
	249	# define CONFIG_ENV_SIZE 0x1000
	250	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE)
bcec8f49	251	#endif /* !SPIFLASH */
76316a31 MS	252	#endif /* !FLASH */
76316a31 MS	253
853643d8 MS	254	/* system ace */
853643d8 MS	255	#ifdef XILINX_SYSACE_BASEADDR
4aecfb16 MS	256	# define CONFIG_SYSTEMACE
	257	/* #define DEBUG_SYSTEMACE */
	258	# define SYSTEMACE_CONFIG_FPGA
	259	# define CONFIG_SYS_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
	260	# define CONFIG_SYS_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
	261	# define CONFIG_DOS_PARTITION
853643d8 MS	262	#endif
853643d8 MS	263
e9b737de	264	#if defined(XILINX_USE_ICACHE)
4aecfb16	265	# define CONFIG_ICACHE
e9b737de	266	#else
4aecfb16	267	# undef CONFIG_ICACHE
e9b737de MS	268	#endif
	269
	270	#if defined(XILINX_USE_DCACHE)
4aecfb16	271	# define CONFIG_DCACHE
e9b737de	272	#else
4aecfb16	273	# undef CONFIG_DCACHE
e9b737de MS	274	#endif
e9b737de MS	275
5811830f MS	276	#ifndef XILINX_DCACHE_BYTE_SIZE
	277	#define XILINX_DCACHE_BYTE_SIZE 32768
	278	#endif
	279
079a136c JL	280	/*
	281	* BOOTP options
	282	*/
	283	#define CONFIG_BOOTP_BOOTFILESIZE
	284	#define CONFIG_BOOTP_BOOTPATH
	285	#define CONFIG_BOOTP_GATEWAY
	286	#define CONFIG_BOOTP_HOSTNAME
76316a31	287
5dc11a51 JL	288	/*
	289	* Command line configuration.
	290	*/
	291	#include <config_cmd_default.h>
	292
	293	#define CONFIG_CMD_ASKENV
5dc11a51	294	#define CONFIG_CMD_IRQ
5dc11a51	295	#define CONFIG_CMD_MFSL
330e5545	296	#define CONFIG_CMD_ECHO
4e779ad2	297	#define CONFIG_CMD_GPIO
4d49b280	298
e9b737de	299	#if defined(CONFIG_DCACHE) \|\| defined(CONFIG_ICACHE)
4aecfb16	300	# define CONFIG_CMD_CACHE
e9b737de	301	#else
4aecfb16	302	# undef CONFIG_CMD_CACHE
e9b737de MS	303	#endif
e9b737de MS	304
6d0f6bcf	305	#ifndef CONFIG_SYS_ENET
4aecfb16	306	# undef CONFIG_CMD_NET
1252df06	307	# undef CONFIG_CMD_NFS
4d49b280	308	#else
4aecfb16 MS	309	# define CONFIG_CMD_PING
4aecfb16 MS	310	# define CONFIG_CMD_DHCP
4eb29cf0	311	# define CONFIG_CMD_TFTPPUT
4d49b280	312	#endif
853643d8 MS	313
853643d8 MS	314	#if defined(CONFIG_SYSTEMACE)
4aecfb16 MS	315	# define CONFIG_CMD_EXT2
4aecfb16 MS	316	# define CONFIG_CMD_FAT
853643d8	317	#endif
5dc11a51 JL	318
5dc11a51 JL	319	#if defined(FLASH)
4aecfb16 MS	320	# define CONFIG_CMD_ECHO
	321	# define CONFIG_CMD_FLASH
	322	# define CONFIG_CMD_IMLS
	323	# define CONFIG_CMD_JFFS2
7cfb13a7 SL	324	# define CONFIG_CMD_UBI
7cfb13a7 SL	325	# undef CONFIG_CMD_UBIFS
4aecfb16	326
bcec8f49 SL	327	# if !defined(RAMENV)
	328	# define CONFIG_CMD_SAVEENV
	329	# define CONFIG_CMD_SAVES
	330	# endif
	331
	332	#else
	333	#if defined(SPIFLASH)
	334	# define CONFIG_CMD_SF
	335
4aecfb16 MS	336	# if !defined(RAMENV)
	337	# define CONFIG_CMD_SAVEENV
	338	# define CONFIG_CMD_SAVES
	339	# endif
853643d8	340	#else
4aecfb16 MS	341	# undef CONFIG_CMD_IMLS
	342	# undef CONFIG_CMD_FLASH
	343	# undef CONFIG_CMD_JFFS2
2cce2d32 SL	344	# undef CONFIG_CMD_UBI
2cce2d32 SL	345	# undef CONFIG_CMD_UBIFS
5dc11a51	346	#endif
bcec8f49	347	#endif
76316a31	348
5dc11a51	349	#if defined(CONFIG_CMD_JFFS2)
7cfb13a7 SL	350	# define CONFIG_MTD_PARTITIONS
	351	#endif
	352
	353	#if defined(CONFIG_CMD_UBIFS)
	354	# define CONFIG_CMD_UBI
	355	# define CONFIG_LZO
	356	#endif
	357
	358	#if defined(CONFIG_CMD_UBI)
	359	# define CONFIG_MTD_PARTITIONS
	360	# define CONFIG_RBTREE
	361	#endif
	362
	363	#if defined(CONFIG_MTD_PARTITIONS)
	364	/* MTD partitions */
68d7d651	365	#define CONFIG_CMD_MTDPARTS /* mtdparts command line support */
942556a9 SR	366	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	367	#define CONFIG_FLASH_CFI_MTD
c82a541d	368	#define MTDIDS_DEFAULT "nor0=flash-0"
144876a3 MS	369
144876a3 MS	370	/* default mtd partition table */
c82a541d	371	#define MTDPARTS_DEFAULT "mtdparts=flash-0:256k(u-boot),"\
144876a3 MS	372	"256k(env),3m(kernel),1m(romfs),"\
	373	"1m(cramfs),-(jffs2)"
	374	#endif
	375
76316a31	376	/* Miscellaneous configurable options */
6d0f6bcf	377	#define CONFIG_SYS_PROMPT "U-Boot-mONStR> "
4aecfb16 MS	378	/* size of console buffer */
	379	#define CONFIG_SYS_CBSIZE 512
	380	/* print buffer size */
	381	#define CONFIG_SYS_PBSIZE \
	382	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	383	/* max number of command args */
	384	#define CONFIG_SYS_MAXARGS 15
6d0f6bcf	385	#define CONFIG_SYS_LONGHELP
4aecfb16 MS	386	/* default load address */
4aecfb16 MS	387	#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START
76316a31	388
330e5545	389	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
76316a31	390	#define CONFIG_BOOTARGS "root=romfs"
330e5545	391	#define CONFIG_HOSTNAME XILINX_BOARD_NAME
853643d8	392	#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
76316a31	393	#define CONFIG_IPADDR 192.168.0.3
853643d8 MS	394	#define CONFIG_SERVERIP 192.168.0.5
853643d8 MS	395	#define CONFIG_GATEWAYIP 192.168.0.1
76316a31 MS	396	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	397
	398	/* architecture dependent code */
6d0f6bcf	399	#define CONFIG_SYS_USR_EXCEP /* user exception */
76316a31	400
0900bee9	401	#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo"
144876a3	402
4aecfb16	403	#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \
c82a541d SL	404	"nor0=flash-0\0"\
c82a541d SL	405	"mtdparts=mtdparts=flash-0:"\
144876a3	406	"256k(u-boot),256k(env),3m(kernel),"\
78376452 MS	407	"1m(romfs),1m(cramfs),-(jffs2)\0"\
	408	"nc=setenv stdout nc;"\
	409	"setenv stdin nc\0" \
	410	"serial=setenv stdout serial;"\
	411	"setenv stdin serial\0"
144876a3	412
188dc16b	413	#define CONFIG_CMDLINE_EDITING
188dc16b	414
78376452 MS	415	#define CONFIG_NETCONSOLE
	416	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	417
0900bee9 MS	418	/* Use the HUSH parser */
0900bee9 MS	419	#define CONFIG_SYS_HUSH_PARSER
0900bee9	420
37e892d9 MS	421	/* Enable flat device tree support */
	422	#define CONFIG_LMB 1
	423	#define CONFIG_FIT 1
	424	#define CONFIG_OF_LIBFDT 1
	425
8422a35e	426	#if defined(CONFIG_XILINX_LL_TEMAC) \|\| defined(CONFIG_XILINX_AXIEMAC)
f5e5e1ff SL	427	# define CONFIG_MII 1
	428	# define CONFIG_CMD_MII 1
	429	# define CONFIG_PHY_GIGE 1
	430	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
	431	# define CONFIG_PHYLIB 1
	432	# define CONFIG_PHY_ATHEROS 1
	433	# define CONFIG_PHY_BROADCOM 1
	434	# define CONFIG_PHY_DAVICOM 1
	435	# define CONFIG_PHY_LXT 1
	436	# define CONFIG_PHY_MARVELL 1
	437	# define CONFIG_PHY_MICREL 1
	438	# define CONFIG_PHY_NATSEMI 1
	439	# define CONFIG_PHY_REALTEK 1
	440	# define CONFIG_PHY_VITESSE 1
	441	#else
	442	# undef CONFIG_MII
	443	# undef CONFIG_CMD_MII
	444	# undef CONFIG_PHYLIB
	445	#endif
	446
9d242745	447	/* SPL part */
9d242745 MS	448	#define CONFIG_CMD_SPL
	449	#define CONFIG_SPL_FRAMEWORK
	450	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	451	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	452	#define CONFIG_SPL_SERIAL_SUPPORT
	453	#define CONFIG_SPL_BOARD_INIT
	454
	455	#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
	456
	457	#define CONFIG_SPL_RAM_DEVICE
	458	#define CONFIG_SPL_NOR_SUPPORT
	459
	460	/* for booting directly linux */
	461	#define CONFIG_SPL_OS_BOOT
	462
	463	#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
	464	0x60000)
	465	#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
	466	0x40000)
	467	#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
	468	0x1000000)
	469
	470	/* SP location before relocation, must use scratch RAM */
	471	/* BRAM start */
	472	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	473	/* BRAM size - will be generated */
	474	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
	475	/* Stack pointer prior relocation, must situated at on-chip RAM */
	476	#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
	477	CONFIG_SYS_INIT_RAM_SIZE - \
	478	GENERATED_GBL_DATA_SIZE)
	479
	480	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
	481
	482	/*
	483	* The main reason to do it in this way is that MALLOC_START
	484	* can't be defined - common/spl/spl.c
	485	*/
	486	#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
	487	# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
	488	CONFIG_SYS_SPL_MALLOC_SIZE)
	489	# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
	490	#else
	491	# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
	492	#endif
	493
	494	/* Just for sure that there is a space for stack */
	495	#define CONFIG_SPL_STACK_SIZE 0x100
	496
	497	#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
	498	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
	499
	500	#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
	501	CONFIG_SYS_INIT_RAM_ADDR - \
	502	GENERATED_GBL_DATA_SIZE - \
	503	CONFIG_SYS_SPL_MALLOC_SIZE - \
	504	CONFIG_SPL_STACK_SIZE)
	505
76316a31	506	#endif /* __CONFIG_H */