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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
6b245014 SDPP |
2 | /* |
3 | * (C) Copyright 2015 Xilinx, Inc, | |
4 | * Michal Simek <michal.simek@xilinx.com> | |
6b245014 SDPP |
5 | */ |
6 | ||
7 | #ifndef _ZYNQMPPL_H_ | |
8 | #define _ZYNQMPPL_H_ | |
9 | ||
10 | #include <xilinx.h> | |
cd93d625 | 11 | #include <linux/bitops.h> |
6b245014 | 12 | |
6b245014 SDPP |
13 | #define ZYNQMP_FPGA_OP_INIT (1 << 0) |
14 | #define ZYNQMP_FPGA_OP_LOAD (1 << 1) | |
15 | #define ZYNQMP_FPGA_OP_DONE (1 << 2) | |
16 | ||
a18d09ea SDPP |
17 | #define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2) |
18 | #define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3) | |
19 | ||
0cba6abb SB |
20 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 |
21 | #define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \ | |
22 | ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) | |
23 | #define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 | |
92687047 | 24 | #define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT) |
0cba6abb | 25 | |
6b245014 SDPP |
26 | extern struct xilinx_fpga_op zynqmp_op; |
27 | ||
28 | #define XILINX_ZYNQMP_DESC \ | |
29 | { xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op } | |
30 | ||
31 | #endif /* _ZYNQMPPL_H_ */ |