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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
0a333602 MV |
2 | /* |
3 | * DHCOM DH-iMX6 PDK board configuration | |
4 | * | |
5 | * Copyright (C) 2017 Marek Vasut <marex@denx.de> | |
0a333602 MV |
6 | */ |
7 | ||
8 | #ifndef __DH_IMX6_CONFIG_H | |
9 | #define __DH_IMX6_CONFIG_H | |
10 | ||
11 | #include <asm/arch/imx-regs.h> | |
12 | ||
0a333602 MV |
13 | #include "mx6_common.h" |
14 | ||
15 | /* | |
16 | * SPI NOR layout: | |
17 | * 0x00_0000-0x00_ffff ... U-Boot SPL | |
18 | * 0x01_0000-0x0f_ffff ... U-Boot | |
19 | * 0x10_0000-0x10_ffff ... U-Boot env #1 | |
20 | * 0x11_0000-0x11_ffff ... U-Boot env #2 | |
21 | * 0x12_0000-0x1f_ffff ... UNUSED | |
22 | */ | |
23 | ||
24 | /* SPL */ | |
25 | #include "imx6_spl.h" /* common IMX6 SPL configuration */ | |
26 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x11400 | |
0a333602 MV |
27 | #define CONFIG_SPL_TARGET "u-boot-with-spl.imx" |
28 | ||
29 | /* Miscellaneous configurable options */ | |
0a333602 MV |
30 | |
31 | #define CONFIG_CMDLINE_TAG | |
32 | #define CONFIG_SETUP_MEMORY_TAGS | |
33 | #define CONFIG_INITRD_TAG | |
34 | #define CONFIG_REVISION_TAG | |
35 | ||
0a333602 MV |
36 | #define CONFIG_BZIP2 |
37 | ||
38 | /* Size of malloc() pool */ | |
39 | #define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) | |
40 | ||
41 | /* Bootcounter */ | |
0a333602 MV |
42 | #define CONFIG_SYS_BOOTCOUNT_BE |
43 | ||
44 | /* FEC ethernet */ | |
0a333602 MV |
45 | #define IMX_FEC_BASE ENET_BASE_ADDR |
46 | #define CONFIG_FEC_XCV_TYPE RMII | |
47 | #define CONFIG_ETHPRIME "FEC" | |
48 | #define CONFIG_FEC_MXC_PHYADDR 0 | |
49 | #define CONFIG_ARP_TIMEOUT 200UL | |
50 | ||
0a333602 MV |
51 | /* I2C Configs */ |
52 | #define CONFIG_SYS_I2C | |
53 | #define CONFIG_SYS_I2C_MXC | |
54 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ | |
55 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
56 | #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ | |
57 | #define CONFIG_SYS_I2C_SPEED 100000 | |
58 | ||
59 | /* MMC Configs */ | |
0a333602 MV |
60 | #define CONFIG_FSL_USDHC |
61 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
62 | #define CONFIG_SYS_FSL_USDHC_NUM 3 | |
63 | #define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ | |
64 | ||
65 | /* SATA Configs */ | |
66 | #ifdef CONFIG_CMD_SATA | |
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67 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 |
68 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
69 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
70 | #define CONFIG_LBA48 | |
0a333602 MV |
71 | #endif |
72 | ||
73 | /* SPI Flash Configs */ | |
0a333602 MV |
74 | |
75 | /* UART */ | |
76 | #define CONFIG_MXC_UART | |
77 | #define CONFIG_MXC_UART_BASE UART1_BASE | |
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78 | #define CONFIG_BAUDRATE 115200 |
79 | ||
80 | /* USB Configs */ | |
81 | #ifdef CONFIG_CMD_USB | |
82 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
83 | #define CONFIG_USB_HOST_ETHER | |
84 | #define CONFIG_USB_ETHER_ASIX | |
85 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
86 | #define CONFIG_MXC_USB_FLAGS 0 | |
87 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ | |
506abdb4 MV |
88 | |
89 | /* USB Gadget (DFU, UMS) */ | |
90 | #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) | |
506abdb4 MV |
91 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) |
92 | #define DFU_DEFAULT_POLL_TIMEOUT 300 | |
93 | ||
94 | /* USB IDs */ | |
95 | #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 | |
96 | #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 | |
97 | #endif | |
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98 | #endif |
99 | ||
100 | /* Watchdog */ | |
0a333602 MV |
101 | #define CONFIG_WATCHDOG_TIMEOUT_MSECS 60000 |
102 | ||
103 | /* allow to overwrite serial and ethaddr */ | |
104 | #define CONFIG_ENV_OVERWRITE | |
105 | ||
0a333602 MV |
106 | #define CONFIG_LOADADDR 0x12000000 |
107 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
108 | ||
109 | #ifndef CONFIG_SPL_BUILD | |
110 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
111 | "console=ttymxc0,115200\0" \ | |
112 | "fdt_addr=0x18000000\0" \ | |
113 | "fdt_high=0xffffffff\0" \ | |
114 | "initrd_high=0xffffffff\0" \ | |
115 | "kernel_addr_r=0x10008000\0" \ | |
116 | "fdt_addr_r=0x13000000\0" \ | |
117 | "ramdisk_addr_r=0x18000000\0" \ | |
118 | "scriptaddr=0x14000000\0" \ | |
119 | "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ | |
120 | BOOTENV | |
121 | ||
122 | #define CONFIG_BOOTCOMMAND "run distro_bootcmd" | |
123 | ||
124 | #define BOOT_TARGET_DEVICES(func) \ | |
125 | func(MMC, mmc, 0) \ | |
126 | func(MMC, mmc, 2) \ | |
127 | func(USB, usb, 1) \ | |
128 | func(SATA, sata, 0) \ | |
129 | func(DHCP, dhcp, na) | |
130 | ||
131 | #include <config_distro_bootcmd.h> | |
132 | #endif | |
133 | ||
134 | /* Physical Memory Map */ | |
0a333602 MV |
135 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
136 | ||
137 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
138 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
139 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
140 | ||
141 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
142 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
143 | ||
144 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
145 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
146 | ||
147 | #define CONFIG_SYS_MEMTEST_START 0x10000000 | |
148 | #define CONFIG_SYS_MEMTEST_END 0x20000000 | |
149 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
150 | ||
151 | /* Environment */ | |
152 | #define CONFIG_ENV_SIZE (16 * 1024) | |
153 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT | |
154 | ||
155 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
156 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
157 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
158 | #define CONFIG_ENV_OFFSET_REDUND \ | |
159 | (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) | |
160 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
0a333602 MV |
161 | #endif |
162 | ||
163 | #endif /* __DH_IMX6_CONFIG_H */ |