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[J-u-boot.git] / cpu / mpc5xxx / fec.c
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945af8d7 1/*
5e5f9ed2 2 * (C) Copyright 2003-2005
945af8d7
WD		 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
7 */
8
9#include <common.h>
10#include <mpc5xxx.h>
11#include <malloc.h>
12#include <net.h>
13#include <miiphy.h>
14#include "sdma.h"
15#include "fec.h"
16
d87080b7
WD		 17DECLARE_GLOBAL_DATA_PTR;
18
77846748 19/* #define DEBUG 0x28 */
945af8d7
WD		 20
21#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
cbd8a35c 22 defined(CONFIG_MPC5xxx_FEC)
945af8d7 23
63ff004c
MB		 24#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
25#error "CONFIG_MII has to be defined!"
26#endif
27
945af8d7 28#if (DEBUG & 0x60)
63ff004c
MB		 29static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
30static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
945af8d7
WD		 31#endif /* DEBUG */
32
33#if (DEBUG & 0x40)
34static uint32 local_crc32(char *string, unsigned int crc_value, int len);
35#endif
36
77846748
WD		 37typedef struct {
38 uint8 data[1500]; /* actual data */
39 int length; /* actual length */
40 int used; /* buffer in use or not */
41 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
42} NBUF;
43
63ff004c
MB		 44int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
45int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
46
d4ca31c4
WD		 47/********************************************************************/
48#if (DEBUG & 0x2)
63ff004c 49static void mpc5xxx_fec_phydump (char *devname)
d4ca31c4
WD		 50{
51 uint16 phyStatus, i;
52 uint8 phyAddr = CONFIG_PHY_ADDR;
53 uint8 reg_mask[] = {
54#if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
55 /* regs to print: 0...7, 16...19, 21, 23, 24 */
56 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
58#else
59 /* regs to print: 0...8, 16...20 */
60 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
61 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
62#endif
63 };
64
65 for (i = 0; i < 32; i++) {
66 if (reg_mask[i]) {
63ff004c 67 miiphy_read(devname, phyAddr, i, &phyStatus);
d4ca31c4
WD		 68 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
69 }
70 }
71}
72#endif
73
945af8d7
WD		 74/********************************************************************/
75static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
76{
77 int ix;
78 char *data;
77846748 79 static int once = 0;
945af8d7 80
945af8d7 81 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
77846748
WD		 82 if (!once) {
83 data = (char *)malloc(FEC_MAX_PKT_SIZE);
84 if (data == NULL) {
85 printf ("RBD INIT FAILED\n");
86 return -1;
87 }
88 fec->rbdBase[ix].dataPointer = (uint32)data;
945af8d7
WD		 89 }
90 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
91 fec->rbdBase[ix].dataLength = 0;
945af8d7 92 }
77846748 93 once ++;
945af8d7
WD		 94
95 /*
96 * have the last RBD to close the ring
97 */
98 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
99 fec->rbdIndex = 0;
100
101 return 0;
102}
103
104/********************************************************************/
105static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
106{
107 int ix;
108
109 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
110 fec->tbdBase[ix].status = 0;
111 }
112
113 /*
114 * Have the last TBD to close the ring
115 */
116 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
117
118 /*
119 * Initialize some indices
120 */
121 fec->tbdIndex = 0;
122 fec->usedTbdIndex = 0;
123 fec->cleanTbdNum = FEC_TBD_NUM;
124}
125
126/********************************************************************/
151ab83a 127static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
945af8d7
WD		 128{
129 /*
130 * Reset buffer descriptor as empty
131 */
132 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
133 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
134 else
135 pRbd->status = FEC_RBD_EMPTY;
136
137 pRbd->dataLength = 0;
138
139 /*
140 * Now, we have an empty RxBD, restart the SmartDMA receive task
141 */
142 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
143
144 /*
145 * Increment BD count
146 */
147 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
148}
149
150/********************************************************************/
151static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
152{
151ab83a 153 volatile FEC_TBD *pUsedTbd;
945af8d7
WD		 154
155#if (DEBUG & 0x1)
156 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
157 fec->cleanTbdNum, fec->usedTbdIndex);
158#endif
159
160 /*
161 * process all the consumed TBDs
162 */
163 while (fec->cleanTbdNum < FEC_TBD_NUM) {
164 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
165 if (pUsedTbd->status & FEC_TBD_READY) {
166#if (DEBUG & 0x20)
167 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
168#endif
169 return;
170 }
171
172 /*
173 * clean this buffer descriptor
174 */
175 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
176 pUsedTbd->status = FEC_TBD_WRAP;
177 else
178 pUsedTbd->status = 0;
179
180 /*
181 * update some indeces for a correct handling of the TBD ring
182 */
183 fec->cleanTbdNum++;
184 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
185 }
186}
187
188/********************************************************************/
189static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
190{
191 uint8 currByte; /* byte for which to compute the CRC */
192 int byte; /* loop - counter */
193 int bit; /* loop - counter */
194 uint32 crc = 0xffffffff; /* initial value */
195
196 /*
197 * The algorithm used is the following:
198 * we loop on each of the six bytes of the provided address,
199 * and we compute the CRC by left-shifting the previous
200 * value by one position, so that each bit in the current
201 * byte of the address may contribute the calculation. If
202 * the latter and the MSB in the CRC are different, then
203 * the CRC value so computed is also ex-ored with the
204 * "polynomium generator". The current byte of the address
205 * is also shifted right by one bit at each iteration.
206 * This is because the CRC generatore in hardware is implemented
207 * as a shift-register with as many ex-ores as the radixes
208 * in the polynomium. This suggests that we represent the
209 * polynomiumm itself as a 32-bit constant.
210 */
211 for (byte = 0; byte < 6; byte++) {
212 currByte = mac[byte];
213 for (bit = 0; bit < 8; bit++) {
214 if ((currByte & 0x01) ^ (crc & 0x01)) {
215 crc >>= 1;
216 crc = crc ^ 0xedb88320;
217 } else {
218 crc >>= 1;
219 }
220 currByte >>= 1;
221 }
222 }
223
224 crc = crc >> 26;
225
226 /*
227 * Set individual hash table register
228 */
229 if (crc >= 32) {
230 fec->eth->iaddr1 = (1 << (crc - 32));
231 fec->eth->iaddr2 = 0;
232 } else {
233 fec->eth->iaddr1 = 0;
234 fec->eth->iaddr2 = (1 << crc);
235 }
236
237 /*
238 * Set physical address
239 */
240 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
241 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
242}
243
244/********************************************************************/
245static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
246{
247 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
248 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
945af8d7
WD		 249
250#if (DEBUG & 0x1)
251 printf ("mpc5xxx_fec_init... Begin\n");
252#endif
253
254 /*
255 * Initialize RxBD/TxBD rings
256 */
257 mpc5xxx_fec_rbd_init(fec);
258 mpc5xxx_fec_tbd_init(fec);
259
945af8d7
WD		 260 /*
261 * Clear FEC-Lite interrupt event register(IEVENT)
262 */
263 fec->eth->ievent = 0xffffffff;
264
265 /*
266 * Set interrupt mask register
267 */
268 fec->eth->imask = 0x00000000;
269
270 /*
271 * Set FEC-Lite receive control register(R_CNTRL):
272 */
273 if (fec->xcv_type == SEVENWIRE) {
274 /*
275 * Frame length=1518; 7-wire mode
276 */
277 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
278 } else {
279 /*
280 * Frame length=1518; MII mode;
281 */
282 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
283 }
284
7e780369
WD		 285 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
286 if (fec->xcv_type != SEVENWIRE) {
945af8d7 287 /*
7152b1d0 288 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
945af8d7
WD		 289 * and do not drop the Preamble.
290 */
7152b1d0 291 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
945af8d7
WD		 292 }
293
294 /*
295 * Set Opcode/Pause Duration Register
296 */
297 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
298
299 /*
300 * Set Rx FIFO alarm and granularity value
301 */
c44ffb9e
WD		 302 fec->eth->rfifo_cntrl = 0x0c000000
303 | (fec->eth->rfifo_cntrl & ~0x0f000000);
945af8d7
WD		 304 fec->eth->rfifo_alarm = 0x0000030c;
305#if (DEBUG & 0x22)
306 if (fec->eth->rfifo_status & 0x00700000 ) {
307 printf("mpc5xxx_fec_init() RFIFO error\n");
308 }
309#endif
310
311 /*
312 * Set Tx FIFO granularity value
313 */
c44ffb9e
WD		 314 fec->eth->tfifo_cntrl = 0x0c000000
315 | (fec->eth->tfifo_cntrl & ~0x0f000000);
945af8d7
WD		 316#if (DEBUG & 0x2)
317 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
318 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
319#endif
320
321 /*
322 * Set transmit fifo watermark register(X_WMRK), default = 64
323 */
324 fec->eth->tfifo_alarm = 0x00000080;
325 fec->eth->x_wmrk = 0x2;
326
327 /*
328 * Set individual address filter for unicast address
329 * and set physical address registers.
330 */
77ddac94 331 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
945af8d7
WD		 332
333 /*
334 * Set multicast address filter
335 */
336 fec->eth->gaddr1 = 0x00000000;
337 fec->eth->gaddr2 = 0x00000000;
338
339 /*
340 * Turn ON cheater FSM: ????
341 */
342 fec->eth->xmit_fsm = 0x03000000;
343
344#if defined(CONFIG_MPC5200)
345 /*
346 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
347 * work w/ the current receive task.
348 */
349 sdma->PtdCntrl |= 0x00000001;
350#endif
351
352 /*
353 * Set priority of different initiators
354 */
355 sdma->IPR0 = 7; /* always */
356 sdma->IPR3 = 6; /* Eth RX */
357 sdma->IPR4 = 5; /* Eth Tx */
358
359 /*
360 * Clear SmartDMA task interrupt pending bits
361 */
362 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
363
945af8d7
WD		 364 /*
365 * Initialize SmartDMA parameters stored in SRAM
366 */
151ab83a
WD		 367 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
368 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
369 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
370 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
945af8d7 371
6c1362cf
WD		 372 /*
373 * Enable FEC-Lite controller
374 */
375 fec->eth->ecntrl |= 0x00000006;
376
377#if (DEBUG & 0x2)
378 if (fec->xcv_type != SEVENWIRE)
6dedf3d4 379 mpc5xxx_fec_phydump (dev->name);
6c1362cf
WD		 380#endif
381
382 /*
383 * Enable SmartDMA receive task
384 */
385 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
386
387#if (DEBUG & 0x1)
388 printf("mpc5xxx_fec_init... Done \n");
389#endif
390
391 return 1;
392}
393
394/********************************************************************/
395static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
396{
6c1362cf
WD		 397 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
398 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
399
400#if (DEBUG & 0x1)
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
402#endif
403
404 /*
405 * Initialize GPIO pins
406 */
407 if (fec->xcv_type == SEVENWIRE) {
408 /* 10MBit with 7-wire operation */
6c7a1408
WD		 409#if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
412#else /* !CONFIG_TOTAL5200 */
413 /* 7-wire only */
6c1362cf 414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
6c7a1408 415#endif /* CONFIG_TOTAL5200 */
6c1362cf
WD		 416 } else {
417 /* 100MBit with MD operation */
418 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
419 }
420
421 /*
422 * Clear FEC-Lite interrupt event register(IEVENT)
423 */
424 fec->eth->ievent = 0xffffffff;
425
426 /*
427 * Set interrupt mask register
428 */
429 fec->eth->imask = 0x00000000;
430
431 if (fec->xcv_type != SEVENWIRE) {
432 /*
433 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
434 * and do not drop the Preamble.
435 */
436 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
437 }
438
945af8d7
WD		 439 if (fec->xcv_type != SEVENWIRE) {
440 /*
441 * Initialize PHY(LXT971A):
442 *
443 * Generally, on power up, the LXT971A reads its configuration
444 * pins to check for forced operation, If not cofigured for
445 * forced operation, it uses auto-negotiation/parallel detection
446 * to automatically determine line operating conditions.
447 * If the PHY device on the other side of the link supports
448 * auto-negotiation, the LXT971A auto-negotiates with it
449 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
450 * support auto-negotiation, the LXT971A automatically detects
451 * the presence of either link pulses(10Mbps PHY) or Idle
452 * symbols(100Mbps) and sets its operating conditions accordingly.
453 *
454 * When auto-negotiation is controlled by software, the following
455 * steps are recommended.
456 *
457 * Note:
458 * The physical address is dependent on hardware configuration.
459 *
460 */
461 int timeout = 1;
462 uint16 phyStatus;
463
464 /*
465 * Reset PHY, then delay 300ns
466 */
63ff004c 467 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
945af8d7
WD		 468 udelay(1000);
469
470 if (fec->xcv_type == MII10) {
471 /*
472 * Force 10Base-T, FDX operation
473 */
a57106fc 474#if (DEBUG & 0x2)
945af8d7 475 printf("Forcing 10 Mbps ethernet link... ");
a57106fc 476#endif
63ff004c 477 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7 478 /*
63ff004c 479 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
945af8d7 480 */
63ff004c 481 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
945af8d7
WD		 482
483 timeout = 20;
484 do { /* wait for link status to go down */
485 udelay(10000);
486 if ((timeout--) == 0) {
487#if (DEBUG & 0x2)
488 printf("hmmm, should not have waited...");
489#endif
490 break;
491 }
63ff004c 492 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 493#if (DEBUG & 0x2)
494 printf("=");
495#endif
496 } while ((phyStatus & 0x0004)); /* !link up */
497
498 timeout = 1000;
499 do { /* wait for link status to come back up */
500 udelay(10000);
501 if ((timeout--) == 0) {
502 printf("failed. Link is down.\n");
503 break;
504 }
63ff004c 505 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 506#if (DEBUG & 0x2)
507 printf("+");
508#endif
509 } while (!(phyStatus & 0x0004)); /* !link up */
510
ab209d51 511#if (DEBUG & 0x2)
945af8d7 512 printf ("done.\n");
ab209d51 513#endif
945af8d7
WD		 514 } else { /* MII100 */
515 /*
516 * Set the auto-negotiation advertisement register bits
517 */
63ff004c 518 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
945af8d7
WD		 519
520 /*
521 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
522 */
63ff004c 523 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
945af8d7
WD		 524
525 /*
526 * Wait for AN completion
527 */
528 timeout = 5000;
529 do {
530 udelay(1000);
531
532 if ((timeout--) == 0) {
533#if (DEBUG & 0x2)
534 printf("PHY auto neg 0 failed...\n");
535#endif
536 return -1;
537 }
538
63ff004c 539 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
945af8d7
WD		 540#if (DEBUG & 0x2)
541 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
542#endif
543 return -1;
544 }
7e780369 545 } while (!(phyStatus & 0x0004));
945af8d7
WD		 546
547#if (DEBUG & 0x2)
548 printf("PHY auto neg complete! \n");
549#endif
550 }
551
552 }
553
945af8d7 554#if (DEBUG & 0x2)
d4ca31c4 555 if (fec->xcv_type != SEVENWIRE)
63ff004c 556 mpc5xxx_fec_phydump (dev->name);
945af8d7 557#endif
d4ca31c4 558
945af8d7
WD		 559
560#if (DEBUG & 0x1)
6c1362cf 561 printf("mpc5xxx_fec_init_phy... Done \n");
945af8d7
WD		 562#endif
563
013dc8d9 564 return 1;
945af8d7
WD		 565}
566
567/********************************************************************/
568static void mpc5xxx_fec_halt(struct eth_device *dev)
569{
77846748 570#if defined(CONFIG_MPC5200)
945af8d7 571 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
77846748
WD		 572#endif
573 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
945af8d7
WD		 574 int counter = 0xffff;
575
576#if (DEBUG & 0x2)
d4ca31c4 577 if (fec->xcv_type != SEVENWIRE)
6dedf3d4 578 mpc5xxx_fec_phydump (dev->name);
945af8d7
WD		 579#endif
580
945af8d7
WD		 581 /*
582 * mask FEC chip interrupts
583 */
584 fec->eth->imask = 0;
585
586 /*
587 * issue graceful stop command to the FEC transmitter if necessary
588 */
589 fec->eth->x_cntrl |= 0x00000001;
590
591 /*
592 * wait for graceful stop to register
593 */
594 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
595
945af8d7
WD		 596 /*
597 * Disable SmartDMA tasks
598 */
599 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
600 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
601
602#if defined(CONFIG_MPC5200)
603 /*
604 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
605 * done. It doesn't work w/ the current receive task.
606 */
607 sdma->PtdCntrl &= ~0x00000001;
608#endif
609
610 /*
611 * Disable the Ethernet Controller
612 */
613 fec->eth->ecntrl &= 0xfffffffd;
614
615 /*
616 * Clear FIFO status registers
617 */
618 fec->eth->rfifo_status &= 0x00700000;
619 fec->eth->tfifo_status &= 0x00700000;
620
621 fec->eth->reset_cntrl = 0x01000000;
622
623 /*
624 * Issue a reset command to the FEC chip
625 */
626 fec->eth->ecntrl |= 0x1;
627
628 /*
629 * wait at least 16 clock cycles
630 */
631 udelay(10);
632
633#if (DEBUG & 0x3)
634 printf("Ethernet task stopped\n");
635#endif
636}
637
638#if (DEBUG & 0x60)
639/********************************************************************/
640
63ff004c 641static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
945af8d7 642{
d4ca31c4 643 uint16 phyAddr = CONFIG_PHY_ADDR;
945af8d7
WD		 644 uint16 phyStatus;
645
646 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
647 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
648
63ff004c 649 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 650 printf("\nphyStatus: 0x%04x\n", phyStatus);
651 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
652 printf("ievent: 0x%08x\n", fec->eth->ievent);
653 printf("x_status: 0x%08x\n", fec->eth->x_status);
654 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
655
656 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
657 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
658 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
659 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
660 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
661 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
662 }
663}
664
63ff004c 665static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
945af8d7 666{
d4ca31c4 667 uint16 phyAddr = CONFIG_PHY_ADDR;
945af8d7
WD		 668 uint16 phyStatus;
669
670 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
671 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
672
63ff004c 673 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
945af8d7
WD		 674 printf("\nphyStatus: 0x%04x\n", phyStatus);
675 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
676 printf("ievent: 0x%08x\n", fec->eth->ievent);
677 printf("x_status: 0x%08x\n", fec->eth->x_status);
678 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
679
680 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
681 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
682 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
683 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
684 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
685 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
686 }
687}
688#endif /* DEBUG */
689
690/********************************************************************/
691
692static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
693 int data_length)
694{
695 /*
696 * This routine transmits one frame. This routine only accepts
697 * 6-byte Ethernet addresses.
698 */
699 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
151ab83a 700 volatile FEC_TBD *pTbd;
945af8d7
WD		 701
702#if (DEBUG & 0x20)
703 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
63ff004c 704 tfifo_print(dev->name, fec);
945af8d7
WD		 705#endif
706
707 /*
708 * Clear Tx BD ring at first
709 */
710 mpc5xxx_fec_tbd_scrub(fec);
711
712 /*
713 * Check for valid length of data.
714 */
715 if ((data_length > 1500) || (data_length <= 0)) {
716 return -1;
717 }
718
719 /*
720 * Check the number of vacant TxBDs.
721 */
722 if (fec->cleanTbdNum < 1) {
723#if (DEBUG & 0x20)
724 printf("No available TxBDs ...\n");
725#endif
726 return -1;
727 }
728
729 /*
730 * Get the first TxBD to send the mac header
731 */
732 pTbd = &fec->tbdBase[fec->tbdIndex];
733 pTbd->dataLength = data_length;
734 pTbd->dataPointer = (uint32)eth_data;
77846748 735 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
945af8d7
WD		 736 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
737
738#if (DEBUG & 0x100)
739 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
740#endif
741
742 /*
743 * Kick the MII i/f
744 */
745 if (fec->xcv_type != SEVENWIRE) {
746 uint16 phyStatus;
63ff004c 747 miiphy_read(dev->name, 0, 0x1, &phyStatus);
945af8d7
WD		 748 }
749
750 /*
751 * Enable SmartDMA transmit task
752 */
753
754#if (DEBUG & 0x20)
63ff004c 755 tfifo_print(dev->name, fec);
945af8d7
WD		 756#endif
757 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
758#if (DEBUG & 0x20)
63ff004c 759 tfifo_print(dev->name, fec);
945af8d7
WD		 760#endif
761#if (DEBUG & 0x8)
762 printf( "+" );
763#endif
764
765 fec->cleanTbdNum -= 1;
766
767#if (DEBUG & 0x129) && (DEBUG & 0x80000000)
768 printf ("smartDMA ethernet Tx task enabled\n");
769#endif
770 /*
771 * wait until frame is sent .
772 */
773 while (pTbd->status & FEC_TBD_READY) {
774 udelay(10);
775#if (DEBUG & 0x8)
776 printf ("TDB status = %04x\n", pTbd->status);
777#endif
778 }
779
780 return 0;
781}
782
783
784/********************************************************************/
785static int mpc5xxx_fec_recv(struct eth_device *dev)
786{
787 /*
788 * This command pulls one frame from the card
789 */
790 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
151ab83a 791 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
945af8d7 792 unsigned long ievent;
77846748
WD		 793 int frame_length, len = 0;
794 NBUF *frame;
77ddac94 795 uchar buff[FEC_MAX_PKT_SIZE];
945af8d7
WD		 796
797#if (DEBUG & 0x1)
798 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
799#endif
800#if (DEBUG & 0x8)
801 printf( "-" );
802#endif
803
804 /*
805 * Check if any critical events have happened
806 */
807 ievent = fec->eth->ievent;
808 fec->eth->ievent = ievent;
809 if (ievent & 0x20060000) {
810 /* BABT, Rx/Tx FIFO errors */
811 mpc5xxx_fec_halt(dev);
812 mpc5xxx_fec_init(dev, NULL);
813 return 0;
814 }
815 if (ievent & 0x80000000) {
816 /* Heartbeat error */
817 fec->eth->x_cntrl |= 0x00000001;
818 }
819 if (ievent & 0x10000000) {
820 /* Graceful stop complete */
821 if (fec->eth->x_cntrl & 0x00000001) {
822 mpc5xxx_fec_halt(dev);
823 fec->eth->x_cntrl &= ~0x00000001;
824 mpc5xxx_fec_init(dev, NULL);
825 }
826 }
827
77846748
WD		 828 if (!(pRbd->status & FEC_RBD_EMPTY)) {
829 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
830 ((pRbd->dataLength - 4) > 14)) {
945af8d7 831
77846748
WD		 832 /*
833 * Get buffer address and size
834 */
835 frame = (NBUF *)pRbd->dataPointer;
836 frame_length = pRbd->dataLength - 4;
837
838#if (DEBUG & 0x20)
839 {
840 int i;
841 printf("recv data hdr:");
842 for (i = 0; i < 14; i++)
843 printf("%x ", *(frame->head + i));
844 printf("\n");
845 }
945af8d7 846#endif
77846748
WD		 847 /*
848 * Fill the buffer and pass it to upper layers
849 */
850 memcpy(buff, frame->head, 14);
851 memcpy(buff + 14, frame->data, frame_length);
852 NetReceive(buff, frame_length);
853 len = frame_length;
854 }
855 /*
856 * Reset buffer descriptor as empty
857 */
858 mpc5xxx_fec_rbd_clean(fec, pRbd);
945af8d7 859 }
77846748
WD		 860 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
861 return len;
945af8d7
WD		 862}
863
864
865/********************************************************************/
866int mpc5xxx_fec_initialize(bd_t * bis)
867{
868 mpc5xxx_fec_priv *fec;
869 struct eth_device *dev;
12f34241
WD		 870 char *tmp, *end;
871 char env_enetaddr[6];
872 int i;
945af8d7
WD		 873
874 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
875 dev = (struct eth_device *)malloc(sizeof(*dev));
12f34241 876 memset(dev, 0, sizeof *dev);
945af8d7
WD		 877
878 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
879 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
880 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
dd0321f5
WD		 881#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
882 defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
883 defined(CONFIG_JUPITER) || defined(CONFIG_MCC200) || \
884 defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT) || \
885 defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \
886 defined(CONFIG_TQM5200) || defined(CONFIG_UC101) || \
887 defined(CONFIG_V38B)
efa329cb 888# ifndef CONFIG_FEC_10MBIT
945af8d7 889 fec->xcv_type = MII100;
efa329cb 890# else
a57106fc 891 fec->xcv_type = MII10;
efa329cb 892# endif
6c7a1408
WD		 893#elif defined(CONFIG_TOTAL5200)
894 fec->xcv_type = SEVENWIRE;
a57106fc
WD		 895#else
896#error fec->xcv_type not initialized.
945af8d7
WD		 897#endif
898
899 dev->priv = (void *)fec;
900 dev->iobase = MPC5XXX_FEC;
901 dev->init = mpc5xxx_fec_init;
902 dev->halt = mpc5xxx_fec_halt;
903 dev->send = mpc5xxx_fec_send;
904 dev->recv = mpc5xxx_fec_recv;
905
77846748 906 sprintf(dev->name, "FEC ETHERNET");
945af8d7
WD		 907 eth_register(dev);
908
63ff004c
MB		 909#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
910 miiphy_register (dev->name,
911 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
912#endif
913
12f34241
WD		 914 /*
915 * Try to set the mac address now. The fec mac address is
42d1f039 916 * a garbage after reset. When not using fec for booting
12f34241
WD		 917 * the Linux fec driver will try to work with this garbage.
918 */
919 tmp = getenv("ethaddr");
920 if (tmp) {
921 for (i=0; i<6; i++) {
922 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
923 if (tmp)
924 tmp = (*end) ? end+1 : end;
925 }
926 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
927 }
928
6c1362cf 929 mpc5xxx_fec_init_phy(dev, bis);
63ff004c 930
945af8d7
WD		 931 return 1;
932}
933
934/* MII-interface related functions */
935/********************************************************************/
63ff004c 936int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
945af8d7
WD		 937{
938 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
939 uint32 reg; /* convenient holder for the PHY register */
940 uint32 phy; /* convenient holder for the PHY */
941 int timeout = 0xffff;
942
943 /*
944 * reading from any PHY's register is done by properly
945 * programming the FEC's MII data register.
946 */
947 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
948 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
949
950 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
951
952 /*
953 * wait for the related interrupt
954 */
955 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
956
957 if (timeout == 0) {
958#if (DEBUG & 0x2)
959 printf ("Read MDIO failed...\n");
960#endif
961 return -1;
962 }
963
964 /*
965 * clear mii interrupt bit
966 */
967 eth->ievent = 0x00800000;
968
969 /*
970 * it's now safe to read the PHY's register
971 */
972 *retVal = (uint16) eth->mii_data;
973
974 return 0;
975}
976
977/********************************************************************/
63ff004c 978int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
945af8d7
WD		 979{
980 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
981 uint32 reg; /* convenient holder for the PHY register */
982 uint32 phy; /* convenient holder for the PHY */
983 int timeout = 0xffff;
984
985 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
986 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
987
988 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
989 FEC_MII_DATA_TA | phy | reg | data);
990
991 /*
992 * wait for the MII interrupt
993 */
994 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
995
996 if (timeout == 0) {
997#if (DEBUG & 0x2)
998 printf ("Write MDIO failed...\n");
999#endif
1000 return -1;
1001 }
1002
1003 /*
1004 * clear MII interrupt bit
1005 */
1006 eth->ievent = 0x00800000;
1007
1008 return 0;
1009}
1010
1011#if (DEBUG & 0x40)
1012static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1013{
1014 int i;
1015 char c;
1016 unsigned int crc, count;
1017
1018 /*
1019 * crc32 algorithm
1020 */
1021 /*
1022 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1023 */
1024 crc = crc_value;
1025
1026 for (i = len; --i >= 0;) {
1027 c = *string++;
1028 for (count = 0; count < 8; count++) {
1029 if ((c & 0x01) ^ (crc & 0x01)) {
1030 crc >>= 1;
1031 crc = crc ^ 0xedb88320;
1032 } else {
1033 crc >>= 1;
1034 }
1035 c >>= 1;
1036 }
1037 }
1038
1039 /*
1040 * In big endian system, do byte swaping for crc value
1041 */
1042 /**/ return crc;
1043}
1044#endif /* DEBUG */
1045
cbd8a35c 1046#endif /* CONFIG_MPC5xxx_FEC */
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