[J-u-boot.git] / drivers / net / at91_emac.c

/*
 * Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
 * Jens Scharsig (esw@bus-elektronik.de)
 *
 * (C) Copyright 2003
 * Author : Hamid Ikdoumi (Atmel)

 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/io.h>
#ifndef CONFIG_AT91_LEGACY
#include <asm/arch/hardware.h>
#include <asm/arch/at91_emac.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#else
/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
#include <asm/arch-at91/at91rm9200.h>
#include <asm/arch-at91/hardware.h>
#include <asm/arch-at91/at91_emac.h>
#include <asm/arch-at91/at91_pmc.h>
#include <asm/arch-at91/at91_pio.h>
#endif
#include <net.h>
#include <netdev.h>
#include <malloc.h>
#include <miiphy.h>
#include <linux/mii.h>

#undef MII_DEBUG
#undef ET_DEBUG

#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
#error AT91 EMAC supports max 1024 RX buffers. \
	Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
#endif

#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
#define CONFIG_DRIVER_AT91EMAC_PHYADDR	0
#endif

/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
#if (AT91C_MASTER_CLOCK > 80000000)
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_64
#elif (AT91C_MASTER_CLOCK > 40000000)
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_32
#elif (AT91C_MASTER_CLOCK > 20000000)
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_16
#else
	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_8
#endif

#ifdef ET_DEBUG
#define DEBUG_AT91EMAC	1
#else
#define DEBUG_AT91EMAC	0
#endif

#ifdef MII_DEBUG
#define DEBUG_AT91PHY	1
#else
#define DEBUG_AT91PHY	0
#endif

#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
#define VERBOSEP	1
#else
#define VERBOSEP	0
#endif

#define RBF_ADDR      0xfffffffc
#define RBF_OWNER     (1<<0)
#define RBF_WRAP      (1<<1)
#define RBF_BROADCAST (1<<31)
#define RBF_MULTICAST (1<<30)
#define RBF_UNICAST   (1<<29)
#define RBF_EXTERNAL  (1<<28)
#define RBF_UNKNOWN   (1<<27)
#define RBF_SIZE      0x07ff
#define RBF_LOCAL4    (1<<26)
#define RBF_LOCAL3    (1<<25)
#define RBF_LOCAL2    (1<<24)
#define RBF_LOCAL1    (1<<23)

#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
#define RBF_FRAMELEN 0x600

typedef struct {
	unsigned long addr, size;
} rbf_t;

typedef struct {
	rbf_t 		rbfdt[RBF_FRAMEMAX];
	unsigned long	rbindex;
} emac_device;

void at91emac_EnableMDIO(at91_emac_t *at91mac)
{
	/* Mac CTRL reg set for MDIO enable */
	writel(readl(&at91mac->ctl) | AT91_EMAC_CTL_MPE, &at91mac->ctl);
}

void at91emac_DisableMDIO(at91_emac_t *at91mac)
{
	/* Mac CTRL reg set for MDIO disable */
	writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
}

int  at91emac_read(at91_emac_t *at91mac, unsigned char addr,
		unsigned char reg, unsigned short *value)
{
	unsigned long netstat;
	at91emac_EnableMDIO(at91mac);

	writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_R |
		AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
		AT91_EMAC_MAN_PHYA(addr),
		&at91mac->man);

	do {
		netstat = readl(&at91mac->sr);
		debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
	} while (!(netstat & AT91_EMAC_SR_IDLE));

	*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;

	at91emac_DisableMDIO(at91mac);

	debug_cond(DEBUG_AT91PHY,
		"AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);

	return 0;
}

int  at91emac_write(at91_emac_t *at91mac, unsigned char addr,
		unsigned char reg, unsigned short value)
{
	unsigned long netstat;
	debug_cond(DEBUG_AT91PHY,
		"AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);

	at91emac_EnableMDIO(at91mac);

	writel(AT91_EMAC_MAN_HIGH | AT91_EMAC_MAN_RW_W |
		AT91_EMAC_MAN_REGA(reg) | AT91_EMAC_MAN_CODE_802_3 |
		AT91_EMAC_MAN_PHYA(addr) | (value & AT91_EMAC_MAN_DATA_MASK),
		&at91mac->man);

	do {
		netstat = readl(&at91mac->sr);
		debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
	} while (!(netstat & AT91_EMAC_SR_IDLE));

	at91emac_DisableMDIO(at91mac);

	return 0;
}

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)

at91_emac_t *get_emacbase_by_name(const char *devname)
{
	struct eth_device *netdev;

	netdev = eth_get_dev_by_name(devname);
	return (at91_emac_t *) netdev->iobase;
}

int  at91emac_mii_read(const char *devname, unsigned char addr,
		unsigned char reg, unsigned short *value)
{
	at91_emac_t *emac;

	emac = get_emacbase_by_name(devname);
	at91emac_read(emac , addr, reg, value);
	return 0;
}


int  at91emac_mii_write(const char *devname, unsigned char addr,
		unsigned char reg, unsigned short value)
{
	at91_emac_t *emac;

	emac = get_emacbase_by_name(devname);
	at91emac_write(emac, addr, reg, value);
	return 0;
}

#endif

static int at91emac_phy_reset(struct eth_device *netdev)
{
	int i;
	u16 status, adv;
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;

	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
		MII_ADVERTISE, adv);
	debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
		(BMCR_ANENABLE | BMCR_ANRESTART));

	for (i = 0; i < 30000; i++) {
		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
			MII_BMSR, &status);
		if (status & BMSR_ANEGCOMPLETE)
			break;
		udelay(100);
	}

	if (status & BMSR_ANEGCOMPLETE) {
		debug_cond(VERBOSEP,
			"%s: Autonegotiation complete\n", netdev->name);
	} else {
		printf("%s: Autonegotiation timed out (status=0x%04x)\n",
		       netdev->name, status);
		return -1;
	}
	return 0;
}

static int at91emac_phy_init(struct eth_device *netdev)
{
	u16 phy_id, status, adv, lpa;
	int media, speed, duplex;
	int i;
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;

	/* Check if the PHY is up to snuff... */
	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
		MII_PHYSID1, &phy_id);
	if (phy_id == 0xffff) {
		printf("%s: No PHY present\n", netdev->name);
		return -1;
	}

	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
		MII_BMSR, &status);

	if (!(status & BMSR_LSTATUS)) {
		/* Try to re-negotiate if we don't have link already. */
		if (at91emac_phy_reset(netdev))
			return -2;

		for (i = 0; i < 100000 / 100; i++) {
			at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
				MII_BMSR, &status);
			if (status & BMSR_LSTATUS)
				break;
			udelay(100);
		}
	}
	if (!(status & BMSR_LSTATUS)) {
		debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
		return -3;
	} else {
		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
			MII_ADVERTISE, &adv);
		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
			MII_LPA, &lpa);
		media = mii_nway_result(lpa & adv);
		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
			 ? 1 : 0);
		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
		debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
		       netdev->name,
		       speed ? "100" : "10",
		       duplex ? "full" : "half");
	}
	return 0;
}

int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
{
	unsigned short stat1;

	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);

	if (!(stat1 & BMSR_LSTATUS))	/* link status up? */
		return -1;

	if (stat1 & BMSR_100FULL) {
		/*set Emac for 100BaseTX and Full Duplex  */
		writel(readl(&emac->cfg) |
			AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD,
			&emac->cfg);
		return 0;
	}

	if (stat1 & BMSR_10FULL) {
		/*set MII for 10BaseT and Full Duplex  */
		writel((readl(&emac->cfg) &
			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
			) | AT91_EMAC_CFG_FD,
			&emac->cfg);
		return 0;
	}

	if (stat1 & BMSR_100HALF) {
		/*set MII for 100BaseTX and Half Duplex  */
		writel((readl(&emac->cfg) &
			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)
			) | AT91_EMAC_CFG_SPD,
			&emac->cfg);
		return 0;
	}

	if (stat1 & BMSR_10HALF) {
		/*set MII for 10BaseT and Half Duplex  */
		writel((readl(&emac->cfg) &
			~(AT91_EMAC_CFG_SPD | AT91_EMAC_CFG_FD)),
			&emac->cfg);
		return 0;
	}
	return 0;
}

static int at91emac_init(struct eth_device *netdev, bd_t *bd)
{
	int i;
	u32 value;
	emac_device *dev;
	at91_emac_t *emac;
	at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO;
	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;

	emac = (at91_emac_t *) netdev->iobase;
	dev = (emac_device *) netdev->priv;

	/* PIO Disable Register */
	value =	ATMEL_PMX_AA_EMDIO |	ATMEL_PMX_AA_EMDC |
		ATMEL_PMX_AA_ERXER |	ATMEL_PMX_AA_ERX1 |
		ATMEL_PMX_AA_ERX0 |	ATMEL_PMX_AA_ECRS |
		ATMEL_PMX_AA_ETX1 |	ATMEL_PMX_AA_ETX0 |
		ATMEL_PMX_AA_ETXEN |	ATMEL_PMX_AA_EREFCK;

	writel(value, &pio->pioa.pdr);
	writel(value, &pio->pioa.asr);

#ifdef CONFIG_RMII
	value = ATMEL_PMX_BA_ERXCK;
#else
	value = ATMEL_PMX_BA_ERXCK |	ATMEL_PMX_BA_ECOL |
		ATMEL_PMX_BA_ERXDV |	ATMEL_PMX_BA_ERX3 |
		ATMEL_PMX_BA_ERX2 |	ATMEL_PMX_BA_ETXER |
		ATMEL_PMX_BA_ETX3 |	ATMEL_PMX_BA_ETX2;
#endif
	writel(value, &pio->piob.pdr);
	writel(value, &pio->piob.bsr);

	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
	writel(readl(&emac->ctl) | AT91_EMAC_CTL_CSR, &emac->ctl);

	/* Init Ethernet buffers */
	for (i = 0; i < RBF_FRAMEMAX; i++) {
		dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
		dev->rbfdt[i].size = 0;
	}
	dev->rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
	dev->rbindex = 0;
	writel((u32) &(dev->rbfdt[0]), &emac->rbqp);

	writel(readl(&emac->rsr) &
		~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA),
		&emac->rsr);

	value = AT91_EMAC_CFG_CAF |	AT91_EMAC_CFG_NBC |
		HCLK_DIV;
#ifdef CONFIG_RMII
	value |= AT91_EMAC_CFG_RMII;
#endif
	writel(value, &emac->cfg);

	writel(readl(&emac->ctl) | AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE,
		&emac->ctl);

	if (!at91emac_phy_init(netdev)) {
		at91emac_UpdateLinkSpeed(emac);
		return 0;
	}
	return -1;
}

static void at91emac_halt(struct eth_device *netdev)
{
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;
	writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE | AT91_EMAC_CTL_RE),
		&emac->ctl);
	debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
}

static int at91emac_send(struct eth_device *netdev, volatile void *packet,
		     int length)
{
	at91_emac_t *emac;

	emac = (at91_emac_t *) netdev->iobase;

	while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
		;
	writel((u32) packet, &emac->tar);
	writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
	while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
		;
	debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
	writel(readl(&emac->tsr) | AT91_EMAC_TSR_COMP, &emac->tsr);
	return 0;
}

static int at91emac_recv(struct eth_device *netdev)
{
	emac_device *dev;
	at91_emac_t *emac;
	rbf_t *rbfp;
	int size;

	emac = (at91_emac_t *) netdev->iobase;
	dev = (emac_device *) netdev->priv;

	rbfp = &dev->rbfdt[dev->rbindex];
	while (rbfp->addr & RBF_OWNER)	{
		size = rbfp->size & RBF_SIZE;
		NetReceive(NetRxPackets[dev->rbindex], size);

		debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
			dev->rbindex, size, rbfp->addr);

		rbfp->addr &= ~RBF_OWNER;
		rbfp->size = 0;
		if (dev->rbindex < (RBF_FRAMEMAX-1))
			dev->rbindex++;
		else
			dev->rbindex = 0;

		rbfp = &(dev->rbfdt[dev->rbindex]);
		if (!(rbfp->addr & RBF_OWNER))
			writel(readl(&emac->rsr) | AT91_EMAC_RSR_REC,
				&emac->rsr);
	}

	if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
		/* EMAC silicon bug 41.3.1 workaround 1 */
		writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
		writel(readl(&emac->ctl) | AT91_EMAC_CTL_RE, &emac->ctl);
		dev->rbindex = 0;
		printf("%s: reset receiver (EMAC dead lock bug)\n",
			netdev->name);
	}
	return 0;
}

static int at91emac_write_hwaddr(struct eth_device *netdev)
{
	at91_emac_t *emac;
	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
	emac = (at91_emac_t *) netdev->iobase;

	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
	debug_cond(DEBUG_AT91EMAC,
		"init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
		netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
		netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
	writel( (netdev->enetaddr[0] | netdev->enetaddr[1] << 8 |
			netdev->enetaddr[2] << 16 | netdev->enetaddr[3] << 24),
			&emac->sa2l);
	writel((netdev->enetaddr[4] | netdev->enetaddr[5] << 8), &emac->sa2h);
	debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
		readl(&emac->sa2h), readl(&emac->sa2l));
	return 0;
}

int at91emac_register(bd_t *bis, unsigned long iobase)
{
	emac_device *emac;
	emac_device *emacfix;
	struct eth_device *dev;

	if (iobase == 0)
		iobase = ATMEL_BASE_EMAC;
	emac = malloc(sizeof(*emac)+512);
	if (emac == NULL)
		return -1;
	dev = malloc(sizeof(*dev));
	if (dev == NULL) {
		free(emac);
		return -1;
	}
	/* alignment as per Errata (64 bytes) is insufficient! */
	emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
	memset(emacfix, 0, sizeof(emac_device));

	memset(dev, 0, sizeof(*dev));
	sprintf(dev->name, "emac");
	dev->iobase = iobase;
	dev->priv = emacfix;
	dev->init = at91emac_init;
	dev->halt = at91emac_halt;
	dev->send = at91emac_send;
	dev->recv = at91emac_recv;
	dev->write_hwaddr = at91emac_write_hwaddr;

	eth_register(dev);

#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
	miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
#endif
	return 1;
}
Commit	Line	Data
c041e9d2 JS	1	/*
	2	* Copyright (C) 2009 BuS Elektronik GmbH & Co. KG
	3	* Jens Scharsig (esw@bus-elektronik.de)
	4	*
	5	* (C) Copyright 2003
	6	* Author : Hamid Ikdoumi (Atmel)
	7
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <asm/io.h>
	29	#ifndef CONFIG_AT91_LEGACY
	30	#include <asm/arch/hardware.h>
	31	#include <asm/arch/at91_emac.h>
	32	#include <asm/arch/at91_pmc.h>
	33	#include <asm/arch/at91_pio.h>
	34	#else
	35	/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
	36	#include <asm/arch-at91/at91rm9200.h>
	37	#include <asm/arch-at91/hardware.h>
	38	#include <asm/arch-at91/at91_emac.h>
	39	#include <asm/arch-at91/at91_pmc.h>
	40	#include <asm/arch-at91/at91_pio.h>
	41	#endif
	42	#include <net.h>
	43	#include <netdev.h>
	44	#include <malloc.h>
	45	#include <miiphy.h>
	46	#include <linux/mii.h>
	47
	48	#undef MII_DEBUG
	49	#undef ET_DEBUG
	50
	51	#if (CONFIG_SYS_RX_ETH_BUFFER > 1024)
	52	#error AT91 EMAC supports max 1024 RX buffers. \
	53	Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
	54	#endif
	55
836cd453 EB	56	#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
	57	#define CONFIG_DRIVER_AT91EMAC_PHYADDR 0
	58	#endif
	59
c041e9d2 JS	60	/* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
	61	#if (AT91C_MASTER_CLOCK > 80000000)
	62	#define HCLK_DIV AT91_EMAC_CFG_MCLK_64
	63	#elif (AT91C_MASTER_CLOCK > 40000000)
	64	#define HCLK_DIV AT91_EMAC_CFG_MCLK_32
	65	#elif (AT91C_MASTER_CLOCK > 20000000)
	66	#define HCLK_DIV AT91_EMAC_CFG_MCLK_16
	67	#else
	68	#define HCLK_DIV AT91_EMAC_CFG_MCLK_8
	69	#endif
	70
	71	#ifdef ET_DEBUG
f4962066	72	#define DEBUG_AT91EMAC 1
c041e9d2	73	#else
f4962066	74	#define DEBUG_AT91EMAC 0
c041e9d2 JS	75	#endif
	76
	77	#ifdef MII_DEBUG
f4962066	78	#define DEBUG_AT91PHY 1
c041e9d2	79	#else
f4962066	80	#define DEBUG_AT91PHY 0
c041e9d2 JS	81	#endif
	82
	83	#ifndef CONFIG_DRIVER_AT91EMAC_QUIET
f4962066	84	#define VERBOSEP 1
c041e9d2	85	#else
f4962066	86	#define VERBOSEP 0
c041e9d2 JS	87	#endif
	88
	89	#define RBF_ADDR 0xfffffffc
	90	#define RBF_OWNER (1<<0)
	91	#define RBF_WRAP (1<<1)
	92	#define RBF_BROADCAST (1<<31)
	93	#define RBF_MULTICAST (1<<30)
	94	#define RBF_UNICAST (1<<29)
	95	#define RBF_EXTERNAL (1<<28)
6052cbab	96	#define RBF_UNKNOWN (1<<27)
c041e9d2 JS	97	#define RBF_SIZE 0x07ff
	98	#define RBF_LOCAL4 (1<<26)
	99	#define RBF_LOCAL3 (1<<25)
	100	#define RBF_LOCAL2 (1<<24)
	101	#define RBF_LOCAL1 (1<<23)
	102
	103	#define RBF_FRAMEMAX CONFIG_SYS_RX_ETH_BUFFER
	104	#define RBF_FRAMELEN 0x600
	105
	106	typedef struct {
	107	unsigned long addr, size;
	108	} rbf_t;
	109
	110	typedef struct {
	111	rbf_t rbfdt[RBF_FRAMEMAX];
	112	unsigned long rbindex;
	113	} emac_device;
	114
	115	void at91emac_EnableMDIO(at91_emac_t *at91mac)
	116	{
	117	/* Mac CTRL reg set for MDIO enable */
	118	writel(readl(&at91mac->ctl) \| AT91_EMAC_CTL_MPE, &at91mac->ctl);
	119	}
	120
	121	void at91emac_DisableMDIO(at91_emac_t *at91mac)
	122	{
	123	/* Mac CTRL reg set for MDIO disable */
	124	writel(readl(&at91mac->ctl) & ~AT91_EMAC_CTL_MPE, &at91mac->ctl);
	125	}
	126
	127	int at91emac_read(at91_emac_t *at91mac, unsigned char addr,
	128	unsigned char reg, unsigned short *value)
	129	{
38bda019	130	unsigned long netstat;
c041e9d2 JS	131	at91emac_EnableMDIO(at91mac);
	132
	133	writel(AT91_EMAC_MAN_HIGH \| AT91_EMAC_MAN_RW_R \|
	134	AT91_EMAC_MAN_REGA(reg) \| AT91_EMAC_MAN_CODE_802_3 \|
	135	AT91_EMAC_MAN_PHYA(addr),
	136	&at91mac->man);
38bda019 AB	137
	138	do {
	139	netstat = readl(&at91mac->sr);
f4962066	140	debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
38bda019 AB	141	} while (!(netstat & AT91_EMAC_SR_IDLE));
38bda019 AB	142
c041e9d2 JS	143	*value = readl(&at91mac->man) & AT91_EMAC_MAN_DATA_MASK;
	144
	145	at91emac_DisableMDIO(at91mac);
	146
f4962066 WD	147	debug_cond(DEBUG_AT91PHY,
f4962066 WD	148	"AT91PHY read %p REG(%d)=%x\n", at91mac, reg, *value);
c041e9d2 JS	149
	150	return 0;
	151	}
	152
	153	int at91emac_write(at91_emac_t *at91mac, unsigned char addr,
	154	unsigned char reg, unsigned short value)
	155	{
38bda019	156	unsigned long netstat;
f4962066 WD	157	debug_cond(DEBUG_AT91PHY,
f4962066 WD	158	"AT91PHY write %p REG(%d)=%p\n", at91mac, reg, &value);
c041e9d2 JS	159
	160	at91emac_EnableMDIO(at91mac);
	161
	162	writel(AT91_EMAC_MAN_HIGH \| AT91_EMAC_MAN_RW_W \|
	163	AT91_EMAC_MAN_REGA(reg) \| AT91_EMAC_MAN_CODE_802_3 \|
	164	AT91_EMAC_MAN_PHYA(addr) \| (value & AT91_EMAC_MAN_DATA_MASK),
	165	&at91mac->man);
38bda019 AB	166
	167	do {
	168	netstat = readl(&at91mac->sr);
f4962066	169	debug_cond(DEBUG_AT91PHY, "poll SR %08lx\n", netstat);
38bda019	170	} while (!(netstat & AT91_EMAC_SR_IDLE));
c041e9d2 JS	171
c041e9d2 JS	172	at91emac_DisableMDIO(at91mac);
38bda019	173
c041e9d2 JS	174	return 0;
	175	}
	176
	177	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	178
d7fb9bcf	179	at91_emac_t get_emacbase_by_name(const char devname)
c041e9d2 JS	180	{
	181	struct eth_device *netdev;
	182
	183	netdev = eth_get_dev_by_name(devname);
	184	return (at91_emac_t *) netdev->iobase;
	185	}
	186
5700bb63	187	int at91emac_mii_read(const char *devname, unsigned char addr,
c041e9d2 JS	188	unsigned char reg, unsigned short *value)
	189	{
	190	at91_emac_t *emac;
	191
	192	emac = get_emacbase_by_name(devname);
	193	at91emac_read(emac , addr, reg, value);
	194	return 0;
	195	}
	196
	197
5700bb63	198	int at91emac_mii_write(const char *devname, unsigned char addr,
c041e9d2 JS	199	unsigned char reg, unsigned short value)
	200	{
	201	at91_emac_t *emac;
	202
	203	emac = get_emacbase_by_name(devname);
	204	at91emac_write(emac, addr, reg, value);
	205	return 0;
	206	}
	207
	208	#endif
	209
	210	static int at91emac_phy_reset(struct eth_device *netdev)
	211	{
	212	int i;
	213	u16 status, adv;
	214	at91_emac_t *emac;
	215
	216	emac = (at91_emac_t *) netdev->iobase;
	217
	218	adv = ADVERTISE_CSMA \| ADVERTISE_ALL;
836cd453 EB	219	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	220	MII_ADVERTISE, adv);
f4962066	221	debug_cond(VERBOSEP, "%s: Starting autonegotiation...\n", netdev->name);
836cd453 EB	222	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
836cd453 EB	223	(BMCR_ANENABLE \| BMCR_ANRESTART));
c041e9d2	224
e63ac4cf	225	for (i = 0; i < 30000; i++) {
836cd453 EB	226	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	227	MII_BMSR, &status);
c041e9d2 JS	228	if (status & BMSR_ANEGCOMPLETE)
	229	break;
	230	udelay(100);
	231	}
	232
	233	if (status & BMSR_ANEGCOMPLETE) {
f4962066 WD	234	debug_cond(VERBOSEP,
f4962066 WD	235	"%s: Autonegotiation complete\n", netdev->name);
c041e9d2 JS	236	} else {
	237	printf("%s: Autonegotiation timed out (status=0x%04x)\n",
	238	netdev->name, status);
77179067	239	return -1;
c041e9d2 JS	240	}
	241	return 0;
	242	}
	243
	244	static int at91emac_phy_init(struct eth_device *netdev)
	245	{
	246	u16 phy_id, status, adv, lpa;
	247	int media, speed, duplex;
	248	int i;
	249	at91_emac_t *emac;
	250
	251	emac = (at91_emac_t *) netdev->iobase;
	252
	253	/* Check if the PHY is up to snuff... */
836cd453 EB	254	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	255	MII_PHYSID1, &phy_id);
c041e9d2 JS	256	if (phy_id == 0xffff) {
c041e9d2 JS	257	printf("%s: No PHY present\n", netdev->name);
77179067	258	return -1;
c041e9d2 JS	259	}
c041e9d2 JS	260
836cd453 EB	261	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	262	MII_BMSR, &status);
c041e9d2 JS	263
	264	if (!(status & BMSR_LSTATUS)) {
	265	/* Try to re-negotiate if we don't have link already. */
	266	if (at91emac_phy_reset(netdev))
77179067	267	return -2;
c041e9d2 JS	268
c041e9d2 JS	269	for (i = 0; i < 100000 / 100; i++) {
836cd453 EB	270	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
836cd453 EB	271	MII_BMSR, &status);
c041e9d2 JS	272	if (status & BMSR_LSTATUS)
	273	break;
	274	udelay(100);
	275	}
	276	}
	277	if (!(status & BMSR_LSTATUS)) {
f4962066	278	debug_cond(VERBOSEP, "%s: link down\n", netdev->name);
77179067	279	return -3;
c041e9d2	280	} else {
836cd453 EB	281	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
	282	MII_ADVERTISE, &adv);
	283	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
	284	MII_LPA, &lpa);
c041e9d2 JS	285	media = mii_nway_result(lpa & adv);
	286	speed = (media & (ADVERTISE_100FULL \| ADVERTISE_100HALF)
	287	? 1 : 0);
	288	duplex = (media & ADVERTISE_FULL) ? 1 : 0;
f4962066	289	debug_cond(VERBOSEP, "%s: link up, %sMbps %s-duplex\n",
c041e9d2 JS	290	netdev->name,
	291	speed ? "100" : "10",
	292	duplex ? "full" : "half");
	293	}
	294	return 0;
	295	}
	296
	297	int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
	298	{
	299	unsigned short stat1;
	300
836cd453	301	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
c041e9d2 JS	302
c041e9d2 JS	303	if (!(stat1 & BMSR_LSTATUS)) /* link status up? */
77179067	304	return -1;
c041e9d2 JS	305
	306	if (stat1 & BMSR_100FULL) {
	307	/set Emac for 100BaseTX and Full Duplex /
	308	writel(readl(&emac->cfg) \|
	309	AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD,
	310	&emac->cfg);
	311	return 0;
	312	}
	313
	314	if (stat1 & BMSR_10FULL) {
	315	/set MII for 10BaseT and Full Duplex /
	316	writel((readl(&emac->cfg) &
	317	~(AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD)
	318	) \| AT91_EMAC_CFG_FD,
	319	&emac->cfg);
	320	return 0;
	321	}
	322
	323	if (stat1 & BMSR_100HALF) {
	324	/set MII for 100BaseTX and Half Duplex /
	325	writel((readl(&emac->cfg) &
	326	~(AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD)
	327	) \| AT91_EMAC_CFG_SPD,
	328	&emac->cfg);
	329	return 0;
	330	}
	331
	332	if (stat1 & BMSR_10HALF) {
	333	/set MII for 10BaseT and Half Duplex /
	334	writel((readl(&emac->cfg) &
	335	~(AT91_EMAC_CFG_SPD \| AT91_EMAC_CFG_FD)),
	336	&emac->cfg);
	337	return 0;
	338	}
77179067	339	return 0;
c041e9d2 JS	340	}
	341
	342	static int at91emac_init(struct eth_device netdev, bd_t bd)
	343	{
	344	int i;
	345	u32 value;
	346	emac_device *dev;
	347	at91_emac_t *emac;
80733994 JS	348	at91_pio_t pio = (at91_pio_t ) ATMEL_BASE_PIO;
80733994 JS	349	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
c041e9d2 JS	350
	351	emac = (at91_emac_t *) netdev->iobase;
	352	dev = (emac_device *) netdev->priv;
	353
	354	/* PIO Disable Register */
80733994 JS	355	value = ATMEL_PMX_AA_EMDIO \| ATMEL_PMX_AA_EMDC \|
	356	ATMEL_PMX_AA_ERXER \| ATMEL_PMX_AA_ERX1 \|
	357	ATMEL_PMX_AA_ERX0 \| ATMEL_PMX_AA_ECRS \|
	358	ATMEL_PMX_AA_ETX1 \| ATMEL_PMX_AA_ETX0 \|
	359	ATMEL_PMX_AA_ETXEN \| ATMEL_PMX_AA_EREFCK;
c041e9d2 JS	360
	361	writel(value, &pio->pioa.pdr);
	362	writel(value, &pio->pioa.asr);
	363
	364	#ifdef CONFIG_RMII
80733994	365	value = ATMEL_PMX_BA_ERXCK;
c041e9d2	366	#else
80733994 JS	367	value = ATMEL_PMX_BA_ERXCK \| ATMEL_PMX_BA_ECOL \|
	368	ATMEL_PMX_BA_ERXDV \| ATMEL_PMX_BA_ERX3 \|
	369	ATMEL_PMX_BA_ERX2 \| ATMEL_PMX_BA_ETXER \|
	370	ATMEL_PMX_BA_ETX3 \| ATMEL_PMX_BA_ETX2;
c041e9d2 JS	371	#endif
	372	writel(value, &pio->piob.pdr);
	373	writel(value, &pio->piob.bsr);
	374
80733994	375	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
c041e9d2 JS	376	writel(readl(&emac->ctl) \| AT91_EMAC_CTL_CSR, &emac->ctl);
c041e9d2 JS	377
c041e9d2 JS	378	/* Init Ethernet buffers */
	379	for (i = 0; i < RBF_FRAMEMAX; i++) {
	380	dev->rbfdt[i].addr = (unsigned long) NetRxPackets[i];
	381	dev->rbfdt[i].size = 0;
	382	}
	383	dev->rbfdt[RBF_FRAMEMAX - 1].addr \|= RBF_WRAP;
	384	dev->rbindex = 0;
	385	writel((u32) &(dev->rbfdt[0]), &emac->rbqp);
	386
	387	writel(readl(&emac->rsr) &
	388	~(AT91_EMAC_RSR_OVR \| AT91_EMAC_RSR_REC \| AT91_EMAC_RSR_BNA),
	389	&emac->rsr);
	390
	391	value = AT91_EMAC_CFG_CAF \| AT91_EMAC_CFG_NBC \|
	392	HCLK_DIV;
	393	#ifdef CONFIG_RMII
836cd453	394	value \|= AT91_EMAC_CFG_RMII;
c041e9d2 JS	395	#endif
	396	writel(value, &emac->cfg);
	397
	398	writel(readl(&emac->ctl) \| AT91_EMAC_CTL_TE \| AT91_EMAC_CTL_RE,
	399	&emac->ctl);
	400
	401	if (!at91emac_phy_init(netdev)) {
	402	at91emac_UpdateLinkSpeed(emac);
	403	return 0;
	404	}
77179067	405	return -1;
c041e9d2 JS	406	}
	407
	408	static void at91emac_halt(struct eth_device *netdev)
	409	{
	410	at91_emac_t *emac;
	411
	412	emac = (at91_emac_t *) netdev->iobase;
	413	writel(readl(&emac->ctl) & ~(AT91_EMAC_CTL_TE \| AT91_EMAC_CTL_RE),
	414	&emac->ctl);
f4962066	415	debug_cond(DEBUG_AT91EMAC, "halt MAC\n");
c041e9d2 JS	416	}
	417
	418	static int at91emac_send(struct eth_device netdev, volatile void packet,
	419	int length)
	420	{
	421	at91_emac_t *emac;
	422
	423	emac = (at91_emac_t *) netdev->iobase;
	424
	425	while (!(readl(&emac->tsr) & AT91_EMAC_TSR_BNQ))
	426	;
	427	writel((u32) packet, &emac->tar);
	428	writel(AT91_EMAC_TCR_LEN(length), &emac->tcr);
	429	while (AT91_EMAC_TCR_LEN(readl(&emac->tcr)))
	430	;
f4962066	431	debug_cond(DEBUG_AT91EMAC, "Send %d\n", length);
c041e9d2 JS	432	writel(readl(&emac->tsr) \| AT91_EMAC_TSR_COMP, &emac->tsr);
	433	return 0;
	434	}
	435
	436	static int at91emac_recv(struct eth_device *netdev)
	437	{
	438	emac_device *dev;
	439	at91_emac_t *emac;
	440	rbf_t *rbfp;
	441	int size;
	442
	443	emac = (at91_emac_t *) netdev->iobase;
	444	dev = (emac_device *) netdev->priv;
	445
	446	rbfp = &dev->rbfdt[dev->rbindex];
	447	while (rbfp->addr & RBF_OWNER) {
	448	size = rbfp->size & RBF_SIZE;
	449	NetReceive(NetRxPackets[dev->rbindex], size);
	450
f4962066	451	debug_cond(DEBUG_AT91EMAC, "Recv[%ld]: %d bytes @ %lx\n",
c041e9d2 JS	452	dev->rbindex, size, rbfp->addr);
	453
	454	rbfp->addr &= ~RBF_OWNER;
	455	rbfp->size = 0;
	456	if (dev->rbindex < (RBF_FRAMEMAX-1))
	457	dev->rbindex++;
	458	else
	459	dev->rbindex = 0;
	460
	461	rbfp = &(dev->rbfdt[dev->rbindex]);
	462	if (!(rbfp->addr & RBF_OWNER))
	463	writel(readl(&emac->rsr) \| AT91_EMAC_RSR_REC,
	464	&emac->rsr);
	465	}
	466
	467	if (readl(&emac->isr) & AT91_EMAC_IxR_RBNA) {
	468	/* EMAC silicon bug 41.3.1 workaround 1 */
	469	writel(readl(&emac->ctl) & ~AT91_EMAC_CTL_RE, &emac->ctl);
	470	writel(readl(&emac->ctl) \| AT91_EMAC_CTL_RE, &emac->ctl);
	471	dev->rbindex = 0;
	472	printf("%s: reset receiver (EMAC dead lock bug)\n",
	473	netdev->name);
	474	}
	475	return 0;
	476	}
	477
409943a9 EB	478	static int at91emac_write_hwaddr(struct eth_device *netdev)
409943a9 EB	479	{
409943a9	480	at91_emac_t *emac;
80733994	481	at91_pmc_t pmc = (at91_pmc_t ) ATMEL_BASE_PMC;
409943a9	482	emac = (at91_emac_t *) netdev->iobase;
409943a9	483
80733994	484	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
f4962066 WD	485	debug_cond(DEBUG_AT91EMAC,
f4962066 WD	486	"init MAC-ADDR %02x:%02x:%02x:%02x:%02x:%02x\n",
2321bfe4 AB	487	netdev->enetaddr[5], netdev->enetaddr[4], netdev->enetaddr[3],
	488	netdev->enetaddr[2], netdev->enetaddr[1], netdev->enetaddr[0]);
	489	writel( (netdev->enetaddr[0] \| netdev->enetaddr[1] << 8 \|
	490	netdev->enetaddr[2] << 16 \| netdev->enetaddr[3] << 24),
	491	&emac->sa2l);
	492	writel((netdev->enetaddr[4] \| netdev->enetaddr[5] << 8), &emac->sa2h);
f4962066	493	debug_cond(DEBUG_AT91EMAC, "init MAC-ADDR %x%x\n",
409943a9 EB	494	readl(&emac->sa2h), readl(&emac->sa2l));
	495	return 0;
	496	}
	497
c041e9d2 JS	498	int at91emac_register(bd_t *bis, unsigned long iobase)
	499	{
	500	emac_device *emac;
	501	emac_device *emacfix;
	502	struct eth_device *dev;
	503
	504	if (iobase == 0)
80733994	505	iobase = ATMEL_BASE_EMAC;
c041e9d2 JS	506	emac = malloc(sizeof(*emac)+512);
c041e9d2 JS	507	if (emac == NULL)
77179067	508	return -1;
c041e9d2 JS	509	dev = malloc(sizeof(*dev));
	510	if (dev == NULL) {
	511	free(emac);
77179067	512	return -1;
c041e9d2 JS	513	}
	514	/* alignment as per Errata (64 bytes) is insufficient! */
	515	emacfix = (emac_device *) (((unsigned long) emac + 0x1ff) & 0xFFFFFE00);
	516	memset(emacfix, 0, sizeof(emac_device));
	517
	518	memset(dev, 0, sizeof(*dev));
4b8d77bb	519	sprintf(dev->name, "emac");
c041e9d2 JS	520	dev->iobase = iobase;
	521	dev->priv = emacfix;
	522	dev->init = at91emac_init;
	523	dev->halt = at91emac_halt;
	524	dev->send = at91emac_send;
	525	dev->recv = at91emac_recv;
409943a9	526	dev->write_hwaddr = at91emac_write_hwaddr;
c041e9d2 JS	527
	528	eth_register(dev);
	529
	530	#if defined(CONFIG_MII) \|\| defined(CONFIG_CMD_MII)
	531	miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write);
	532	#endif
	533	return 1;
	534	}