common: Drop init.h from common header
[J-u-boot.git] / board / freescale / corenet_ds / ddr.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0
d1712369 2/*
3dbd5d7d 3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
d1712369
KG
4 */
5
6#include <common.h>
7#include <i2c.h>
28a96671 8#include <hwconfig.h>
691d719d 9#include <init.h>
2189d5f1 10#include <vsprintf.h>
28a96671 11#include <asm/mmu.h>
5614e71b
YS
12#include <fsl_ddr_sdram.h>
13#include <fsl_ddr_dimm_params.h>
28a96671
YS
14#include <asm/fsl_law.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
28a96671
YS
18
19/*
20 * Fixed sdram init -- doesn't use serial presence detect.
21 */
22extern fixed_ddr_parm_t fixed_ddr_parm_0[];
51370d56 23#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
28a96671
YS
24extern fixed_ddr_parm_t fixed_ddr_parm_1[];
25#endif
26
27phys_size_t fixed_sdram(void)
28{
29 int i;
28a96671
YS
30 char buf[32];
31 fsl_ddr_cfg_regs_t ddr_cfg_regs;
32 phys_size_t ddr_size;
33 unsigned int lawbar1_target_id;
5cfbc458
KG
34 ulong ddr_freq, ddr_freq_mhz;
35
36 ddr_freq = get_ddr_freq(0);
37 ddr_freq_mhz = ddr_freq / 1000000;
28a96671 38
28a96671 39 printf("Configuring DDR for %s MT/s data rate\n",
5cfbc458 40 strmhz(buf, ddr_freq));
28a96671
YS
41
42 for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
5cfbc458
KG
43 if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
44 (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
28a96671
YS
45 memcpy(&ddr_cfg_regs,
46 fixed_ddr_parm_0[i].ddr_settings,
47 sizeof(ddr_cfg_regs));
48 break;
49 }
50 }
51
52 if (fixed_ddr_parm_0[i].max_freq == 0)
53 panic("Unsupported DDR data rate %s MT/s data rate\n",
5cfbc458 54 strmhz(buf, ddr_freq));
28a96671
YS
55
56 ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
6b06d7dc 57 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
c63e1370 58 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
28a96671 59
51370d56 60#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
28a96671
YS
61 memcpy(&ddr_cfg_regs,
62 fixed_ddr_parm_1[i].ddr_settings,
63 sizeof(ddr_cfg_regs));
6b06d7dc 64 ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
c63e1370 65 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1, 0);
28a96671
YS
66#endif
67
68 /*
69 * setup laws for DDR. If not interleaving, presuming half memory on
70 * DDR1 and the other half on DDR2
71 */
72 if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
73 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
74 ddr_size,
75 LAW_TRGT_IF_DDR_INTRLV) < 0) {
76 printf("ERROR setting Local Access Windows for DDR\n");
77 return 0;
78 }
79 } else {
51370d56 80#if (CONFIG_SYS_NUM_DDR_CTLRS == 2)
28a96671
YS
81 /* We require both controllers have identical DIMMs */
82 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
83 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
84 ddr_size / 2,
85 lawbar1_target_id) < 0) {
86 printf("ERROR setting Local Access Windows for DDR\n");
87 return 0;
88 }
89 lawbar1_target_id = LAW_TRGT_IF_DDR_2;
90 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
91 ddr_size / 2,
92 lawbar1_target_id) < 0) {
93 printf("ERROR setting Local Access Windows for DDR\n");
94 return 0;
95 }
96#else
97 lawbar1_target_id = LAW_TRGT_IF_DDR_1;
98 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
99 ddr_size,
100 lawbar1_target_id) < 0) {
101 printf("ERROR setting Local Access Windows for DDR\n");
102 return 0;
103 }
104#endif
105 }
106 return ddr_size;
107}
d1712369 108
712cf7ab 109struct board_specific_parameters {
d1712369 110 u32 n_ranks;
712cf7ab 111 u32 datarate_mhz_high;
d1712369 112 u32 clk_adjust;
6b06d7dc 113 u32 wrlvl_start;
d1712369
KG
114 u32 cpo;
115 u32 write_data_delay;
0dd38a35 116 u32 force_2t;
712cf7ab 117};
d1712369 118
712cf7ab
YS
119/*
120 * This table contains all valid speeds we want to override with board
121 * specific parameters. datarate_mhz_high values need to be in ascending order
122 * for each n_ranks group.
123 */
124static const struct board_specific_parameters udimm0[] = {
6b06d7dc
YS
125 /*
126 * memory controller 0
712cf7ab
YS
127 * num| hi| clk| wrlvl | cpo |wrdata|2T
128 * ranks| mhz|adjst| start | |delay |
6b06d7dc 129 */
712cf7ab
YS
130 {4, 850, 4, 6, 0xff, 2, 0},
131 {4, 950, 5, 7, 0xff, 2, 0},
132 {4, 1050, 5, 8, 0xff, 2, 0},
133 {4, 1250, 5, 10, 0xff, 2, 0},
134 {4, 1350, 5, 11, 0xff, 2, 0},
135 {4, 1666, 5, 12, 0xff, 2, 0},
136 {2, 850, 5, 6, 0xff, 2, 0},
137 {2, 1050, 5, 7, 0xff, 2, 0},
138 {2, 1250, 4, 6, 0xff, 2, 0},
139 {2, 1350, 5, 7, 0xff, 2, 0},
140 {2, 1666, 5, 8, 0xff, 2, 0},
765ad3cf
YS
141 {1, 1250, 4, 6, 0xff, 2, 0},
142 {1, 1335, 4, 7, 0xff, 2, 0},
712cf7ab
YS
143 {1, 1666, 4, 8, 0xff, 2, 0},
144 {}
145};
d1712369 146
712cf7ab
YS
147/*
148 * The two slots have slightly different timing. The center values are good
149 * for both slots. We use identical speed tables for them. In future use, if
150 * DIMMs have fewer center values that require two separated tables, copy the
151 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
152 */
153static const struct board_specific_parameters *udimms[] = {
154 udimm0,
155 udimm0,
9ec8dec5
YS
156};
157
712cf7ab 158static const struct board_specific_parameters rdimm0[] = {
9ec8dec5
YS
159 /*
160 * memory controller 0
712cf7ab
YS
161 * num| hi| clk| wrlvl | cpo |wrdata|2T
162 * ranks| mhz|adjst| start | |delay |
9ec8dec5 163 */
712cf7ab
YS
164 {4, 850, 4, 6, 0xff, 2, 0},
165 {4, 950, 5, 7, 0xff, 2, 0},
166 {4, 1050, 5, 8, 0xff, 2, 0},
167 {4, 1250, 5, 10, 0xff, 2, 0},
168 {4, 1350, 5, 11, 0xff, 2, 0},
169 {4, 1666, 5, 12, 0xff, 2, 0},
170 {2, 850, 4, 6, 0xff, 2, 0},
171 {2, 1050, 4, 7, 0xff, 2, 0},
172 {2, 1666, 4, 8, 0xff, 2, 0},
173 {1, 850, 4, 5, 0xff, 2, 0},
174 {1, 950, 4, 7, 0xff, 2, 0},
175 {1, 1666, 4, 8, 0xff, 2, 0},
176 {}
177};
9ec8dec5 178
712cf7ab
YS
179/*
180 * The two slots have slightly different timing. See comments above.
181 */
182static const struct board_specific_parameters *rdimms[] = {
183 rdimm0,
184 rdimm0,
d1712369
KG
185};
186
187void fsl_ddr_board_options(memctl_options_t *popts,
188 dimm_params_t *pdimm,
189 unsigned int ctrl_num)
190{
712cf7ab 191 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
d1712369
KG
192 ulong ddr_freq;
193
712cf7ab
YS
194 if (ctrl_num > 1) {
195 printf("Wrong parameter for controller number %d", ctrl_num);
196 return;
9ec8dec5 197 }
712cf7ab
YS
198 if (!pdimm->n_ranks)
199 return;
200
201 if (popts->registered_dimm_en)
202 pbsp = rdimms[ctrl_num];
203 else
204 pbsp = udimms[ctrl_num];
205
206
d1712369
KG
207 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
208 * freqency and n_banks specified in board_specific_parameters table.
209 */
210 ddr_freq = get_ddr_freq(0) / 1000000;
712cf7ab
YS
211 while (pbsp->datarate_mhz_high) {
212 if (pbsp->n_ranks == pdimm->n_ranks) {
213 if (ddr_freq <= pbsp->datarate_mhz_high) {
214 popts->cpo_override = pbsp->cpo;
215 popts->write_data_delay =
216 pbsp->write_data_delay;
217 popts->clk_adjust = pbsp->clk_adjust;
218 popts->wrlvl_start = pbsp->wrlvl_start;
0dd38a35 219 popts->twot_en = pbsp->force_2t;
712cf7ab
YS
220 goto found;
221 }
222 pbsp_highest = pbsp;
d1712369
KG
223 }
224 pbsp++;
225 }
226
712cf7ab
YS
227 if (pbsp_highest) {
228 printf("Error: board specific timing not found "
229 "for data rate %lu MT/s!\n"
230 "Trying to use the highest speed (%u) parameters\n",
231 ddr_freq, pbsp_highest->datarate_mhz_high);
232 popts->cpo_override = pbsp_highest->cpo;
233 popts->write_data_delay = pbsp_highest->write_data_delay;
234 popts->clk_adjust = pbsp_highest->clk_adjust;
235 popts->wrlvl_start = pbsp_highest->wrlvl_start;
0dd38a35 236 popts->twot_en = pbsp_highest->force_2t;
712cf7ab
YS
237 } else {
238 panic("DIMM is not supported by this board");
939e5bf9 239 }
712cf7ab 240found:
d1712369
KG
241 /*
242 * Factors to consider for half-strength driver enable:
243 * - number of DIMMs installed
244 */
245 popts->half_strength_driver_enable = 0;
246 /*
247 * Write leveling override
248 */
249 popts->wrlvl_override = 1;
6b06d7dc
YS
250 popts->wrlvl_sample = 0xf;
251
d1712369
KG
252 /*
253 * Rtt and Rtt_WR override
254 */
6b06d7dc 255 popts->rtt_override = 0;
d1712369
KG
256
257 /* Enable ZQ calibration */
258 popts->zq_en = 1;
6b06d7dc
YS
259
260 /* DHC_EN =1, ODT = 60 Ohm */
261 popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
d1712369 262}
28a96671 263
f1683aa7 264int dram_init(void)
28a96671
YS
265{
266 phys_size_t dram_size;
28a96671
YS
267
268 puts("Initializing....");
269
3dbd5d7d 270 if (fsl_use_spd()) {
28a96671
YS
271 puts("using SPD\n");
272 dram_size = fsl_ddr_sdram();
273 } else {
274 puts("using fixed parameters\n");
275 dram_size = fixed_sdram();
276 }
277
278 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
279 dram_size *= 0x100000;
280
21cd5815 281 debug(" DDR: ");
088454cd
SG
282 gd->ram_size = dram_size;
283
284 return 0;
28a96671 285}
This page took 0.506178 seconds and 4 git commands to generate.