Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
177ba1f9 LFT |
2 | /* |
3 | * Copyright (C) 2016-2017 Intel Corporation | |
177ba1f9 LFT |
4 | */ |
5 | ||
6 | #include <common.h> | |
7 | #include <fdtdec.h> | |
336d4615 | 8 | #include <malloc.h> |
177ba1f9 | 9 | #include <asm/io.h> |
21143ce1 | 10 | #include <dm.h> |
934aec71 MV |
11 | #include <clk.h> |
12 | #include <dm/device-internal.h> | |
177ba1f9 LFT |
13 | #include <asm/arch/clock_manager.h> |
14 | ||
0b8f6378 | 15 | #ifdef CONFIG_SPL_BUILD |
480f7f9c | 16 | |
177ba1f9 LFT |
17 | static u32 eosc1_hz; |
18 | static u32 cb_intosc_hz; | |
19 | static u32 f2s_free_hz; | |
177ba1f9 LFT |
20 | |
21 | struct mainpll_cfg { | |
22 | u32 vco0_psrc; | |
23 | u32 vco1_denom; | |
24 | u32 vco1_numer; | |
25 | u32 mpuclk; | |
26 | u32 mpuclk_cnt; | |
27 | u32 mpuclk_src; | |
28 | u32 nocclk; | |
29 | u32 nocclk_cnt; | |
30 | u32 nocclk_src; | |
31 | u32 cntr2clk_cnt; | |
32 | u32 cntr3clk_cnt; | |
33 | u32 cntr4clk_cnt; | |
34 | u32 cntr5clk_cnt; | |
35 | u32 cntr6clk_cnt; | |
36 | u32 cntr7clk_cnt; | |
37 | u32 cntr7clk_src; | |
38 | u32 cntr8clk_cnt; | |
39 | u32 cntr9clk_cnt; | |
40 | u32 cntr9clk_src; | |
41 | u32 cntr15clk_cnt; | |
42 | u32 nocdiv_l4mainclk; | |
43 | u32 nocdiv_l4mpclk; | |
44 | u32 nocdiv_l4spclk; | |
45 | u32 nocdiv_csatclk; | |
46 | u32 nocdiv_cstraceclk; | |
47 | u32 nocdiv_cspdbclk; | |
48 | }; | |
49 | ||
50 | struct perpll_cfg { | |
51 | u32 vco0_psrc; | |
52 | u32 vco1_denom; | |
53 | u32 vco1_numer; | |
54 | u32 cntr2clk_cnt; | |
55 | u32 cntr2clk_src; | |
56 | u32 cntr3clk_cnt; | |
57 | u32 cntr3clk_src; | |
58 | u32 cntr4clk_cnt; | |
59 | u32 cntr4clk_src; | |
60 | u32 cntr5clk_cnt; | |
61 | u32 cntr5clk_src; | |
62 | u32 cntr6clk_cnt; | |
63 | u32 cntr6clk_src; | |
64 | u32 cntr7clk_cnt; | |
65 | u32 cntr8clk_cnt; | |
66 | u32 cntr8clk_src; | |
67 | u32 cntr9clk_cnt; | |
480f7f9c | 68 | u32 cntr9clk_src; |
177ba1f9 LFT |
69 | u32 emacctl_emac0sel; |
70 | u32 emacctl_emac1sel; | |
71 | u32 emacctl_emac2sel; | |
72 | u32 gpiodiv_gpiodbclk; | |
73 | }; | |
74 | ||
480f7f9c MV |
75 | struct strtou32 { |
76 | const char *str; | |
77 | const u32 val; | |
177ba1f9 LFT |
78 | }; |
79 | ||
480f7f9c MV |
80 | static const struct strtou32 mainpll_cfg_tab[] = { |
81 | { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) }, | |
82 | { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) }, | |
83 | { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) }, | |
84 | { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) }, | |
85 | { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) }, | |
86 | { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) }, | |
87 | { "nocclk-src", offsetof(struct mainpll_cfg, nocclk_src) }, | |
88 | { "cntr2clk-cnt", offsetof(struct mainpll_cfg, cntr2clk_cnt) }, | |
89 | { "cntr3clk-cnt", offsetof(struct mainpll_cfg, cntr3clk_cnt) }, | |
90 | { "cntr4clk-cnt", offsetof(struct mainpll_cfg, cntr4clk_cnt) }, | |
91 | { "cntr5clk-cnt", offsetof(struct mainpll_cfg, cntr5clk_cnt) }, | |
92 | { "cntr6clk-cnt", offsetof(struct mainpll_cfg, cntr6clk_cnt) }, | |
93 | { "cntr7clk-cnt", offsetof(struct mainpll_cfg, cntr7clk_cnt) }, | |
94 | { "cntr7clk-src", offsetof(struct mainpll_cfg, cntr7clk_src) }, | |
95 | { "cntr8clk-cnt", offsetof(struct mainpll_cfg, cntr8clk_cnt) }, | |
96 | { "cntr9clk-cnt", offsetof(struct mainpll_cfg, cntr9clk_cnt) }, | |
97 | { "cntr9clk-src", offsetof(struct mainpll_cfg, cntr9clk_src) }, | |
98 | { "cntr15clk-cnt", offsetof(struct mainpll_cfg, cntr15clk_cnt) }, | |
99 | { "nocdiv-l4mainclk", offsetof(struct mainpll_cfg, nocdiv_l4mainclk) }, | |
100 | { "nocdiv-l4mpclk", offsetof(struct mainpll_cfg, nocdiv_l4mpclk) }, | |
101 | { "nocdiv-l4spclk", offsetof(struct mainpll_cfg, nocdiv_l4spclk) }, | |
102 | { "nocdiv-csatclk", offsetof(struct mainpll_cfg, nocdiv_csatclk) }, | |
103 | { "nocdiv-cstraceclk", offsetof(struct mainpll_cfg, nocdiv_cstraceclk) }, | |
104 | { "nocdiv-cspdbgclk", offsetof(struct mainpll_cfg, nocdiv_cspdbclk) }, | |
105 | }; | |
106 | ||
107 | static const struct strtou32 perpll_cfg_tab[] = { | |
108 | { "vco0-psrc", offsetof(struct perpll_cfg, vco0_psrc) }, | |
109 | { "vco1-denom", offsetof(struct perpll_cfg, vco1_denom) }, | |
110 | { "vco1-numer", offsetof(struct perpll_cfg, vco1_numer) }, | |
111 | { "cntr2clk-cnt", offsetof(struct perpll_cfg, cntr2clk_cnt) }, | |
112 | { "cntr2clk-src", offsetof(struct perpll_cfg, cntr2clk_src) }, | |
113 | { "cntr3clk-cnt", offsetof(struct perpll_cfg, cntr3clk_cnt) }, | |
114 | { "cntr3clk-src", offsetof(struct perpll_cfg, cntr3clk_src) }, | |
115 | { "cntr4clk-cnt", offsetof(struct perpll_cfg, cntr4clk_cnt) }, | |
116 | { "cntr4clk-src", offsetof(struct perpll_cfg, cntr4clk_src) }, | |
117 | { "cntr5clk-cnt", offsetof(struct perpll_cfg, cntr5clk_cnt) }, | |
118 | { "cntr5clk-src", offsetof(struct perpll_cfg, cntr5clk_src) }, | |
119 | { "cntr6clk-cnt", offsetof(struct perpll_cfg, cntr6clk_cnt) }, | |
120 | { "cntr6clk-src", offsetof(struct perpll_cfg, cntr6clk_src) }, | |
121 | { "cntr7clk-cnt", offsetof(struct perpll_cfg, cntr7clk_cnt) }, | |
122 | { "cntr8clk-cnt", offsetof(struct perpll_cfg, cntr8clk_cnt) }, | |
123 | { "cntr8clk-src", offsetof(struct perpll_cfg, cntr8clk_src) }, | |
124 | { "cntr9clk-cnt", offsetof(struct perpll_cfg, cntr9clk_cnt) }, | |
125 | { "emacctl-emac0sel", offsetof(struct perpll_cfg, emacctl_emac0sel) }, | |
126 | { "emacctl-emac1sel", offsetof(struct perpll_cfg, emacctl_emac1sel) }, | |
127 | { "emacctl-emac2sel", offsetof(struct perpll_cfg, emacctl_emac2sel) }, | |
128 | { "gpiodiv-gpiodbclk", offsetof(struct perpll_cfg, gpiodiv_gpiodbclk) }, | |
129 | }; | |
130 | ||
131 | static const struct strtou32 alteragrp_cfg_tab[] = { | |
132 | { "nocclk", offsetof(struct mainpll_cfg, nocclk) }, | |
133 | { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) }, | |
134 | }; | |
135 | ||
136 | struct strtopu32 { | |
137 | const char *str; | |
138 | u32 *p; | |
139 | }; | |
140 | ||
141 | const struct strtopu32 dt_to_val[] = { | |
934aec71 MV |
142 | { "altera_arria10_hps_eosc1", &eosc1_hz }, |
143 | { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz }, | |
144 | { "altera_arria10_hps_f2h_free", &f2s_free_hz }, | |
480f7f9c | 145 | }; |
177ba1f9 | 146 | |
480f7f9c MV |
147 | static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab, |
148 | int cfg_tab_len, void *cfg) | |
177ba1f9 | 149 | { |
480f7f9c MV |
150 | int i; |
151 | u32 val; | |
152 | ||
153 | for (i = 0; i < cfg_tab_len; i++) { | |
154 | if (fdtdec_get_int_array(blob, node, cfg_tab[i].str, &val, 1)) { | |
155 | /* could not find required property */ | |
156 | return -EINVAL; | |
157 | } | |
158 | *(u32 *)(cfg + cfg_tab[i].val) = val; | |
177ba1f9 LFT |
159 | } |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
934aec71 | 164 | static int of_get_input_clks(const void *blob) |
177ba1f9 | 165 | { |
934aec71 MV |
166 | struct udevice *dev; |
167 | struct clk clk; | |
168 | int i, ret; | |
177ba1f9 | 169 | |
480f7f9c | 170 | for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) { |
934aec71 | 171 | memset(&clk, 0, sizeof(clk)); |
480f7f9c | 172 | |
934aec71 MV |
173 | ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str, |
174 | &dev); | |
175 | if (ret) | |
176 | return ret; | |
480f7f9c | 177 | |
934aec71 MV |
178 | ret = clk_request(dev, &clk); |
179 | if (ret) | |
180 | return ret; | |
181 | ||
182 | *dt_to_val[i].p = clk_get_rate(&clk); | |
480f7f9c | 183 | } |
934aec71 MV |
184 | |
185 | return 0; | |
177ba1f9 LFT |
186 | } |
187 | ||
188 | static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg, | |
480f7f9c | 189 | struct perpll_cfg *per_cfg) |
177ba1f9 | 190 | { |
934aec71 | 191 | int ret, node, child, len; |
177ba1f9 LFT |
192 | const char *node_name; |
193 | ||
934aec71 MV |
194 | ret = of_get_input_clks(blob); |
195 | if (ret) | |
196 | return ret; | |
480f7f9c MV |
197 | |
198 | node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT); | |
199 | ||
177ba1f9 LFT |
200 | if (node < 0) |
201 | return -EINVAL; | |
202 | ||
203 | child = fdt_first_subnode(blob, node); | |
177ba1f9 | 204 | |
177ba1f9 LFT |
205 | if (child < 0) |
206 | return -EINVAL; | |
207 | ||
208 | node_name = fdt_get_name(blob, child, &len); | |
209 | ||
210 | while (node_name) { | |
480f7f9c MV |
211 | if (!strcmp(node_name, "mainpll")) { |
212 | if (of_to_struct(blob, child, mainpll_cfg_tab, | |
213 | ARRAY_SIZE(mainpll_cfg_tab), main_cfg)) | |
177ba1f9 | 214 | return -EINVAL; |
480f7f9c MV |
215 | } else if (!strcmp(node_name, "perpll")) { |
216 | if (of_to_struct(blob, child, perpll_cfg_tab, | |
217 | ARRAY_SIZE(perpll_cfg_tab), per_cfg)) | |
177ba1f9 | 218 | return -EINVAL; |
480f7f9c MV |
219 | } else if (!strcmp(node_name, "alteragrp")) { |
220 | if (of_to_struct(blob, child, alteragrp_cfg_tab, | |
221 | ARRAY_SIZE(alteragrp_cfg_tab), main_cfg)) | |
177ba1f9 | 222 | return -EINVAL; |
177ba1f9 LFT |
223 | } |
224 | child = fdt_next_subnode(blob, child); | |
225 | ||
226 | if (child < 0) | |
227 | break; | |
228 | ||
229 | node_name = fdt_get_name(blob, child, &len); | |
230 | } | |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | /* calculate the intended main VCO frequency based on handoff */ | |
236 | static unsigned int cm_calc_handoff_main_vco_clk_hz | |
237 | (struct mainpll_cfg *main_cfg) | |
238 | { | |
239 | unsigned int clk_hz; | |
240 | ||
241 | /* Check main VCO clock source: eosc, intosc or f2s? */ | |
242 | switch (main_cfg->vco0_psrc) { | |
243 | case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: | |
244 | clk_hz = eosc1_hz; | |
245 | break; | |
246 | case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: | |
247 | clk_hz = cb_intosc_hz; | |
248 | break; | |
249 | case CLKMGR_MAINPLL_VCO0_PSRC_F2S: | |
250 | clk_hz = f2s_free_hz; | |
251 | break; | |
252 | default: | |
253 | return 0; | |
254 | } | |
255 | ||
256 | /* calculate the VCO frequency */ | |
257 | clk_hz /= 1 + main_cfg->vco1_denom; | |
258 | clk_hz *= 1 + main_cfg->vco1_numer; | |
259 | ||
260 | return clk_hz; | |
261 | } | |
262 | ||
263 | /* calculate the intended periph VCO frequency based on handoff */ | |
264 | static unsigned int cm_calc_handoff_periph_vco_clk_hz( | |
265 | struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) | |
266 | { | |
267 | unsigned int clk_hz; | |
268 | ||
269 | /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */ | |
270 | switch (per_cfg->vco0_psrc) { | |
271 | case CLKMGR_PERPLL_VCO0_PSRC_EOSC: | |
272 | clk_hz = eosc1_hz; | |
273 | break; | |
274 | case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: | |
275 | clk_hz = cb_intosc_hz; | |
276 | break; | |
277 | case CLKMGR_PERPLL_VCO0_PSRC_F2S: | |
278 | clk_hz = f2s_free_hz; | |
279 | break; | |
280 | case CLKMGR_PERPLL_VCO0_PSRC_MAIN: | |
281 | clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); | |
282 | clk_hz /= main_cfg->cntr15clk_cnt; | |
283 | break; | |
284 | default: | |
285 | return 0; | |
286 | } | |
287 | ||
288 | /* calculate the VCO frequency */ | |
289 | clk_hz /= 1 + per_cfg->vco1_denom; | |
290 | clk_hz *= 1 + per_cfg->vco1_numer; | |
291 | ||
292 | return clk_hz; | |
293 | } | |
294 | ||
295 | /* calculate the intended MPU clock frequency based on handoff */ | |
296 | static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg, | |
297 | struct perpll_cfg *per_cfg) | |
298 | { | |
299 | unsigned int clk_hz; | |
300 | ||
301 | /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ | |
302 | switch (main_cfg->mpuclk_src) { | |
303 | case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN: | |
304 | clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); | |
305 | clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) | |
306 | + 1; | |
307 | break; | |
308 | case CLKMGR_MAINPLL_MPUCLK_SRC_PERI: | |
309 | clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); | |
310 | clk_hz /= ((main_cfg->mpuclk >> | |
311 | CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) & | |
312 | CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1; | |
313 | break; | |
314 | case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1: | |
315 | clk_hz = eosc1_hz; | |
316 | break; | |
317 | case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC: | |
318 | clk_hz = cb_intosc_hz; | |
319 | break; | |
320 | case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA: | |
321 | clk_hz = f2s_free_hz; | |
322 | break; | |
323 | default: | |
324 | return 0; | |
325 | } | |
326 | ||
327 | clk_hz /= main_cfg->mpuclk_cnt + 1; | |
328 | return clk_hz; | |
329 | } | |
330 | ||
331 | /* calculate the intended NOC clock frequency based on handoff */ | |
332 | static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg, | |
333 | struct perpll_cfg *per_cfg) | |
334 | { | |
335 | unsigned int clk_hz; | |
336 | ||
337 | /* Check MPU clock source: main, periph, osc1, intosc or f2s? */ | |
338 | switch (main_cfg->nocclk_src) { | |
339 | case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN: | |
340 | clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); | |
341 | clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK) | |
342 | + 1; | |
343 | break; | |
344 | case CLKMGR_MAINPLL_NOCCLK_SRC_PERI: | |
345 | clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg); | |
346 | clk_hz /= ((main_cfg->nocclk >> | |
347 | CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) & | |
348 | CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1; | |
349 | break; | |
350 | case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1: | |
351 | clk_hz = eosc1_hz; | |
352 | break; | |
353 | case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC: | |
354 | clk_hz = cb_intosc_hz; | |
355 | break; | |
356 | case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA: | |
357 | clk_hz = f2s_free_hz; | |
358 | break; | |
359 | default: | |
360 | return 0; | |
361 | } | |
362 | ||
363 | clk_hz /= main_cfg->nocclk_cnt + 1; | |
364 | return clk_hz; | |
365 | } | |
366 | ||
367 | /* return 1 if PLL ramp is required */ | |
368 | static int cm_is_pll_ramp_required(int main0periph1, | |
369 | struct mainpll_cfg *main_cfg, | |
370 | struct perpll_cfg *per_cfg) | |
371 | { | |
372 | /* Check for main PLL */ | |
373 | if (main0periph1 == 0) { | |
374 | /* | |
375 | * PLL ramp is not required if both MPU clock and NOC clock are | |
376 | * not sourced from main PLL | |
377 | */ | |
378 | if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && | |
379 | main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) | |
380 | return 0; | |
381 | ||
382 | /* | |
383 | * PLL ramp is required if MPU clock is sourced from main PLL | |
384 | * and MPU clock is over 900MHz (as advised by HW team) | |
385 | */ | |
386 | if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN && | |
387 | (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > | |
388 | CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) | |
389 | return 1; | |
390 | ||
391 | /* | |
392 | * PLL ramp is required if NOC clock is sourced from main PLL | |
393 | * and NOC clock is over 300MHz (as advised by HW team) | |
394 | */ | |
395 | if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN && | |
396 | (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > | |
397 | CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) | |
398 | return 2; | |
399 | ||
400 | } else if (main0periph1 == 1) { | |
401 | /* | |
402 | * PLL ramp is not required if both MPU clock and NOC clock are | |
403 | * not sourced from periph PLL | |
404 | */ | |
405 | if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI && | |
406 | main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI) | |
407 | return 0; | |
408 | ||
409 | /* | |
410 | * PLL ramp is required if MPU clock are source from periph PLL | |
411 | * and MPU clock is over 900MHz (as advised by HW team) | |
412 | */ | |
413 | if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI && | |
414 | (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) > | |
415 | CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ)) | |
416 | return 1; | |
417 | ||
418 | /* | |
419 | * PLL ramp is required if NOC clock are source from periph PLL | |
420 | * and NOC clock is over 300MHz (as advised by HW team) | |
421 | */ | |
422 | if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI && | |
423 | (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) > | |
424 | CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ)) | |
425 | return 2; | |
426 | } | |
427 | ||
428 | return 0; | |
429 | } | |
430 | ||
431 | static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg, | |
432 | struct perpll_cfg *per_cfg, | |
433 | u32 safe_hz, u32 clk_hz) | |
434 | { | |
435 | u32 cnt; | |
436 | u32 clk; | |
437 | u32 shift; | |
438 | u32 mask; | |
439 | u32 denom; | |
440 | ||
441 | if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { | |
442 | cnt = main_cfg->mpuclk_cnt; | |
443 | clk = main_cfg->mpuclk; | |
444 | shift = 0; | |
445 | mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; | |
446 | denom = main_cfg->vco1_denom; | |
447 | } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { | |
448 | cnt = main_cfg->nocclk_cnt; | |
449 | clk = main_cfg->nocclk; | |
450 | shift = 0; | |
451 | mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; | |
452 | denom = main_cfg->vco1_denom; | |
453 | } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { | |
454 | cnt = main_cfg->mpuclk_cnt; | |
455 | clk = main_cfg->mpuclk; | |
456 | shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB; | |
457 | mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK; | |
458 | denom = per_cfg->vco1_denom; | |
459 | } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { | |
460 | cnt = main_cfg->nocclk_cnt; | |
461 | clk = main_cfg->nocclk; | |
462 | shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB; | |
463 | mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK; | |
464 | denom = per_cfg->vco1_denom; | |
465 | } else { | |
466 | return 0; | |
467 | } | |
468 | ||
469 | return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) * | |
470 | (1 + denom) - 1; | |
471 | } | |
472 | ||
473 | /* | |
474 | * Calculate the new PLL numerator which is based on existing DTS hand off and | |
475 | * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the | |
476 | * numerator while maintaining denominator as denominator will influence the | |
477 | * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final | |
478 | * value for numerator is minus with 1 to cater our register value | |
479 | * representation. | |
480 | */ | |
481 | static unsigned int cm_calc_safe_pll_numer(int main0periph1, | |
482 | struct mainpll_cfg *main_cfg, | |
483 | struct perpll_cfg *per_cfg, | |
484 | unsigned int safe_hz) | |
485 | { | |
486 | unsigned int clk_hz = 0; | |
487 | ||
488 | /* Check for main PLL */ | |
489 | if (main0periph1 == 0) { | |
490 | /* Check main VCO clock source: eosc, intosc or f2s? */ | |
491 | switch (main_cfg->vco0_psrc) { | |
492 | case CLKMGR_MAINPLL_VCO0_PSRC_EOSC: | |
493 | clk_hz = eosc1_hz; | |
494 | break; | |
495 | case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC: | |
496 | clk_hz = cb_intosc_hz; | |
497 | break; | |
498 | case CLKMGR_MAINPLL_VCO0_PSRC_F2S: | |
499 | clk_hz = f2s_free_hz; | |
500 | break; | |
501 | default: | |
502 | return 0; | |
503 | } | |
504 | } else if (main0periph1 == 1) { | |
505 | /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */ | |
506 | switch (per_cfg->vco0_psrc) { | |
507 | case CLKMGR_PERPLL_VCO0_PSRC_EOSC: | |
508 | clk_hz = eosc1_hz; | |
509 | break; | |
510 | case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC: | |
511 | clk_hz = cb_intosc_hz; | |
512 | break; | |
513 | case CLKMGR_PERPLL_VCO0_PSRC_F2S: | |
514 | clk_hz = f2s_free_hz; | |
515 | break; | |
516 | case CLKMGR_PERPLL_VCO0_PSRC_MAIN: | |
517 | clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg); | |
518 | clk_hz /= main_cfg->cntr15clk_cnt; | |
519 | break; | |
520 | default: | |
521 | return 0; | |
522 | } | |
523 | } else { | |
524 | return 0; | |
525 | } | |
526 | ||
527 | return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz); | |
528 | } | |
529 | ||
530 | /* ramping the main PLL to final value */ | |
531 | static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg, | |
532 | struct perpll_cfg *per_cfg, | |
533 | unsigned int pll_ramp_main_hz) | |
534 | { | |
535 | unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; | |
536 | ||
537 | /* find out the increment value */ | |
538 | if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) { | |
539 | clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; | |
540 | clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); | |
541 | } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) { | |
542 | clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; | |
543 | clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); | |
544 | } | |
545 | ||
546 | /* execute the ramping here */ | |
547 | for (clk_hz = pll_ramp_main_hz + clk_incr_hz; | |
548 | clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { | |
549 | writel((main_cfg->vco1_denom << | |
550 | CLKMGR_MAINPLL_VCO1_DENOM_LSB) | | |
551 | cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz), | |
94172c79 | 552 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); |
177ba1f9 LFT |
553 | mdelay(1); |
554 | cm_wait_for_lock(LOCKED_MASK); | |
555 | } | |
556 | writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) | | |
94172c79 LFT |
557 | main_cfg->vco1_numer, |
558 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); | |
177ba1f9 LFT |
559 | mdelay(1); |
560 | cm_wait_for_lock(LOCKED_MASK); | |
561 | } | |
562 | ||
563 | /* ramping the periph PLL to final value */ | |
564 | static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg, | |
565 | struct perpll_cfg *per_cfg, | |
566 | unsigned int pll_ramp_periph_hz) | |
567 | { | |
568 | unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0; | |
569 | ||
570 | /* find out the increment value */ | |
571 | if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) { | |
572 | clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ; | |
573 | clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg); | |
574 | } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) { | |
575 | clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ; | |
576 | clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg); | |
577 | } | |
578 | /* execute the ramping here */ | |
579 | for (clk_hz = pll_ramp_periph_hz + clk_incr_hz; | |
580 | clk_hz < clk_final_hz; clk_hz += clk_incr_hz) { | |
94172c79 LFT |
581 | writel((per_cfg->vco1_denom << |
582 | CLKMGR_PERPLL_VCO1_DENOM_LSB) | | |
583 | cm_calc_safe_pll_numer(1, main_cfg, per_cfg, | |
584 | clk_hz), | |
585 | socfpga_get_clkmgr_addr() + | |
586 | CLKMGR_A10_PERPLL_VCO1); | |
177ba1f9 LFT |
587 | mdelay(1); |
588 | cm_wait_for_lock(LOCKED_MASK); | |
589 | } | |
590 | writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) | | |
94172c79 LFT |
591 | per_cfg->vco1_numer, |
592 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); | |
177ba1f9 LFT |
593 | mdelay(1); |
594 | cm_wait_for_lock(LOCKED_MASK); | |
595 | } | |
596 | ||
597 | /* | |
598 | * Setup clocks while making no assumptions of the | |
599 | * previous state of the clocks. | |
600 | * | |
601 | * Start by being paranoid and gate all sw managed clocks | |
602 | * | |
603 | * Put all plls in bypass | |
604 | * | |
605 | * Put all plls VCO registers back to reset value (bgpwr dwn). | |
606 | * | |
607 | * Put peripheral and main pll src to reset value to avoid glitch. | |
608 | * | |
609 | * Delay 5 us. | |
610 | * | |
611 | * Deassert bg pwr dn and set numerator and denominator | |
612 | * | |
613 | * Start 7 us timer. | |
614 | * | |
615 | * set internal dividers | |
616 | * | |
617 | * Wait for 7 us timer. | |
618 | * | |
619 | * Enable plls | |
620 | * | |
621 | * Set external dividers while plls are locking | |
622 | * | |
623 | * Wait for pll lock | |
624 | * | |
625 | * Assert/deassert outreset all. | |
626 | * | |
627 | * Take all pll's out of bypass | |
628 | * | |
629 | * Clear safe mode | |
630 | * | |
631 | * set source main and peripheral clocks | |
632 | * | |
633 | * Ungate clocks | |
634 | */ | |
635 | ||
636 | static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg) | |
637 | { | |
638 | unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0, | |
639 | ramp_required; | |
640 | ||
641 | /* gate off all mainpll clock excpet HW managed clock */ | |
642 | writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | | |
643 | CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, | |
94172c79 | 644 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENR); |
177ba1f9 LFT |
645 | |
646 | /* now we can gate off the rest of the peripheral clocks */ | |
94172c79 | 647 | writel(0, socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EN); |
177ba1f9 LFT |
648 | |
649 | /* Put all plls in external bypass */ | |
650 | writel(CLKMGR_MAINPLL_BYPASS_RESET, | |
94172c79 | 651 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSS); |
177ba1f9 | 652 | writel(CLKMGR_PERPLL_BYPASS_RESET, |
94172c79 | 653 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSS); |
177ba1f9 LFT |
654 | |
655 | /* | |
656 | * Put all plls VCO registers back to reset value. | |
657 | * Some code might have messed with them. At same time set the | |
658 | * desired clock source | |
659 | */ | |
660 | writel(CLKMGR_MAINPLL_VCO0_RESET | | |
661 | CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK | | |
662 | (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB), | |
94172c79 | 663 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0); |
177ba1f9 LFT |
664 | |
665 | writel(CLKMGR_PERPLL_VCO0_RESET | | |
666 | CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK | | |
667 | (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB), | |
94172c79 | 668 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0); |
177ba1f9 | 669 | |
94172c79 LFT |
670 | writel(CLKMGR_MAINPLL_VCO1_RESET, |
671 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); | |
672 | writel(CLKMGR_PERPLL_VCO1_RESET, | |
673 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); | |
177ba1f9 LFT |
674 | |
675 | /* clear the interrupt register status register */ | |
676 | writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | | |
677 | CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | | |
678 | CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | | |
679 | CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | | |
680 | CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | | |
681 | CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK | | |
682 | CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK | | |
683 | CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK, | |
94172c79 | 684 | socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR); |
177ba1f9 LFT |
685 | |
686 | /* Program VCO Numerator and Denominator for main PLL */ | |
687 | ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg); | |
688 | if (ramp_required) { | |
689 | /* set main PLL to safe starting threshold frequency */ | |
690 | if (ramp_required == 1) | |
691 | pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; | |
692 | else if (ramp_required == 2) | |
693 | pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; | |
694 | ||
94172c79 LFT |
695 | writel((main_cfg->vco1_denom << |
696 | CLKMGR_MAINPLL_VCO1_DENOM_LSB) | | |
177ba1f9 LFT |
697 | cm_calc_safe_pll_numer(0, main_cfg, per_cfg, |
698 | pll_ramp_main_hz), | |
94172c79 | 699 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); |
177ba1f9 | 700 | } else |
94172c79 LFT |
701 | writel((main_cfg->vco1_denom << |
702 | CLKMGR_MAINPLL_VCO1_DENOM_LSB) | | |
703 | main_cfg->vco1_numer, | |
704 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1); | |
177ba1f9 LFT |
705 | |
706 | /* Program VCO Numerator and Denominator for periph PLL */ | |
707 | ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg); | |
708 | if (ramp_required) { | |
709 | /* set periph PLL to safe starting threshold frequency */ | |
710 | if (ramp_required == 1) | |
711 | pll_ramp_periph_hz = | |
712 | CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ; | |
713 | else if (ramp_required == 2) | |
714 | pll_ramp_periph_hz = | |
715 | CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ; | |
716 | ||
94172c79 LFT |
717 | writel((per_cfg->vco1_denom << |
718 | CLKMGR_PERPLL_VCO1_DENOM_LSB) | | |
177ba1f9 LFT |
719 | cm_calc_safe_pll_numer(1, main_cfg, per_cfg, |
720 | pll_ramp_periph_hz), | |
94172c79 | 721 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); |
177ba1f9 | 722 | } else |
94172c79 LFT |
723 | writel((per_cfg->vco1_denom << |
724 | CLKMGR_PERPLL_VCO1_DENOM_LSB) | | |
177ba1f9 | 725 | per_cfg->vco1_numer, |
94172c79 | 726 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1); |
177ba1f9 LFT |
727 | |
728 | /* Wait for at least 5 us */ | |
729 | udelay(5); | |
730 | ||
731 | /* Now deassert BGPWRDN and PWRDN */ | |
94172c79 | 732 | clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, |
177ba1f9 LFT |
733 | CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK | |
734 | CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK); | |
94172c79 | 735 | clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0, |
177ba1f9 LFT |
736 | CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK | |
737 | CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK); | |
738 | ||
739 | /* Wait for at least 7 us */ | |
740 | udelay(7); | |
741 | ||
742 | /* enable the VCO and disable the external regulator to PLL */ | |
94172c79 | 743 | writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) & |
177ba1f9 LFT |
744 | ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) | |
745 | CLKMGR_MAINPLL_VCO0_EN_SET_MSK, | |
94172c79 LFT |
746 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0); |
747 | writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0) & | |
177ba1f9 LFT |
748 | ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) | |
749 | CLKMGR_PERPLL_VCO0_EN_SET_MSK, | |
94172c79 | 750 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0); |
177ba1f9 LFT |
751 | |
752 | /* setup all the main PLL counter and clock source */ | |
753 | writel(main_cfg->nocclk, | |
94172c79 | 754 | socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_NOCCLK); |
177ba1f9 | 755 | writel(main_cfg->mpuclk, |
94172c79 | 756 | socfpga_get_clkmgr_addr() + CLKMGR_A10_ALTR_MPUCLK); |
177ba1f9 LFT |
757 | |
758 | /* main_emaca_clk divider */ | |
94172c79 LFT |
759 | writel(main_cfg->cntr2clk_cnt, |
760 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR2CLK); | |
177ba1f9 | 761 | /* main_emacb_clk divider */ |
94172c79 LFT |
762 | writel(main_cfg->cntr3clk_cnt, |
763 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR3CLK); | |
177ba1f9 | 764 | /* main_emac_ptp_clk divider */ |
94172c79 LFT |
765 | writel(main_cfg->cntr4clk_cnt, |
766 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR4CLK); | |
177ba1f9 | 767 | /* main_gpio_db_clk divider */ |
94172c79 LFT |
768 | writel(main_cfg->cntr5clk_cnt, |
769 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR5CLK); | |
177ba1f9 | 770 | /* main_sdmmc_clk divider */ |
94172c79 LFT |
771 | writel(main_cfg->cntr6clk_cnt, |
772 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR6CLK); | |
177ba1f9 LFT |
773 | /* main_s2f_user0_clk divider */ |
774 | writel(main_cfg->cntr7clk_cnt | | |
775 | (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB), | |
94172c79 | 776 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR7CLK); |
177ba1f9 | 777 | /* main_s2f_user1_clk divider */ |
94172c79 LFT |
778 | writel(main_cfg->cntr8clk_cnt, |
779 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR8CLK); | |
177ba1f9 LFT |
780 | /* main_hmc_pll_clk divider */ |
781 | writel(main_cfg->cntr9clk_cnt | | |
782 | (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB), | |
94172c79 | 783 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR9CLK); |
177ba1f9 LFT |
784 | /* main_periph_ref_clk divider */ |
785 | writel(main_cfg->cntr15clk_cnt, | |
94172c79 | 786 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_CNTR15CLK); |
177ba1f9 LFT |
787 | |
788 | /* setup all the peripheral PLL counter and clock source */ | |
789 | /* peri_emaca_clk divider */ | |
790 | writel(per_cfg->cntr2clk_cnt | | |
791 | (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB), | |
94172c79 | 792 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR2CLK); |
177ba1f9 LFT |
793 | /* peri_emacb_clk divider */ |
794 | writel(per_cfg->cntr3clk_cnt | | |
795 | (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB), | |
94172c79 | 796 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR3CLK); |
177ba1f9 LFT |
797 | /* peri_emac_ptp_clk divider */ |
798 | writel(per_cfg->cntr4clk_cnt | | |
799 | (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB), | |
94172c79 | 800 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR4CLK); |
177ba1f9 LFT |
801 | /* peri_gpio_db_clk divider */ |
802 | writel(per_cfg->cntr5clk_cnt | | |
803 | (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB), | |
94172c79 | 804 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR5CLK); |
177ba1f9 LFT |
805 | /* peri_sdmmc_clk divider */ |
806 | writel(per_cfg->cntr6clk_cnt | | |
807 | (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB), | |
94172c79 | 808 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR6CLK); |
177ba1f9 | 809 | /* peri_s2f_user0_clk divider */ |
94172c79 LFT |
810 | writel(per_cfg->cntr7clk_cnt, |
811 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR7CLK); | |
177ba1f9 LFT |
812 | /* peri_s2f_user1_clk divider */ |
813 | writel(per_cfg->cntr8clk_cnt | | |
814 | (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB), | |
94172c79 | 815 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR8CLK); |
177ba1f9 | 816 | /* peri_hmc_pll_clk divider */ |
94172c79 LFT |
817 | writel(per_cfg->cntr9clk_cnt, |
818 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_CNTR9CLK); | |
177ba1f9 LFT |
819 | |
820 | /* setup all the external PLL counter */ | |
821 | /* mpu wrapper / external divider */ | |
822 | writel(main_cfg->mpuclk_cnt | | |
823 | (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB), | |
94172c79 | 824 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_MPUCLK); |
177ba1f9 LFT |
825 | /* NOC wrapper / external divider */ |
826 | writel(main_cfg->nocclk_cnt | | |
827 | (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB), | |
94172c79 | 828 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCCLK); |
177ba1f9 LFT |
829 | /* NOC subclock divider such as l4 */ |
830 | writel(main_cfg->nocdiv_l4mainclk | | |
831 | (main_cfg->nocdiv_l4mpclk << | |
832 | CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) | | |
833 | (main_cfg->nocdiv_l4spclk << | |
834 | CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) | | |
835 | (main_cfg->nocdiv_csatclk << | |
836 | CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) | | |
837 | (main_cfg->nocdiv_cstraceclk << | |
838 | CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) | | |
839 | (main_cfg->nocdiv_cspdbclk << | |
840 | CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB), | |
94172c79 | 841 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_NOCDIV); |
177ba1f9 LFT |
842 | /* gpio_db external divider */ |
843 | writel(per_cfg->gpiodiv_gpiodbclk, | |
94172c79 | 844 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_GPIOFIV); |
177ba1f9 LFT |
845 | |
846 | /* setup the EMAC clock mux select */ | |
847 | writel((per_cfg->emacctl_emac0sel << | |
848 | CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) | | |
849 | (per_cfg->emacctl_emac1sel << | |
850 | CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) | | |
851 | (per_cfg->emacctl_emac2sel << | |
852 | CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB), | |
94172c79 | 853 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_EMACCTL); |
177ba1f9 LFT |
854 | |
855 | /* at this stage, check for PLL lock status */ | |
856 | cm_wait_for_lock(LOCKED_MASK); | |
857 | ||
858 | /* | |
859 | * after locking, but before taking out of bypass, | |
860 | * assert/deassert outresetall | |
861 | */ | |
862 | /* assert mainpll outresetall */ | |
94172c79 | 863 | setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, |
177ba1f9 LFT |
864 | CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); |
865 | /* assert perpll outresetall */ | |
94172c79 | 866 | setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0, |
177ba1f9 LFT |
867 | CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); |
868 | /* de-assert mainpll outresetall */ | |
94172c79 | 869 | clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0, |
177ba1f9 LFT |
870 | CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK); |
871 | /* de-assert perpll outresetall */ | |
94172c79 | 872 | clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO0, |
177ba1f9 LFT |
873 | CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK); |
874 | ||
875 | /* Take all PLLs out of bypass when boot mode is cleared. */ | |
876 | /* release mainpll from bypass */ | |
877 | writel(CLKMGR_MAINPLL_BYPASS_RESET, | |
94172c79 | 878 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR); |
177ba1f9 LFT |
879 | /* wait till Clock Manager is not busy */ |
880 | cm_wait_for_fsm(); | |
881 | ||
882 | /* release perpll from bypass */ | |
883 | writel(CLKMGR_PERPLL_BYPASS_RESET, | |
94172c79 | 884 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR); |
177ba1f9 LFT |
885 | /* wait till Clock Manager is not busy */ |
886 | cm_wait_for_fsm(); | |
887 | ||
888 | /* clear boot mode */ | |
94172c79 | 889 | clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL, |
177ba1f9 LFT |
890 | CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK); |
891 | /* wait till Clock Manager is not busy */ | |
892 | cm_wait_for_fsm(); | |
893 | ||
894 | /* At here, we need to ramp to final value if needed */ | |
895 | if (pll_ramp_main_hz != 0) | |
896 | cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz); | |
897 | if (pll_ramp_periph_hz != 0) | |
898 | cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz); | |
899 | ||
900 | /* Now ungate non-hw-managed clocks */ | |
901 | writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK | | |
94172c79 LFT |
902 | CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK, |
903 | socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_ENS); | |
904 | writel(CLKMGR_PERPLL_EN_RESET, | |
905 | socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_ENS); | |
177ba1f9 LFT |
906 | |
907 | /* Clear the loss lock and slip bits as they might set during | |
908 | clock reconfiguration */ | |
909 | writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK | | |
910 | CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK | | |
911 | CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK | | |
912 | CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK | | |
913 | CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK | | |
914 | CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK, | |
94172c79 | 915 | socfpga_get_clkmgr_addr() + CLKMGR_A10_INTR); |
177ba1f9 LFT |
916 | |
917 | return 0; | |
918 | } | |
919 | ||
0b8f6378 | 920 | static void cm_use_intosc(void) |
177ba1f9 | 921 | { |
94172c79 | 922 | setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL, |
177ba1f9 LFT |
923 | CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK); |
924 | } | |
925 | ||
177ba1f9 LFT |
926 | int cm_basic_init(const void *blob) |
927 | { | |
928 | struct mainpll_cfg main_cfg; | |
929 | struct perpll_cfg per_cfg; | |
177ba1f9 LFT |
930 | int rval; |
931 | ||
932 | /* initialize to zero for use case of optional node */ | |
933 | memset(&main_cfg, 0, sizeof(main_cfg)); | |
934 | memset(&per_cfg, 0, sizeof(per_cfg)); | |
177ba1f9 | 935 | |
480f7f9c | 936 | rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg); |
177ba1f9 LFT |
937 | if (rval) |
938 | return rval; | |
939 | ||
0b8f6378 MV |
940 | cm_use_intosc(); |
941 | ||
f4c3e0dc | 942 | return cm_full_cfg(&main_cfg, &per_cfg); |
177ba1f9 | 943 | } |
0b8f6378 | 944 | #endif |
177ba1f9 | 945 | |
d81b5da3 | 946 | static u32 cm_get_rate_dm(char *name) |
177ba1f9 | 947 | { |
d81b5da3 MV |
948 | struct uclass *uc; |
949 | struct udevice *dev = NULL; | |
950 | struct clk clk = { 0 }; | |
951 | ulong rate; | |
952 | int ret; | |
953 | ||
954 | /* Device addresses start at 1 */ | |
955 | ret = uclass_get(UCLASS_CLK, &uc); | |
956 | if (ret) | |
177ba1f9 | 957 | return 0; |
177ba1f9 | 958 | |
d81b5da3 MV |
959 | ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev); |
960 | if (ret) | |
177ba1f9 | 961 | return 0; |
177ba1f9 | 962 | |
d81b5da3 MV |
963 | ret = device_probe(dev); |
964 | if (ret) | |
177ba1f9 | 965 | return 0; |
177ba1f9 | 966 | |
d81b5da3 MV |
967 | ret = clk_request(dev, &clk); |
968 | if (ret) | |
969 | return 0; | |
177ba1f9 | 970 | |
d81b5da3 | 971 | rate = clk_get_rate(&clk); |
177ba1f9 | 972 | |
d81b5da3 | 973 | clk_free(&clk); |
177ba1f9 | 974 | |
d81b5da3 | 975 | return rate; |
177ba1f9 LFT |
976 | } |
977 | ||
d81b5da3 | 978 | static u32 cm_get_rate_dm_khz(char *name) |
177ba1f9 | 979 | { |
d81b5da3 | 980 | return cm_get_rate_dm(name) / 1000; |
177ba1f9 LFT |
981 | } |
982 | ||
d81b5da3 | 983 | unsigned long cm_get_mpu_clk_hz(void) |
177ba1f9 | 984 | { |
d81b5da3 | 985 | return cm_get_rate_dm("main_mpu_base_clk"); |
177ba1f9 LFT |
986 | } |
987 | ||
988 | unsigned int cm_get_qspi_controller_clk_hz(void) | |
989 | { | |
d81b5da3 | 990 | return cm_get_rate_dm("qspi_clk"); |
177ba1f9 LFT |
991 | } |
992 | ||
d81b5da3 | 993 | unsigned int cm_get_l4_sp_clk_hz(void) |
21143ce1 | 994 | { |
d81b5da3 | 995 | return cm_get_rate_dm("l4_sp_clk"); |
21143ce1 EP |
996 | } |
997 | ||
177ba1f9 LFT |
998 | void cm_print_clock_quick_summary(void) |
999 | { | |
d81b5da3 MV |
1000 | printf("MPU %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk")); |
1001 | printf("MMC %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk")); | |
1002 | printf("QSPI %8d kHz\n", cm_get_rate_dm_khz("qspi_clk")); | |
1003 | printf("SPI %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk")); | |
1004 | printf("EOSC1 %8d kHz\n", cm_get_rate_dm_khz("osc1")); | |
1005 | printf("cb_intosc %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk")); | |
1006 | printf("f2s_free %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk")); | |
1007 | printf("Main VCO %8d kHz\n", cm_get_rate_dm_khz("main_pll@40")); | |
1008 | printf("NOC %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk")); | |
1009 | printf("L4 Main %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk")); | |
1010 | printf("L4 MP %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk")); | |
1011 | printf("L4 SP %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk")); | |
1012 | printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk")); | |
177ba1f9 | 1013 | } |