[J-u-boot.git] / drivers / usb / dwc3 / dwc3-generic.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Generic DWC3 Glue layer
 *
 * Copyright (C) 2016 - 2018 Xilinx, Inc.
 *
 * Based on dwc3-omap.c.
 */

#include <common.h>
#include <cpu_func.h>
#include <asm-generic/io.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dwc3-uboot.h>
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
#include <malloc.h>
#include <usb.h>
#include "core.h"
#include "gadget.h"
#include <reset.h>
#include <clk.h>
#include <usb/xhci.h>

struct dwc3_generic_plat {
	fdt_addr_t base;
	u32 maximum_speed;
	enum usb_dr_mode dr_mode;
};

struct dwc3_generic_priv {
	void *base;
	struct dwc3 dwc3;
	struct phy_bulk phys;
};

struct dwc3_generic_host_priv {
	struct xhci_ctrl xhci_ctrl;
	struct dwc3_generic_priv gen_priv;
};

static int dwc3_generic_probe(struct udevice *dev,
			      struct dwc3_generic_priv *priv)
{
	int rc;
	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
	struct dwc3 *dwc3 = &priv->dwc3;

	dwc3->dev = dev;
	dwc3->maximum_speed = plat->maximum_speed;
	dwc3->dr_mode = plat->dr_mode;
#if CONFIG_IS_ENABLED(OF_CONTROL)
	dwc3_of_parse(dwc3);
#endif

	rc = dwc3_setup_phy(dev, &priv->phys);
	if (rc)
		return rc;

	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;


	rc =  dwc3_init(dwc3);
	if (rc) {
		unmap_physmem(priv->base, MAP_NOCACHE);
		return rc;
	}

	return 0;
}

static int dwc3_generic_remove(struct udevice *dev,
			       struct dwc3_generic_priv *priv)
{
	struct dwc3 *dwc3 = &priv->dwc3;

	dwc3_remove(dwc3);
	dwc3_shutdown_phy(dev, &priv->phys);
	unmap_physmem(dwc3->regs, MAP_NOCACHE);

	return 0;
}

static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
{
	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
	ofnode node = dev->node;

	plat->base = dev_read_addr(dev);

	plat->maximum_speed = usb_get_maximum_speed(node);
	if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
		pr_info("No USB maximum speed specified. Using super speed\n");
		plat->maximum_speed = USB_SPEED_SUPER;
	}

	plat->dr_mode = usb_get_dr_mode(node);
	if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
		pr_err("Invalid usb mode setup\n");
		return -ENODEV;
	}

	return 0;
}

#if CONFIG_IS_ENABLED(DM_USB_GADGET)
int dm_usb_gadget_handle_interrupts(struct udevice *dev)
{
	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	struct dwc3 *dwc3 = &priv->dwc3;

	dwc3_gadget_uboot_handle_interrupt(dwc3);

	return 0;
}

static int dwc3_generic_peripheral_probe(struct udevice *dev)
{
	struct dwc3_generic_priv *priv = dev_get_priv(dev);

	return dwc3_generic_probe(dev, priv);
}

static int dwc3_generic_peripheral_remove(struct udevice *dev)
{
	struct dwc3_generic_priv *priv = dev_get_priv(dev);

	return dwc3_generic_remove(dev, priv);
}

U_BOOT_DRIVER(dwc3_generic_peripheral) = {
	.name	= "dwc3-generic-peripheral",
	.id	= UCLASS_USB_GADGET_GENERIC,
	.ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
	.probe = dwc3_generic_peripheral_probe,
	.remove = dwc3_generic_peripheral_remove,
	.priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
	.platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
};
#endif

#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
static int dwc3_generic_host_probe(struct udevice *dev)
{
	struct xhci_hcor *hcor;
	struct xhci_hccr *hccr;
	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	int rc;

	rc = dwc3_generic_probe(dev, &priv->gen_priv);
	if (rc)
		return rc;

	hccr = (struct xhci_hccr *)priv->gen_priv.base;
	hcor = (struct xhci_hcor *)(priv->gen_priv.base +
			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

	return xhci_register(dev, hccr, hcor);
}

static int dwc3_generic_host_remove(struct udevice *dev)
{
	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	int rc;

	rc = xhci_deregister(dev);
	if (rc)
		return rc;

	return dwc3_generic_remove(dev, &priv->gen_priv);
}

U_BOOT_DRIVER(dwc3_generic_host) = {
	.name	= "dwc3-generic-host",
	.id	= UCLASS_USB,
	.ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
	.probe = dwc3_generic_host_probe,
	.remove = dwc3_generic_host_remove,
	.priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
	.platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
	.ops = &xhci_usb_ops,
	.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif

struct dwc3_glue_data {
	struct clk_bulk		clks;
	struct reset_ctl_bulk	resets;
	fdt_addr_t regs;
};

struct dwc3_glue_ops {
	void (*select_dr_mode)(struct udevice *dev, int index,
			       enum usb_dr_mode mode);
};

void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
			    enum usb_dr_mode mode)
{
#define USBOTGSS_UTMI_OTG_STATUS		0x0084
#define USBOTGSS_UTMI_OTG_OFFSET		0x0480

/* UTMI_OTG_STATUS REGISTER */
#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE	BIT(31)
#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT	BIT(9)
#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
#define USBOTGSS_UTMI_OTG_STATUS_IDDIG		BIT(4)
#define USBOTGSS_UTMI_OTG_STATUS_SESSEND	BIT(3)
#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID	BIT(2)
#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID	BIT(1)
enum dwc3_omap_utmi_mode {
	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
	DWC3_OMAP_UTMI_MODE_HW,
	DWC3_OMAP_UTMI_MODE_SW,
};

	u32 use_id_pin;
	u32 host_mode;
	u32 reg;
	u32 utmi_mode;
	u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;

	struct dwc3_glue_data *glue = dev_get_platdata(dev);
	void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);

	if (device_is_compatible(dev, "ti,am437x-dwc3"))
		utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;

	utmi_mode = dev_read_u32_default(dev, "utmi-mode",
					 DWC3_OMAP_UTMI_MODE_UNKNOWN);
	if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
		debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
		      dev->name);
		mode = USB_DR_MODE_PERIPHERAL;
	}

	switch (mode)  {
	case USB_DR_MODE_PERIPHERAL:
		use_id_pin = 0;
		host_mode = 0;
		break;
	case USB_DR_MODE_HOST:
		use_id_pin = 0;
		host_mode = 1;
		break;
	case USB_DR_MODE_OTG:
	default:
		use_id_pin = 1;
		host_mode = 0;
		break;
	}

	reg = readl(base + utmi_status_offset);

	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
	if (!use_id_pin)
		reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;

	writel(reg, base + utmi_status_offset);

	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND |
		USBOTGSS_UTMI_OTG_STATUS_VBUSVALID |
		USBOTGSS_UTMI_OTG_STATUS_IDDIG);

	reg |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID |
		USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;

	if (!host_mode)
		reg |= USBOTGSS_UTMI_OTG_STATUS_IDDIG |
			USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;

	writel(reg, base + utmi_status_offset);

	unmap_physmem(base, MAP_NOCACHE);
}

struct dwc3_glue_ops ti_ops = {
	.select_dr_mode = dwc3_ti_select_dr_mode,
};

static int dwc3_glue_bind(struct udevice *parent)
{
	ofnode node;
	int ret;

	ofnode_for_each_subnode(node, parent->node) {
		const char *name = ofnode_get_name(node);
		enum usb_dr_mode dr_mode;
		struct udevice *dev;
		const char *driver = NULL;

		debug("%s: subnode name: %s\n", __func__, name);

		dr_mode = usb_get_dr_mode(node);

		switch (dr_mode) {
		case USB_DR_MODE_PERIPHERAL:
		case USB_DR_MODE_OTG:
#if CONFIG_IS_ENABLED(DM_USB_GADGET)
			debug("%s: dr_mode: OTG or Peripheral\n", __func__);
			driver = "dwc3-generic-peripheral";
#endif
			break;
#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
		case USB_DR_MODE_HOST:
			debug("%s: dr_mode: HOST\n", __func__);
			driver = "dwc3-generic-host";
			break;
#endif
		default:
			debug("%s: unsupported dr_mode\n", __func__);
			return -ENODEV;
		};

		if (!driver)
			continue;

		ret = device_bind_driver_to_node(parent, driver, name,
						 node, &dev);
		if (ret) {
			debug("%s: not able to bind usb device mode\n",
			      __func__);
			return ret;
		}
	}

	return 0;
}

static int dwc3_glue_reset_init(struct udevice *dev,
				struct dwc3_glue_data *glue)
{
	int ret;

	ret = reset_get_bulk(dev, &glue->resets);
	if (ret == -ENOTSUPP || ret == -ENOENT)
		return 0;
	else if (ret)
		return ret;

	ret = reset_deassert_bulk(&glue->resets);
	if (ret) {
		reset_release_bulk(&glue->resets);
		return ret;
	}

	return 0;
}

static int dwc3_glue_clk_init(struct udevice *dev,
			      struct dwc3_glue_data *glue)
{
	int ret;

	ret = clk_get_bulk(dev, &glue->clks);
	if (ret == -ENOSYS || ret == -ENOENT)
		return 0;
	if (ret)
		return ret;

#if CONFIG_IS_ENABLED(CLK)
	ret = clk_enable_bulk(&glue->clks);
	if (ret) {
		clk_release_bulk(&glue->clks);
		return ret;
	}
#endif

	return 0;
}

static int dwc3_glue_probe(struct udevice *dev)
{
	struct dwc3_glue_ops *ops = (struct dwc3_glue_ops *)dev_get_driver_data(dev);
	struct dwc3_glue_data *glue = dev_get_platdata(dev);
	struct udevice *child = NULL;
	int index = 0;
	int ret;

	glue->regs = dev_read_addr(dev);

	ret = dwc3_glue_clk_init(dev, glue);
	if (ret)
		return ret;

	ret = dwc3_glue_reset_init(dev, glue);
	if (ret)
		return ret;

	ret = device_find_first_child(dev, &child);
	if (ret)
		return ret;

	while (child) {
		enum usb_dr_mode dr_mode;

		dr_mode = usb_get_dr_mode(child->node);
		device_find_next_child(&child);
		if (ops && ops->select_dr_mode)
			ops->select_dr_mode(dev, index, dr_mode);
		index++;
	}

	return 0;
}

static int dwc3_glue_remove(struct udevice *dev)
{
	struct dwc3_glue_data *glue = dev_get_platdata(dev);

	reset_release_bulk(&glue->resets);

	clk_release_bulk(&glue->clks);

	return 0;
}

static const struct udevice_id dwc3_glue_ids[] = {
	{ .compatible = "xlnx,zynqmp-dwc3" },
	{ .compatible = "xlnx,versal-dwc3" },
	{ .compatible = "ti,keystone-dwc3"},
	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
	{ .compatible = "ti,am654-dwc3" },
	{ }
};

U_BOOT_DRIVER(dwc3_generic_wrapper) = {
	.name	= "dwc3-generic-wrapper",
	.id	= UCLASS_NOP,
	.of_match = dwc3_glue_ids,
	.bind = dwc3_glue_bind,
	.probe = dwc3_glue_probe,
	.remove = dwc3_glue_remove,
	.platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),

};
Commit	Line	Data
22929e12	1	// SPDX-License-Identifier: GPL-2.0
49d67454 MS	2	/*
	3	* Generic DWC3 Glue layer
	4	*
	5	* Copyright (C) 2016 - 2018 Xilinx, Inc.
	6	*
	7	* Based on dwc3-omap.c.
	8	*/
	9
	10	#include <common.h>
1eb69ae4	11	#include <cpu_func.h>
93991cf1	12	#include <asm-generic/io.h>
49d67454 MS	13	#include <dm.h>
	14	#include <dm/device-internal.h>
	15	#include <dm/lists.h>
446e3a20	16	#include <dwc3-uboot.h>
49d67454 MS	17	#include <linux/usb/ch9.h>
	18	#include <linux/usb/gadget.h>
	19	#include <malloc.h>
	20	#include <usb.h>
	21	#include "core.h"
	22	#include "gadget.h"
446e3a20 JJH	23	#include <reset.h>
446e3a20 JJH	24	#include <clk.h>
b575e909	25	#include <usb/xhci.h>
49d67454	26
3a38a0ad JJH	27	struct dwc3_generic_plat {
	28	fdt_addr_t base;
	29	u32 maximum_speed;
	30	enum usb_dr_mode dr_mode;
	31	};
	32
3a38a0ad	33	struct dwc3_generic_priv {
1af590df	34	void *base;
446e3a20	35	struct dwc3 dwc3;
6dfb8a80	36	struct phy_bulk phys;
446e3a20 JJH	37	};
446e3a20 JJH	38
b575e909 JJH	39	struct dwc3_generic_host_priv {
	40	struct xhci_ctrl xhci_ctrl;
	41	struct dwc3_generic_priv gen_priv;
	42	};
	43
1af590df JJH	44	static int dwc3_generic_probe(struct udevice *dev,
1af590df JJH	45	struct dwc3_generic_priv *priv)
49d67454	46	{
446e3a20	47	int rc;
3a38a0ad	48	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
446e3a20 JJH	49	struct dwc3 *dwc3 = &priv->dwc3;
446e3a20 JJH	50
ba6c5f7a	51	dwc3->dev = dev;
3a38a0ad JJH	52	dwc3->maximum_speed = plat->maximum_speed;
3a38a0ad JJH	53	dwc3->dr_mode = plat->dr_mode;
ba6c5f7a JJH	54	#if CONFIG_IS_ENABLED(OF_CONTROL)
	55	dwc3_of_parse(dwc3);
	56	#endif
3a38a0ad	57
6dfb8a80	58	rc = dwc3_setup_phy(dev, &priv->phys);
446e3a20 JJH	59	if (rc)
	60	return rc;
	61
1af590df JJH	62	priv->base = map_physmem(plat->base, DWC3_OTG_REGS_END, MAP_NOCACHE);
1af590df JJH	63	dwc3->regs = priv->base + DWC3_GLOBALS_REGS_START;
ba6c5f7a	64
446e3a20 JJH	65
	66	rc = dwc3_init(dwc3);
	67	if (rc) {
1af590df	68	unmap_physmem(priv->base, MAP_NOCACHE);
446e3a20 JJH	69	return rc;
446e3a20 JJH	70	}
49d67454	71
446e3a20	72	return 0;
49d67454 MS	73	}
49d67454 MS	74
1af590df JJH	75	static int dwc3_generic_remove(struct udevice *dev,
1af590df JJH	76	struct dwc3_generic_priv *priv)
49d67454	77	{
446e3a20	78	struct dwc3 *dwc3 = &priv->dwc3;
49d67454	79
446e3a20	80	dwc3_remove(dwc3);
6dfb8a80	81	dwc3_shutdown_phy(dev, &priv->phys);
446e3a20	82	unmap_physmem(dwc3->regs, MAP_NOCACHE);
49d67454 MS	83
	84	return 0;
	85	}
	86
1af590df	87	static int dwc3_generic_ofdata_to_platdata(struct udevice *dev)
49d67454	88	{
3a38a0ad	89	struct dwc3_generic_plat *plat = dev_get_platdata(dev);
ac28e59a	90	ofnode node = dev->node;
49d67454	91
ac28e59a	92	plat->base = dev_read_addr(dev);
49d67454	93
3a38a0ad JJH	94	plat->maximum_speed = usb_get_maximum_speed(node);
3a38a0ad JJH	95	if (plat->maximum_speed == USB_SPEED_UNKNOWN) {
1a63e5e5 JJH	96	pr_info("No USB maximum speed specified. Using super speed\n");
1a63e5e5 JJH	97	plat->maximum_speed = USB_SPEED_SUPER;
49d67454 MS	98	}
49d67454 MS	99
3a38a0ad JJH	100	plat->dr_mode = usb_get_dr_mode(node);
3a38a0ad JJH	101	if (plat->dr_mode == USB_DR_MODE_UNKNOWN) {
49d67454 MS	102	pr_err("Invalid usb mode setup\n");
	103	return -ENODEV;
	104	}
	105
	106	return 0;
	107	}
	108
1af590df JJH	109	#if CONFIG_IS_ENABLED(DM_USB_GADGET)
	110	int dm_usb_gadget_handle_interrupts(struct udevice *dev)
	111	{
	112	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	113	struct dwc3 *dwc3 = &priv->dwc3;
	114
	115	dwc3_gadget_uboot_handle_interrupt(dwc3);
	116
	117	return 0;
	118	}
	119
	120	static int dwc3_generic_peripheral_probe(struct udevice *dev)
	121	{
	122	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	123
	124	return dwc3_generic_probe(dev, priv);
	125	}
	126
	127	static int dwc3_generic_peripheral_remove(struct udevice *dev)
	128	{
	129	struct dwc3_generic_priv *priv = dev_get_priv(dev);
	130
	131	return dwc3_generic_remove(dev, priv);
	132	}
	133
49d67454 MS	134	U_BOOT_DRIVER(dwc3_generic_peripheral) = {
49d67454 MS	135	.name = "dwc3-generic-peripheral",
01311624	136	.id = UCLASS_USB_GADGET_GENERIC,
1af590df	137	.ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
49d67454 MS	138	.probe = dwc3_generic_peripheral_probe,
49d67454 MS	139	.remove = dwc3_generic_peripheral_remove,
3a38a0ad JJH	140	.priv_auto_alloc_size = sizeof(struct dwc3_generic_priv),
3a38a0ad JJH	141	.platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
49d67454	142	};
687ab545	143	#endif
49d67454	144
b575e909 JJH	145	#if defined(CONFIG_SPL_USB_HOST_SUPPORT) \|\| !defined(CONFIG_SPL_BUILD)
	146	static int dwc3_generic_host_probe(struct udevice *dev)
	147	{
	148	struct xhci_hcor *hcor;
	149	struct xhci_hccr *hccr;
	150	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	151	int rc;
	152
	153	rc = dwc3_generic_probe(dev, &priv->gen_priv);
	154	if (rc)
	155	return rc;
	156
	157	hccr = (struct xhci_hccr *)priv->gen_priv.base;
	158	hcor = (struct xhci_hcor *)(priv->gen_priv.base +
	159	HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
	160
	161	return xhci_register(dev, hccr, hcor);
	162	}
	163
	164	static int dwc3_generic_host_remove(struct udevice *dev)
	165	{
	166	struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
	167	int rc;
	168
	169	rc = xhci_deregister(dev);
	170	if (rc)
	171	return rc;
	172
	173	return dwc3_generic_remove(dev, &priv->gen_priv);
	174	}
	175
	176	U_BOOT_DRIVER(dwc3_generic_host) = {
	177	.name = "dwc3-generic-host",
	178	.id = UCLASS_USB,
	179	.ofdata_to_platdata = dwc3_generic_ofdata_to_platdata,
	180	.probe = dwc3_generic_host_probe,
	181	.remove = dwc3_generic_host_remove,
	182	.priv_auto_alloc_size = sizeof(struct dwc3_generic_host_priv),
	183	.platdata_auto_alloc_size = sizeof(struct dwc3_generic_plat),
	184	.ops = &xhci_usb_ops,
	185	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	186	};
	187	#endif
	188
446e3a20 JJH	189	struct dwc3_glue_data {
	190	struct clk_bulk clks;
	191	struct reset_ctl_bulk resets;
93991cf1 JJH	192	fdt_addr_t regs;
	193	};
	194
	195	struct dwc3_glue_ops {
	196	void (select_dr_mode)(struct udevice dev, int index,
	197	enum usb_dr_mode mode);
446e3a20 JJH	198	};
446e3a20 JJH	199
d66e54ac JJH	200	void dwc3_ti_select_dr_mode(struct udevice *dev, int index,
	201	enum usb_dr_mode mode)
	202	{
	203	#define USBOTGSS_UTMI_OTG_STATUS 0x0084
	204	#define USBOTGSS_UTMI_OTG_OFFSET 0x0480
	205
	206	/* UTMI_OTG_STATUS REGISTER */
	207	#define USBOTGSS_UTMI_OTG_STATUS_SW_MODE BIT(31)
	208	#define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT BIT(9)
	209	#define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE BIT(8)
	210	#define USBOTGSS_UTMI_OTG_STATUS_IDDIG BIT(4)
	211	#define USBOTGSS_UTMI_OTG_STATUS_SESSEND BIT(3)
	212	#define USBOTGSS_UTMI_OTG_STATUS_SESSVALID BIT(2)
	213	#define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID BIT(1)
	214	enum dwc3_omap_utmi_mode {
	215	DWC3_OMAP_UTMI_MODE_UNKNOWN = 0,
	216	DWC3_OMAP_UTMI_MODE_HW,
	217	DWC3_OMAP_UTMI_MODE_SW,
	218	};
	219
	220	u32 use_id_pin;
	221	u32 host_mode;
	222	u32 reg;
	223	u32 utmi_mode;
	224	u32 utmi_status_offset = USBOTGSS_UTMI_OTG_STATUS;
	225
	226	struct dwc3_glue_data *glue = dev_get_platdata(dev);
	227	void *base = map_physmem(glue->regs, 0x10000, MAP_NOCACHE);
	228
	229	if (device_is_compatible(dev, "ti,am437x-dwc3"))
	230	utmi_status_offset += USBOTGSS_UTMI_OTG_OFFSET;
	231
	232	utmi_mode = dev_read_u32_default(dev, "utmi-mode",
	233	DWC3_OMAP_UTMI_MODE_UNKNOWN);
	234	if (utmi_mode != DWC3_OMAP_UTMI_MODE_HW) {
	235	debug("%s: OTG is not supported. defaulting to PERIPHERAL\n",
	236	dev->name);
	237	mode = USB_DR_MODE_PERIPHERAL;
	238	}
	239
	240	switch (mode) {
	241	case USB_DR_MODE_PERIPHERAL:
	242	use_id_pin = 0;
	243	host_mode = 0;
	244	break;
	245	case USB_DR_MODE_HOST:
	246	use_id_pin = 0;
	247	host_mode = 1;
	248	break;
	249	case USB_DR_MODE_OTG:
	250	default:
	251	use_id_pin = 1;
	252	host_mode = 0;
	253	break;
	254	}
	255
	256	reg = readl(base + utmi_status_offset);
	257
	258	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SW_MODE);
	259	if (!use_id_pin)
	260	reg \|= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
	261
	262	writel(reg, base + utmi_status_offset);
	263
264	reg &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSEND \|
265	USBOTGSS_UTMI_OTG_STATUS_VBUSVALID \|
266	USBOTGSS_UTMI_OTG_STATUS_IDDIG);
267
268	reg \|= USBOTGSS_UTMI_OTG_STATUS_SESSVALID \|
269	USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
270
271	if (!host_mode)
272	reg \|= USBOTGSS_UTMI_OTG_STATUS_IDDIG \|
273	USBOTGSS_UTMI_OTG_STATUS_VBUSVALID;
274
275	writel(reg, base + utmi_status_offset);
276
277	unmap_physmem(base, MAP_NOCACHE);
278	}
279
280	struct dwc3_glue_ops ti_ops = {
281	.select_dr_mode = dwc3_ti_select_dr_mode,
282	};
283
446e3a20	284	static int dwc3_glue_bind(struct udevice *parent)
49d67454	285	{
ac28e59a	286	ofnode node;
49d67454 MS	287	int ret;
49d67454 MS	288
ac28e59a KY	289	ofnode_for_each_subnode(node, parent->node) {
ac28e59a KY	290	const char *name = ofnode_get_name(node);
49d67454 MS	291	enum usb_dr_mode dr_mode;
49d67454 MS	292	struct udevice *dev;
446e3a20	293	const char *driver = NULL;
49d67454 MS	294
49d67454 MS	295	debug("%s: subnode name: %s\n", __func__, name);
49d67454 MS	296
	297	dr_mode = usb_get_dr_mode(node);
	298
	299	switch (dr_mode) {
	300	case USB_DR_MODE_PERIPHERAL:
	301	case USB_DR_MODE_OTG:
446e3a20	302	#if CONFIG_IS_ENABLED(DM_USB_GADGET)
49d67454 MS	303	debug("%s: dr_mode: OTG or Peripheral\n", __func__);
49d67454 MS	304	driver = "dwc3-generic-peripheral";
446e3a20	305	#endif
49d67454	306	break;
b575e909	307	#if defined(CONFIG_SPL_USB_HOST_SUPPORT) \|\| !defined(CONFIG_SPL_BUILD)
49d67454 MS	308	case USB_DR_MODE_HOST:
49d67454 MS	309	debug("%s: dr_mode: HOST\n", __func__);
b575e909	310	driver = "dwc3-generic-host";
49d67454	311	break;
b575e909	312	#endif
49d67454 MS	313	default:
	314	debug("%s: unsupported dr_mode\n", __func__);
	315	return -ENODEV;
	316	};
	317
446e3a20 JJH	318	if (!driver)
	319	continue;
	320
49d67454	321	ret = device_bind_driver_to_node(parent, driver, name,
ac28e59a	322	node, &dev);
49d67454 MS	323	if (ret) {
	324	debug("%s: not able to bind usb device mode\n",
	325	__func__);
	326	return ret;
	327	}
	328	}
	329
	330	return 0;
	331	}
	332
446e3a20 JJH	333	static int dwc3_glue_reset_init(struct udevice *dev,
	334	struct dwc3_glue_data *glue)
	335	{
	336	int ret;
	337
	338	ret = reset_get_bulk(dev, &glue->resets);
d624434f	339	if (ret == -ENOTSUPP \|\| ret == -ENOENT)
446e3a20 JJH	340	return 0;
	341	else if (ret)
	342	return ret;
	343
	344	ret = reset_deassert_bulk(&glue->resets);
	345	if (ret) {
	346	reset_release_bulk(&glue->resets);
	347	return ret;
	348	}
	349
	350	return 0;
	351	}
	352
	353	static int dwc3_glue_clk_init(struct udevice *dev,
	354	struct dwc3_glue_data *glue)
	355	{
	356	int ret;
	357
	358	ret = clk_get_bulk(dev, &glue->clks);
d624434f	359	if (ret == -ENOSYS \|\| ret == -ENOENT)
446e3a20 JJH	360	return 0;
	361	if (ret)
	362	return ret;
	363
	364	#if CONFIG_IS_ENABLED(CLK)
	365	ret = clk_enable_bulk(&glue->clks);
	366	if (ret) {
	367	clk_release_bulk(&glue->clks);
	368	return ret;
	369	}
	370	#endif
	371
	372	return 0;
	373	}
	374
	375	static int dwc3_glue_probe(struct udevice *dev)
	376	{
93991cf1	377	struct dwc3_glue_ops ops = (struct dwc3_glue_ops )dev_get_driver_data(dev);
446e3a20	378	struct dwc3_glue_data *glue = dev_get_platdata(dev);
93991cf1 JJH	379	struct udevice *child = NULL;
93991cf1 JJH	380	int index = 0;
446e3a20 JJH	381	int ret;
446e3a20 JJH	382
93991cf1 JJH	383	glue->regs = dev_read_addr(dev);
93991cf1 JJH	384
446e3a20 JJH	385	ret = dwc3_glue_clk_init(dev, glue);
	386	if (ret)
	387	return ret;
	388
	389	ret = dwc3_glue_reset_init(dev, glue);
	390	if (ret)
	391	return ret;
	392
93991cf1 JJH	393	ret = device_find_first_child(dev, &child);
	394	if (ret)
	395	return ret;
	396
	397	while (child) {
	398	enum usb_dr_mode dr_mode;
	399
ac28e59a	400	dr_mode = usb_get_dr_mode(child->node);
93991cf1 JJH	401	device_find_next_child(&child);
	402	if (ops && ops->select_dr_mode)
	403	ops->select_dr_mode(dev, index, dr_mode);
	404	index++;
	405	}
	406
446e3a20 JJH	407	return 0;
	408	}
	409
	410	static int dwc3_glue_remove(struct udevice *dev)
	411	{
	412	struct dwc3_glue_data *glue = dev_get_platdata(dev);
	413
	414	reset_release_bulk(&glue->resets);
	415
	416	clk_release_bulk(&glue->clks);
	417
e445d466	418	return 0;
446e3a20 JJH	419	}
	420
	421	static const struct udevice_id dwc3_glue_ids[] = {
49d67454	422	{ .compatible = "xlnx,zynqmp-dwc3" },
648856ac	423	{ .compatible = "xlnx,versal-dwc3" },
1c03ade3	424	{ .compatible = "ti,keystone-dwc3"},
d66e54ac	425	{ .compatible = "ti,dwc3", .data = (ulong)&ti_ops },
1ce5f1f9	426	{ .compatible = "ti,am437x-dwc3", .data = (ulong)&ti_ops },
cab4e275	427	{ .compatible = "ti,am654-dwc3" },
49d67454 MS	428	{ }
	429	};
	430
	431	U_BOOT_DRIVER(dwc3_generic_wrapper) = {
	432	.name = "dwc3-generic-wrapper",
3b83829e	433	.id = UCLASS_NOP,
446e3a20 JJH	434	.of_match = dwc3_glue_ids,
	435	.bind = dwc3_glue_bind,
	436	.probe = dwc3_glue_probe,
	437	.remove = dwc3_glue_remove,
	438	.platdata_auto_alloc_size = sizeof(struct dwc3_glue_data),
	439
49d67454	440	};