[J-u-boot.git] / nand_spl / nand_boot_fsl_nfc.c

/*
 * (C) Copyright 2009
 * Magnus Lilja <lilja.magnus@gmail.com>
 *
 * (C) Copyright 2008
 * Maxim Artamonov, <scn1874 at yandex.ru>
 *
 * (C) Copyright 2006-2008
 * Stefan Roese, DENX Software Engineering, sr at denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <nand.h>
#ifdef CONFIG_MX31
#include <asm/arch/mx31-regs.h>
#else
#include <asm/arch/imx-regs.h>
#endif
#include <asm/io.h>
#include <fsl_nfc.h>

static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR;

static void nfc_wait_ready(void)
{
	uint32_t tmp;

	while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
		;

	/* Reset interrupt flag */
	tmp = readw(&nfc->nand_flash_config2);
	tmp &= ~NFC_INT;
	writew(tmp, &nfc->nand_flash_config2);
}

void nfc_nand_init(void)
{
#if defined(MXC_NFC_V1_1)
	int ecc_per_page  = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	int config1;

	writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);

	/* unlocking RAM Buff */
	writew(0x2, &nfc->configuration);

	/* hardware ECC checking and correct */
	config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800;
	/*
	 * if spare size is larger that 16 bytes per 512 byte hunk
	 * then use 8 symbol correction instead of 4
	 */
	if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16)
		config1 &= ~NFC_4_8N_ECC;
	else
		config1 |= NFC_4_8N_ECC;
	writew(config1, &nfc->nand_flash_config1);
#elif defined(MXC_NFC_V1)
	/* unlocking RAM Buff */
	writew(0x2, &nfc->configuration);

	/* hardware ECC checking and correct */
	writew(NFC_ECC_EN, &nfc->nand_flash_config1);
#endif
}

static void nfc_nand_command(unsigned short command)
{
	writew(command, &nfc->flash_cmd);
	writew(NFC_CMD, &nfc->nand_flash_config2);
	nfc_wait_ready();
}

static void nfc_nand_page_address(unsigned int page_address)
{
	unsigned int page_count;

	writew(0x00, &nfc->flash_add);
	writew(NFC_ADDR, &nfc->nand_flash_config2);
	nfc_wait_ready();

	/* code only for large page flash */
	if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
		writew(0x00, &nfc->flash_add);
		writew(NFC_ADDR, &nfc->nand_flash_config2);
		nfc_wait_ready();
	}

	page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;

	if (page_address <= page_count) {
		page_count--; /* transform 0x01000000 to 0x00ffffff */
		do {
			writew(page_address & 0xff, &nfc->flash_add);
			writew(NFC_ADDR, &nfc->nand_flash_config2);
			nfc_wait_ready();
			page_address = page_address >> 8;
			page_count = page_count >> 8;
		} while (page_count);
	}

	writew(0x00, &nfc->flash_add);
	writew(NFC_ADDR, &nfc->nand_flash_config2);
	nfc_wait_ready();
}

static void nfc_nand_data_output(void)
{
	int config1 = readw(&nfc->nand_flash_config1);
#ifdef NAND_MXC_2K_MULTI_CYCLE
	int i;
#endif

	config1 |= NFC_ECC_EN | NFC_INT_MSK;
	writew(config1, &nfc->nand_flash_config1);
	writew(0, &nfc->buffer_address);
	writew(NFC_OUTPUT, &nfc->nand_flash_config2);
	nfc_wait_ready();
#ifdef NAND_MXC_2K_MULTI_CYCLE
	/*
	 * This NAND controller requires multiple input commands
	 * for pages larger than 512 bytes.
	 */
	for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
		config1 = readw(&nfc->nand_flash_config1);
		config1 |= NFC_ECC_EN | NFC_INT_MSK;
		writew(config1, &nfc->nand_flash_config1);
		writew(i, &nfc->buffer_address);
		writew(NFC_OUTPUT, &nfc->nand_flash_config2);
		nfc_wait_ready();
	}
#endif
}

static int nfc_nand_check_ecc(void)
{
	return readw(&nfc->ecc_status_result);
}

static int nfc_read_page(unsigned int page_address, unsigned char *buf)
{
	int i;
	u32 *src;
	u32 *dst;

	writew(0, &nfc->buffer_address); /* read in first 0 buffer */
	nfc_nand_command(NAND_CMD_READ0);
	nfc_nand_page_address(page_address);

	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
		nfc_nand_command(NAND_CMD_READSTART);

	nfc_nand_data_output(); /* fill the main buffer 0 */

	if (nfc_nand_check_ecc())
		return -1;

	src = &nfc->main_area[0][0];
	dst = (u32 *)buf;

	/* main copy loop from NAND-buffer to SDRAM memory */
	for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
		writel(readl(src), dst);
		src++;
		dst++;
	}

	return 0;
}

static int is_badblock(int pagenumber)
{
	int page = pagenumber;
	u32 badblock;
	u32 *src;

	/* Check the first two pages for bad block markers */
	for (page = pagenumber; page < pagenumber + 2; page++) {
		writew(0, &nfc->buffer_address); /* read in first 0 buffer */
		nfc_nand_command(NAND_CMD_READ0);
		nfc_nand_page_address(page);

		if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
			nfc_nand_command(NAND_CMD_READSTART);

		nfc_nand_data_output(); /* fill the main buffer 0 */

		src = &nfc->spare_area[0][0];

		/*
		 * IMPORTANT NOTE: The nand flash controller uses a non-
		 * standard layout for large page devices. This can
		 * affect the position of the bad block marker.
		 */
		/* Get the bad block marker */
		badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
		badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
		badblock &= 0xff;

		/* bad block marker verify */
		if (badblock != 0xff)
			return 1; /* potential bad block */
	}

	return 0;
}

static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
{
	int i;
	unsigned int page;
	unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
				CONFIG_SYS_NAND_PAGE_SIZE;

	nfc_nand_init();

	/* Convert to page number */
	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
	i = 0;

	while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
		if (nfc_read_page(page, buf) < 0)
			return -1;

		page++;
		i++;
		buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;

		/*
		 * Check if we have crossed a block boundary, and if so
		 * check for bad block.
		 */
		if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
			/*
			 * Yes, new block. See if this block is good. If not,
			 * loop until we find a good block.
			 */
			while (is_badblock(page)) {
				page = page + CONFIG_SYS_NAND_PAGE_COUNT;
				/* Check i we've reached the end of flash. */
				if (page >= maxpages)
					return -1;
			}
		}
	}

	return 0;
}

/*
 * The main entry for NAND booting. It's necessary that SDRAM is already
 * configured and available since this code loads the main U-Boot image
 * from NAND into SDRAM and starts it from there.
 */
void nand_boot(void)
{
	__attribute__((noreturn)) void (*uboot)(void);

	/*
	 * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
	 * be aligned to full pages
	 */
	if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
		       (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
		/* Copy from NAND successful, start U-boot */
		uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
		uboot();
	} else {
		/* Unrecoverable error when copying from NAND */
		hang();
	}
}

/*
 * Called in case of an exception.
 */
void hang(void)
{
	/* Loop forever */
	while (1) ;
}
Commit	Line	Data
40c642bc ML	1	/*
	2	* (C) Copyright 2009
	3	* Magnus Lilja <lilja.magnus@gmail.com>
	4	*
	5	* (C) Copyright 2008
	6	* Maxim Artamonov, <scn1874 at yandex.ru>
	7	*
	8	* (C) Copyright 2006-2008
	9	* Stefan Roese, DENX Software Engineering, sr at denx.de.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <nand.h>
f3bb63a3	29	#ifdef CONFIG_MX31
61f2b38a	30	#include <asm/arch/mx31-regs.h>
f3bb63a3	31	#else
61f2b38a	32	#include <asm/arch/imx-regs.h>
f3bb63a3	33	#endif
40c642bc ML	34	#include <asm/io.h>
	35	#include <fsl_nfc.h>
	36
4fff329d	37	static struct fsl_nfc_regs const nfc = (void )NFC_BASE_ADDR;
40c642bc ML	38
	39	static void nfc_wait_ready(void)
	40	{
	41	uint32_t tmp;
	42
	43	while (!(readw(&nfc->nand_flash_config2) & NFC_INT))
	44	;
	45
	46	/* Reset interrupt flag */
	47	tmp = readw(&nfc->nand_flash_config2);
	48	tmp &= ~NFC_INT;
	49	writew(tmp, &nfc->nand_flash_config2);
	50	}
	51
f3bb63a3	52	void nfc_nand_init(void)
40c642bc	53	{
f3bb63a3 JR	54	#if defined(MXC_NFC_V1_1)
	55	int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512;
	56	int config1;
	57
	58	writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
	59
	60	/* unlocking RAM Buff */
	61	writew(0x2, &nfc->configuration);
	62
	63	/* hardware ECC checking and correct */
	64	config1 = readw(&nfc->nand_flash_config1) \| NFC_ECC_EN \| 0x800;
	65	/*
	66	* if spare size is larger that 16 bytes per 512 byte hunk
	67	* then use 8 symbol correction instead of 4
	68	*/
	69	if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16)
	70	config1 &= ~NFC_4_8N_ECC;
	71	else
	72	config1 \|= NFC_4_8N_ECC;
	73	writew(config1, &nfc->nand_flash_config1);
	74	#elif defined(MXC_NFC_V1)
40c642bc ML	75	/* unlocking RAM Buff */
	76	writew(0x2, &nfc->configuration);
	77
	78	/* hardware ECC checking and correct */
	79	writew(NFC_ECC_EN, &nfc->nand_flash_config1);
f3bb63a3	80	#endif
40c642bc ML	81	}
	82
	83	static void nfc_nand_command(unsigned short command)
	84	{
	85	writew(command, &nfc->flash_cmd);
	86	writew(NFC_CMD, &nfc->nand_flash_config2);
	87	nfc_wait_ready();
	88	}
	89
	90	static void nfc_nand_page_address(unsigned int page_address)
	91	{
	92	unsigned int page_count;
	93
f3bb63a3	94	writew(0x00, &nfc->flash_add);
40c642bc ML	95	writew(NFC_ADDR, &nfc->nand_flash_config2);
	96	nfc_wait_ready();
	97
f3bb63a3 JR	98	/* code only for large page flash */
f3bb63a3 JR	99	if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
40c642bc ML	100	writew(0x00, &nfc->flash_add);
	101	writew(NFC_ADDR, &nfc->nand_flash_config2);
	102	nfc_wait_ready();
	103	}
	104
	105	page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE;
	106
	107	if (page_address <= page_count) {
	108	page_count--; /* transform 0x01000000 to 0x00ffffff */
	109	do {
	110	writew(page_address & 0xff, &nfc->flash_add);
	111	writew(NFC_ADDR, &nfc->nand_flash_config2);
	112	nfc_wait_ready();
	113	page_address = page_address >> 8;
	114	page_count = page_count >> 8;
	115	} while (page_count);
	116	}
f3bb63a3 JR	117
	118	writew(0x00, &nfc->flash_add);
	119	writew(NFC_ADDR, &nfc->nand_flash_config2);
	120	nfc_wait_ready();
40c642bc ML	121	}
	122
	123	static void nfc_nand_data_output(void)
	124	{
f3bb63a3 JR	125	int config1 = readw(&nfc->nand_flash_config1);
f3bb63a3 JR	126	#ifdef NAND_MXC_2K_MULTI_CYCLE
40c642bc	127	int i;
f3bb63a3	128	#endif
40c642bc	129
f3bb63a3 JR	130	config1 \|= NFC_ECC_EN \| NFC_INT_MSK;
	131	writew(config1, &nfc->nand_flash_config1);
	132	writew(0, &nfc->buffer_address);
	133	writew(NFC_OUTPUT, &nfc->nand_flash_config2);
	134	nfc_wait_ready();
	135	#ifdef NAND_MXC_2K_MULTI_CYCLE
40c642bc	136	/*
f3bb63a3 JR	137	* This NAND controller requires multiple input commands
f3bb63a3 JR	138	* for pages larger than 512 bytes.
40c642bc	139	*/
f3bb63a3 JR	140	for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
	141	config1 = readw(&nfc->nand_flash_config1);
	142	config1 \|= NFC_ECC_EN \| NFC_INT_MSK;
	143	writew(config1, &nfc->nand_flash_config1);
	144	writew(i, &nfc->buffer_address);
40c642bc ML	145	writew(NFC_OUTPUT, &nfc->nand_flash_config2);
	146	nfc_wait_ready();
	147	}
f3bb63a3	148	#endif
40c642bc ML	149	}
	150
	151	static int nfc_nand_check_ecc(void)
	152	{
	153	return readw(&nfc->ecc_status_result);
	154	}
	155
	156	static int nfc_read_page(unsigned int page_address, unsigned char *buf)
	157	{
	158	int i;
	159	u32 *src;
	160	u32 *dst;
	161
	162	writew(0, &nfc->buffer_address); /* read in first 0 buffer */
	163	nfc_nand_command(NAND_CMD_READ0);
	164	nfc_nand_page_address(page_address);
	165
f3bb63a3	166	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
40c642bc ML	167	nfc_nand_command(NAND_CMD_READSTART);
	168
	169	nfc_nand_data_output(); /* fill the main buffer 0 */
	170
	171	if (nfc_nand_check_ecc())
	172	return -1;
	173
f3bb63a3	174	src = &nfc->main_area[0][0];
40c642bc ML	175	dst = (u32 *)buf;
	176
	177	/* main copy loop from NAND-buffer to SDRAM memory */
	178	for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) {
	179	writel(readl(src), dst);
	180	src++;
	181	dst++;
	182	}
	183
	184	return 0;
	185	}
	186
	187	static int is_badblock(int pagenumber)
	188	{
	189	int page = pagenumber;
	190	u32 badblock;
	191	u32 *src;
	192
	193	/* Check the first two pages for bad block markers */
	194	for (page = pagenumber; page < pagenumber + 2; page++) {
	195	writew(0, &nfc->buffer_address); /* read in first 0 buffer */
	196	nfc_nand_command(NAND_CMD_READ0);
	197	nfc_nand_page_address(page);
	198
f3bb63a3	199	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
40c642bc ML	200	nfc_nand_command(NAND_CMD_READSTART);
	201
	202	nfc_nand_data_output(); /* fill the main buffer 0 */
	203
f3bb63a3	204	src = &nfc->spare_area[0][0];
40c642bc ML	205
	206	/*
	207	* IMPORTANT NOTE: The nand flash controller uses a non-
	208	* standard layout for large page devices. This can
	209	* affect the position of the bad block marker.
	210	*/
	211	/* Get the bad block marker */
	212	badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]);
	213	badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4);
	214	badblock &= 0xff;
	215
	216	/* bad block marker verify */
	217	if (badblock != 0xff)
	218	return 1; /* potential bad block */
	219	}
	220
	221	return 0;
	222	}
	223
	224	static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
	225	{
	226	int i;
	227	unsigned int page;
	228	unsigned int maxpages = CONFIG_SYS_NAND_SIZE /
	229	CONFIG_SYS_NAND_PAGE_SIZE;
	230
40c642bc ML	231	nfc_nand_init();
	232
	233	/* Convert to page number */
	234	page = from / CONFIG_SYS_NAND_PAGE_SIZE;
	235	i = 0;
	236
	237	while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) {
	238	if (nfc_read_page(page, buf) < 0)
	239	return -1;
	240
	241	page++;
	242	i++;
	243	buf = buf + CONFIG_SYS_NAND_PAGE_SIZE;
	244
	245	/*
	246	* Check if we have crossed a block boundary, and if so
	247	* check for bad block.
	248	*/
	249	if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
	250	/*
	251	* Yes, new block. See if this block is good. If not,
f3bb63a3	252	* loop until we find a good block.
40c642bc ML	253	*/
	254	while (is_badblock(page)) {
	255	page = page + CONFIG_SYS_NAND_PAGE_COUNT;
	256	/* Check i we've reached the end of flash. */
	257	if (page >= maxpages)
	258	return -1;
	259	}
	260	}
	261	}
	262
	263	return 0;
	264	}
	265
	266	/*
	267	* The main entry for NAND booting. It's necessary that SDRAM is already
	268	* configured and available since this code loads the main U-Boot image
	269	* from NAND into SDRAM and starts it from there.
	270	*/
	271	void nand_boot(void)
	272	{
	273	__attribute__((noreturn)) void (*uboot)(void);
	274
40c642bc ML	275	/*
	276	* CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must
	277	* be aligned to full pages
	278	*/
	279	if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
	280	(uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) {
	281	/* Copy from NAND successful, start U-boot */
	282	uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
	283	uboot();
	284	} else {
	285	/* Unrecoverable error when copying from NAND */
	286	hang();
	287	}
	288	}
	289
	290	/*
	291	* Called in case of an exception.
	292	*/
	293	void hang(void)
	294	{
	295	/* Loop forever */
	296	while (1) ;
	297	}