[J-u-boot.git] / board / dhelectronics / dh_imx6 / dh_imx6.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * DHCOM DH-iMX6 PDK board support
 *
 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
 */

#include <common.h>
#include <dm.h>
#include <eeprom.h>
#include <image.h>
#include <init.h>
#include <net.h>
#include <dm/device-internal.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <ahci.h>
#include <dwc_ahsata.h>
#include <env.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c_eeprom.h>
#include <mmc.h>
#include <usb.h>
#include <usb/ehci-ci.h>

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	gd->ram_size = imx_ddr_size();
	return 0;
}

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

static int setup_fec_clock(void)
{
	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* set gpr1[21] to select anatop clock */
	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);

	return enable_fec_anatop_clock(0, ENET_50MHZ);
}

#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
	/*
	 * Set daisy chain for otg_pin_id on MX6Q.
	 * For MX6DL, this bit is reserved.
	 */
	imx_iomux_set_gpr_register(1, 13, 1, 0);
}

int board_usb_phy_mode(int port)
{
	if (port == 1)
		return USB_INIT_HOST;
	else
		return USB_INIT_DEVICE;
}
#endif

static int setup_dhcom_mac_from_fuse(void)
{
	struct udevice *dev;
	ofnode eeprom;
	unsigned char enetaddr[6];
	int ret;

	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
	if (ret)	/* ethaddr is already set */
		return 0;

	imx_get_mac_from_fuse(0, enetaddr);

	if (is_valid_ethaddr(enetaddr)) {
		eth_env_set_enetaddr("ethaddr", enetaddr);
		return 0;
	}

	eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
	if (!ofnode_valid(eeprom)) {
		printf("Invalid hardware path to EEPROM!\n");
		return -ENODEV;
	}

	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
	if (ret) {
		printf("Cannot find EEPROM!\n");
		return ret;
	}

	ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
	if (ret) {
		printf("Error reading configuration EEPROM!\n");
		return ret;
	}

	if (is_valid_ethaddr(enetaddr))
		eth_env_set_enetaddr("ethaddr", enetaddr);

	return 0;
}

int board_early_init_f(void)
{
#ifdef CONFIG_USB_EHCI_MX6
	setup_usb();
#endif

	return 0;
}

int board_init(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

	/* Enable eim_slow clocks */
	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);

	setup_dhcom_mac_from_fuse();

	setup_fec_clock();

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	/* 8 bit bus width */
	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

#define HW_CODE_BIT_0	IMX_GPIO_NR(2, 19)
#define HW_CODE_BIT_1	IMX_GPIO_NR(6, 6)
#define HW_CODE_BIT_2	IMX_GPIO_NR(2, 16)

static int board_get_hwcode(void)
{
	int hw_code;

	gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
	gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
	gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");

	gpio_direction_input(HW_CODE_BIT_0);
	gpio_direction_input(HW_CODE_BIT_1);
	gpio_direction_input(HW_CODE_BIT_2);

	/* HW 100 + HW 200 = 00b; HW 300 = 01b */
	hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
		   (gpio_get_value(HW_CODE_BIT_1) << 1) |
		    gpio_get_value(HW_CODE_BIT_0)) + 2;

	return hw_code;
}

int board_late_init(void)
{
	u32 hw_code;
	char buf[16];

	hw_code = board_get_hwcode();

	switch (get_cpu_type()) {
	case MXC_CPU_MX6SOLO:
		snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
		break;
	case MXC_CPU_MX6DL:
		snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
		break;
	case MXC_CPU_MX6D:
		snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
		break;
	case MXC_CPU_MX6Q:
		snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
		break;
	default:
		snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
		break;
	}

	env_set("dhcom", buf);

#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif
	return 0;
}

int checkboard(void)
{
	puts("Board: DHCOM i.MX6\n");
	return 0;
}

#ifdef CONFIG_MULTI_DTB_FIT
int board_fit_config_name_match(const char *name)
{
	if (is_mx6dq()) {
		if (!strcmp(name, "imx6q-dhcom-pdk2"))
			return 0;
	} else if (is_mx6sdl()) {
		if (!strcmp(name, "imx6dl-dhcom-pdk2"))
			return 0;
	}

	return -1;
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
0a333602 MV	2	/*
	3	* DHCOM DH-iMX6 PDK board support
	4	*
	5	* Copyright (C) 2017 Marek Vasut <marex@denx.de>
0a333602 MV	6	*/
	7
	8	#include <common.h>
198fee84	9	#include <dm.h>
cb3ef681	10	#include <eeprom.h>
4d72caa5	11	#include <image.h>
5255932f	12	#include <init.h>
90526e9f	13	#include <net.h>
198fee84	14	#include <dm/device-internal.h>
0a333602 MV	15	#include <asm/arch/clock.h>
	16	#include <asm/arch/crm_regs.h>
	17	#include <asm/arch/imx-regs.h>
	18	#include <asm/arch/iomux.h>
	19	#include <asm/arch/mx6-pins.h>
	20	#include <asm/arch/sys_proto.h>
	21	#include <asm/gpio.h>
	22	#include <asm/io.h>
	23	#include <asm/mach-imx/boot_mode.h>
	24	#include <asm/mach-imx/iomux-v3.h>
0a333602	25	#include <asm/mach-imx/sata.h>
0050c929 MV	26	#include <ahci.h>
0050c929 MV	27	#include <dwc_ahsata.h>
9fb625ce	28	#include <env.h>
0a333602	29	#include <errno.h>
e37ac717	30	#include <fsl_esdhc_imx.h>
0a333602	31	#include <fuse.h>
4a6f5b4f	32	#include <i2c_eeprom.h>
0a333602	33	#include <mmc.h>
0a333602 MV	34	#include <usb.h>
	35	#include <usb/ehci-ci.h>
	36
	37	DECLARE_GLOBAL_DATA_PTR;
	38
0a333602 MV	39	int dram_init(void)
	40	{
	41	gd->ram_size = imx_ddr_size();
	42	return 0;
	43	}
	44
	45	/*
	46	* Do not overwrite the console
	47	* Use always serial for U-Boot console
	48	*/
	49	int overwrite_console(void)
	50	{
	51	return 1;
	52	}
	53
0a333602 MV	54	static int setup_fec_clock(void)
	55	{
	56	struct iomuxc iomuxc_regs = (struct iomuxc )IOMUXC_BASE_ADDR;
	57
	58	/* set gpr1[21] to select anatop clock */
	59	clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
	60
	61	return enable_fec_anatop_clock(0, ENET_50MHZ);
	62	}
	63
0a333602 MV	64	#ifdef CONFIG_USB_EHCI_MX6
	65	static void setup_usb(void)
	66	{
	67	/*
	68	* Set daisy chain for otg_pin_id on MX6Q.
	69	* For MX6DL, this bit is reserved.
	70	*/
	71	imx_iomux_set_gpr_register(1, 13, 1, 0);
	72	}
	73
	74	int board_usb_phy_mode(int port)
0a333602 MV	75	{
0a333602 MV	76	if (port == 1)
506abdb4	77	return USB_INIT_HOST;
0a333602	78	else
506abdb4	79	return USB_INIT_DEVICE;
0a333602	80	}
0a333602 MV	81	#endif
	82
	83	static int setup_dhcom_mac_from_fuse(void)
	84	{
4a6f5b4f LZ	85	struct udevice *dev;
4a6f5b4f LZ	86	ofnode eeprom;
0a333602 MV	87	unsigned char enetaddr[6];
	88	int ret;
	89
	90	ret = eth_env_get_enetaddr("ethaddr", enetaddr);
	91	if (ret) /* ethaddr is already set */
	92	return 0;
	93
	94	imx_get_mac_from_fuse(0, enetaddr);
	95
	96	if (is_valid_ethaddr(enetaddr)) {
	97	eth_env_set_enetaddr("ethaddr", enetaddr);
	98	return 0;
	99	}
	100
4a6f5b4f LZ	101	eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
	102	if (!ofnode_valid(eeprom)) {
	103	printf("Invalid hardware path to EEPROM!\n");
	104	return -ENODEV;
	105	}
	106
	107	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
0a333602	108	if (ret) {
4a6f5b4f	109	printf("Cannot find EEPROM!\n");
0a333602 MV	110	return ret;
	111	}
	112
4a6f5b4f	113	ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
0a333602 MV	114	if (ret) {
	115	printf("Error reading configuration EEPROM!\n");
	116	return ret;
	117	}
	118
	119	if (is_valid_ethaddr(enetaddr))
	120	eth_env_set_enetaddr("ethaddr", enetaddr);
	121
	122	return 0;
	123	}
	124
	125	int board_early_init_f(void)
	126	{
	127	#ifdef CONFIG_USB_EHCI_MX6
	128	setup_usb();
	129	#endif
	130
	131	return 0;
	132	}
	133
0a333602 MV	134	int board_init(void)
	135	{
	136	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	137
	138	/* address of boot parameters */
	139	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	140
	141	/* Enable eim_slow clocks */
	142	setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
	143
0a333602 MV	144	setup_dhcom_mac_from_fuse();
0a333602 MV	145
15df6b31 HS	146	setup_fec_clock();
15df6b31 HS	147
0a333602 MV	148	return 0;
	149	}
	150
	151	#ifdef CONFIG_CMD_BMODE
	152	static const struct boot_mode board_boot_modes[] = {
	153	/* 4 bit bus width */
	154	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	155	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	156	/* 8 bit bus width */
5331fadb	157	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
0a333602 MV	158	{NULL, 0},
	159	};
	160	#endif
	161
	162	#define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
	163	#define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
	164	#define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
	165
	166	static int board_get_hwcode(void)
	167	{
	168	int hw_code;
	169
3a05eb8f MV	170	gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
	171	gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
	172	gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
	173
0a333602 MV	174	gpio_direction_input(HW_CODE_BIT_0);
	175	gpio_direction_input(HW_CODE_BIT_1);
	176	gpio_direction_input(HW_CODE_BIT_2);
	177
	178	/* HW 100 + HW 200 = 00b; HW 300 = 01b */
	179	hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) \|
	180	(gpio_get_value(HW_CODE_BIT_1) << 1) \|
	181	gpio_get_value(HW_CODE_BIT_0)) + 2;
	182
	183	return hw_code;
	184	}
	185
	186	int board_late_init(void)
	187	{
	188	u32 hw_code;
	189	char buf[16];
	190
	191	hw_code = board_get_hwcode();
	192
	193	switch (get_cpu_type()) {
	194	case MXC_CPU_MX6SOLO:
	195	snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
	196	break;
	197	case MXC_CPU_MX6DL:
	198	snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
	199	break;
	200	case MXC_CPU_MX6D:
	201	snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
	202	break;
	203	case MXC_CPU_MX6Q:
	204	snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
	205	break;
	206	default:
	207	snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
	208	break;
	209	}
	210
	211	env_set("dhcom", buf);
	212
	213	#ifdef CONFIG_CMD_BMODE
	214	add_board_boot_modes(board_boot_modes);
	215	#endif
	216	return 0;
	217	}
	218
	219	int checkboard(void)
	220	{
	221	puts("Board: DHCOM i.MX6\n");
	222	return 0;
	223	}
8039211a LZ	224
	225	#ifdef CONFIG_MULTI_DTB_FIT
	226	int board_fit_config_name_match(const char *name)
	227	{
	228	if (is_mx6dq()) {
	229	if (!strcmp(name, "imx6q-dhcom-pdk2"))
	230	return 0;
	231	} else if (is_mx6sdl()) {
	232	if (!strcmp(name, "imx6dl-dhcom-pdk2"))
	233	return 0;
	234	}
	235
	236	return -1;
	237	}
	238	#endif