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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
7288c2c2 YS |
2 | /* |
3 | * Copyright 2015 Freescale Semiconductor | |
7288c2c2 YS |
4 | */ |
5 | #include <common.h> | |
7b51b576 | 6 | #include <env.h> |
691d719d | 7 | #include <init.h> |
7288c2c2 YS |
8 | #include <malloc.h> |
9 | #include <errno.h> | |
10 | #include <netdev.h> | |
11 | #include <fsl_ifc.h> | |
12 | #include <fsl_ddr.h> | |
401d1c4f | 13 | #include <asm/global_data.h> |
7288c2c2 YS |
14 | #include <asm/io.h> |
15 | #include <fdt_support.h> | |
b08c8c48 | 16 | #include <linux/libfdt.h> |
7288c2c2 | 17 | #include <fsl-mc/fsl_mc.h> |
f3998fdc | 18 | #include <env_internal.h> |
7288c2c2 | 19 | #include <i2c.h> |
7fb79e65 | 20 | #include <rtc.h> |
9f3183d2 | 21 | #include <asm/arch/soc.h> |
e71a980a | 22 | #include <hwconfig.h> |
fcfdb6d5 | 23 | #include <fsl_sec.h> |
54ad7b5a | 24 | #include <asm/arch/ppa.h> |
e33938ac | 25 | #include <asm/arch-fsl-layerscape/fsl_icid.h> |
54ad7b5a | 26 | |
7288c2c2 YS |
27 | |
28 | #include "../common/qixis.h" | |
44937214 | 29 | #include "ls2080aqds_qixis.h" |
35cc100b | 30 | #include "../common/vid.h" |
7288c2c2 | 31 | |
e71a980a HW |
32 | #define PIN_MUX_SEL_SDHC 0x00 |
33 | #define PIN_MUX_SEL_DSPI 0x0a | |
916d9f09 | 34 | #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27) |
e71a980a HW |
35 | |
36 | #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value) | |
37 | ||
7288c2c2 YS |
38 | DECLARE_GLOBAL_DATA_PTR; |
39 | ||
e71a980a HW |
40 | enum { |
41 | MUX_TYPE_SDHC, | |
42 | MUX_TYPE_DSPI, | |
43 | }; | |
44 | ||
7288c2c2 YS |
45 | unsigned long long get_qixis_addr(void) |
46 | { | |
47 | unsigned long long addr; | |
48 | ||
49 | if (gd->flags & GD_FLG_RELOC) | |
50 | addr = QIXIS_BASE_PHYS; | |
51 | else | |
52 | addr = QIXIS_BASE_PHYS_EARLY; | |
53 | ||
54 | /* | |
55 | * IFC address under 256MB is mapped to 0x30000000, any address above | |
56 | * is mapped to 0x5_10000000 up to 4GB. | |
57 | */ | |
58 | addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000; | |
59 | ||
60 | return addr; | |
61 | } | |
62 | ||
63 | int checkboard(void) | |
64 | { | |
65 | char buf[64]; | |
66 | u8 sw; | |
67 | static const char *const freq[] = {"100", "125", "156.25", | |
68 | "100 separate SSCG"}; | |
69 | int clock; | |
70 | ||
ff1b8e3f PK |
71 | cpu_name(buf); |
72 | printf("Board: %s-QDS, ", buf); | |
73 | ||
7288c2c2 | 74 | sw = QIXIS_READ(arch); |
7288c2c2 YS |
75 | printf("Board Arch: V%d, ", sw >> 4); |
76 | printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); | |
77 | ||
ff1b8e3f PK |
78 | memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); |
79 | ||
7288c2c2 YS |
80 | sw = QIXIS_READ(brdcfg[0]); |
81 | sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; | |
82 | ||
83 | if (sw < 0x8) | |
84 | printf("vBank: %d\n", sw); | |
85 | else if (sw == 0x8) | |
86 | puts("PromJet\n"); | |
87 | else if (sw == 0x9) | |
88 | puts("NAND\n"); | |
a646f669 YY |
89 | else if (sw == 0xf) |
90 | puts("QSPI\n"); | |
7288c2c2 YS |
91 | else if (sw == 0x15) |
92 | printf("IFCCard\n"); | |
93 | else | |
94 | printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); | |
95 | ||
96 | printf("FPGA: v%d (%s), build %d", | |
97 | (int)QIXIS_READ(scver), qixis_read_tag(buf), | |
98 | (int)qixis_read_minor()); | |
99 | /* the timestamp string contains "\n" at the end */ | |
100 | printf(" on %s", qixis_read_time(buf)); | |
101 | ||
102 | /* | |
103 | * Display the actual SERDES reference clocks as configured by the | |
104 | * dip switches on the board. Note that the SWx registers could | |
105 | * technically be set to force the reference clocks to match the | |
106 | * values that the SERDES expects (or vice versa). For now, however, | |
107 | * we just display both values and hope the user notices when they | |
108 | * don't match. | |
109 | */ | |
110 | puts("SERDES1 Reference : "); | |
111 | sw = QIXIS_READ(brdcfg[2]); | |
112 | clock = (sw >> 6) & 3; | |
113 | printf("Clock1 = %sMHz ", freq[clock]); | |
114 | clock = (sw >> 4) & 3; | |
115 | printf("Clock2 = %sMHz", freq[clock]); | |
116 | ||
117 | puts("\nSERDES2 Reference : "); | |
118 | clock = (sw >> 2) & 3; | |
119 | printf("Clock1 = %sMHz ", freq[clock]); | |
120 | clock = (sw >> 0) & 3; | |
121 | printf("Clock2 = %sMHz\n", freq[clock]); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | unsigned long get_board_sys_clk(void) | |
127 | { | |
128 | u8 sysclk_conf = QIXIS_READ(brdcfg[1]); | |
129 | ||
130 | switch (sysclk_conf & 0x0F) { | |
131 | case QIXIS_SYSCLK_83: | |
132 | return 83333333; | |
133 | case QIXIS_SYSCLK_100: | |
134 | return 100000000; | |
135 | case QIXIS_SYSCLK_125: | |
136 | return 125000000; | |
137 | case QIXIS_SYSCLK_133: | |
138 | return 133333333; | |
139 | case QIXIS_SYSCLK_150: | |
140 | return 150000000; | |
141 | case QIXIS_SYSCLK_160: | |
142 | return 160000000; | |
143 | case QIXIS_SYSCLK_166: | |
144 | return 166666666; | |
145 | } | |
146 | return 66666666; | |
147 | } | |
148 | ||
149 | unsigned long get_board_ddr_clk(void) | |
150 | { | |
151 | u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); | |
152 | ||
153 | switch ((ddrclk_conf & 0x30) >> 4) { | |
154 | case QIXIS_DDRCLK_100: | |
155 | return 100000000; | |
156 | case QIXIS_DDRCLK_125: | |
157 | return 125000000; | |
158 | case QIXIS_DDRCLK_133: | |
159 | return 133333333; | |
160 | } | |
161 | return 66666666; | |
162 | } | |
163 | ||
164 | int select_i2c_ch_pca9547(u8 ch) | |
165 | { | |
166 | int ret; | |
885ae051 CH |
167 | #ifdef CONFIG_DM_I2C |
168 | struct udevice *dev; | |
7288c2c2 | 169 | |
885ae051 CH |
170 | ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev); |
171 | if (!ret) | |
172 | ret = dm_i2c_write(dev, 0, &ch, 1); | |
173 | ||
174 | #else | |
7288c2c2 | 175 | ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); |
885ae051 | 176 | #endif |
7288c2c2 YS |
177 | if (ret) { |
178 | puts("PCA: failed to select proper channel\n"); | |
179 | return ret; | |
180 | } | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
e71a980a HW |
185 | int config_board_mux(int ctrl_type) |
186 | { | |
187 | u8 reg5; | |
188 | ||
189 | reg5 = QIXIS_READ(brdcfg[5]); | |
190 | ||
191 | switch (ctrl_type) { | |
192 | case MUX_TYPE_SDHC: | |
193 | reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); | |
194 | break; | |
195 | case MUX_TYPE_DSPI: | |
196 | reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); | |
197 | break; | |
198 | default: | |
199 | printf("Wrong mux interface type\n"); | |
200 | return -1; | |
201 | } | |
202 | ||
203 | QIXIS_WRITE(brdcfg[5], reg5); | |
204 | ||
205 | return 0; | |
206 | } | |
207 | ||
7288c2c2 YS |
208 | int board_init(void) |
209 | { | |
e71a980a HW |
210 | char *env_hwconfig; |
211 | u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; | |
212 | u32 val; | |
213 | ||
7288c2c2 YS |
214 | init_final_memctl_regs(); |
215 | ||
e71a980a HW |
216 | val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); |
217 | ||
00caae6d | 218 | env_hwconfig = env_get("hwconfig"); |
e71a980a HW |
219 | |
220 | if (hwconfig_f("dspi", env_hwconfig) && | |
221 | DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8))) | |
222 | config_board_mux(MUX_TYPE_DSPI); | |
223 | else | |
224 | config_board_mux(MUX_TYPE_SDHC); | |
225 | ||
88718be3 | 226 | #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI) |
453418f2 YY |
227 | val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4); |
228 | ||
229 | if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3)) | |
230 | QIXIS_WRITE(brdcfg[9], | |
231 | (QIXIS_READ(brdcfg[9]) & 0xf8) | | |
232 | FSL_QIXIS_BRDCFG9_QSPI); | |
233 | #endif | |
234 | ||
7288c2c2 YS |
235 | #ifdef CONFIG_ENV_IS_NOWHERE |
236 | gd->env_addr = (ulong)&default_environment[0]; | |
237 | #endif | |
238 | select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); | |
885ae051 | 239 | |
db07c447 | 240 | #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT |
885ae051 CH |
241 | #ifdef CONFIG_DM_I2C |
242 | rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR); | |
243 | #else | |
7fb79e65 | 244 | rtc_enable_32khz_output(); |
db07c447 | 245 | #endif |
885ae051 CH |
246 | #endif |
247 | ||
15e7c681 UA |
248 | #ifdef CONFIG_FSL_CAAM |
249 | sec_init(); | |
250 | #endif | |
54ad7b5a SK |
251 | |
252 | #ifdef CONFIG_FSL_LS_PPA | |
253 | ppa_init(); | |
254 | #endif | |
255 | ||
8cbef912 IC |
256 | #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) |
257 | pci_init(); | |
258 | #endif | |
259 | ||
7288c2c2 YS |
260 | return 0; |
261 | } | |
262 | ||
263 | int board_early_init_f(void) | |
264 | { | |
8c77ef85 YY |
265 | #ifdef CONFIG_SYS_I2C_EARLY_INIT |
266 | i2c_early_init_f(); | |
267 | #endif | |
7288c2c2 | 268 | fsl_lsch3_early_init_f(); |
916d9f09 YY |
269 | #ifdef CONFIG_FSL_QSPI |
270 | /* input clk: 1/2 platform clk, output: input/20 */ | |
271 | out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20); | |
272 | #endif | |
7288c2c2 YS |
273 | return 0; |
274 | } | |
275 | ||
35cc100b PJ |
276 | int misc_init_r(void) |
277 | { | |
278 | if (adjust_vdd(0)) | |
279 | printf("Warning: Adjusting core voltage failed.\n"); | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
7288c2c2 YS |
284 | void detail_board_ddr_info(void) |
285 | { | |
286 | puts("\nDDR "); | |
287 | print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, ""); | |
288 | print_ddr_info(0); | |
44937214 | 289 | #ifdef CONFIG_SYS_FSL_HAS_DP_DDR |
3c1d218a | 290 | if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { |
7288c2c2 YS |
291 | puts("\nDP-DDR "); |
292 | print_size(gd->bd->bi_dram[2].size, ""); | |
293 | print_ddr_info(CONFIG_DP_DDR_CTRL); | |
294 | } | |
44937214 | 295 | #endif |
7288c2c2 YS |
296 | } |
297 | ||
1f55a938 | 298 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
7288c2c2 YS |
299 | void fdt_fixup_board_enet(void *fdt) |
300 | { | |
301 | int offset; | |
302 | ||
e91f1dec | 303 | offset = fdt_path_offset(fdt, "/soc/fsl-mc"); |
7288c2c2 YS |
304 | |
305 | if (offset < 0) | |
e91f1dec | 306 | offset = fdt_path_offset(fdt, "/fsl-mc"); |
7288c2c2 YS |
307 | |
308 | if (offset < 0) { | |
309 | printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", | |
310 | __func__, offset); | |
311 | return; | |
312 | } | |
313 | ||
7e968049 MYK |
314 | if (get_mc_boot_status() == 0 && |
315 | (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) | |
7288c2c2 YS |
316 | fdt_status_okay(fdt, offset); |
317 | else | |
318 | fdt_status_fail(fdt, offset); | |
319 | } | |
b7b8410a AG |
320 | |
321 | void board_quiesce_devices(void) | |
322 | { | |
323 | fsl_mc_ldpaa_exit(gd->bd); | |
324 | } | |
7288c2c2 YS |
325 | #endif |
326 | ||
327 | #ifdef CONFIG_OF_BOARD_SETUP | |
b75d8dc5 | 328 | int ft_board_setup(void *blob, struct bd_info *bd) |
7288c2c2 | 329 | { |
a2dc818f BS |
330 | u64 base[CONFIG_NR_DRAM_BANKS]; |
331 | u64 size[CONFIG_NR_DRAM_BANKS]; | |
7288c2c2 YS |
332 | |
333 | ft_cpu_setup(blob, bd); | |
334 | ||
a2dc818f BS |
335 | /* fixup DT for the two GPP DDR banks */ |
336 | base[0] = gd->bd->bi_dram[0].start; | |
337 | size[0] = gd->bd->bi_dram[0].size; | |
338 | base[1] = gd->bd->bi_dram[1].start; | |
339 | size[1] = gd->bd->bi_dram[1].size; | |
340 | ||
36cc0de0 YS |
341 | #ifdef CONFIG_RESV_RAM |
342 | /* reduce size if reserved memory is within this bank */ | |
343 | if (gd->arch.resv_ram >= base[0] && | |
344 | gd->arch.resv_ram < base[0] + size[0]) | |
345 | size[0] = gd->arch.resv_ram - base[0]; | |
346 | else if (gd->arch.resv_ram >= base[1] && | |
347 | gd->arch.resv_ram < base[1] + size[1]) | |
348 | size[1] = gd->arch.resv_ram - base[1]; | |
349 | #endif | |
350 | ||
a2dc818f | 351 | fdt_fixup_memory_banks(blob, base, size, 2); |
7288c2c2 | 352 | |
a78df40c NG |
353 | fdt_fsl_mc_fixup_iommu_map_entry(blob); |
354 | ||
a5c289b9 | 355 | fsl_fdt_fixup_dr_usb(blob, bd); |
ef53b8c4 | 356 | |
1f55a938 | 357 | #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) |
7288c2c2 | 358 | fdt_fixup_board_enet(blob); |
7288c2c2 YS |
359 | #endif |
360 | ||
e33938ac LT |
361 | fdt_fixup_icid(blob); |
362 | ||
7288c2c2 YS |
363 | return 0; |
364 | } | |
365 | #endif | |
366 | ||
367 | void qixis_dump_switch(void) | |
368 | { | |
369 | int i, nr_of_cfgsw; | |
370 | ||
371 | QIXIS_WRITE(cms[0], 0x00); | |
372 | nr_of_cfgsw = QIXIS_READ(cms[1]); | |
373 | ||
374 | puts("DIP switch settings dump:\n"); | |
375 | for (i = 1; i <= nr_of_cfgsw; i++) { | |
376 | QIXIS_WRITE(cms[0], i); | |
377 | printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); | |
378 | } | |
379 | } |