projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5fb692ca SR |
1 | /* |
| 2 | * (C) Copyright 2007 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 5fb692ca SR |
6 | */ |
| 7 | ||
| 8 | #include <ppc_asm.tmpl> | |
| cf6eb6da | 9 | #include <asm/mmu.h> |
| 5fb692ca | 10 | #include <config.h> |
| 550650dd | 11 | #include <asm/ppc4xx.h> |
| 5fb692ca | 12 | |
| 5fb692ca SR |
13 | /************************************************************************** |
| 14 | * TLB TABLE | |
| 15 | * | |
| 16 | * This table is used by the cpu boot code to setup the initial tlb | |
| 17 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 18 | * this table lets each board set things up however they like. | |
| 19 | * | |
| 20 | * Pointer to the table is returned in r1 | |
| 21 | * | |
| 22 | *************************************************************************/ | |
| 23 | ||
| 24 | .section .bootpg,"ax" | |
| 25 | .globl tlbtab | |
| 26 | ||
| 27 | tlbtab: | |
| 28 | tlbtab_start | |
| cf6eb6da SR |
29 | tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG) |
| 30 | tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG) | |
| 31 | tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX ) | |
| 32 | tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG ) | |
| 33 | tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG ) | |
| 34 | tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG ) | |
| 5fb692ca | 35 | tlbtab_end |