[J-u-boot.git] / arch / arm / cpu / arm926ejs / at91 / lowlevel_init.S

/*
 * Memory Setup stuff - taken from blob memsetup.S
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
 *		       Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
 *
 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_wdt.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_matrix.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_rstc.h>
#ifdef CONFIG_ATMEL_LEGACY
#include <asm/arch/at91sam9_matrix.h>
#endif
#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
#endif

_TEXT_BASE:
	.word	CONFIG_SYS_TEXT_BASE

.globl lowlevel_init
.type lowlevel_init,function
lowlevel_init:

	mov	r5, pc		/* r5 = POS1 + 4 current */
POS1:
	ldr	r0, =POS1	/* r0 = POS1 compile */
	ldr	r2, _TEXT_BASE
	sub	r0, r0, r2	/* r0 = POS1-_TEXT_BASE (POS1 relative) */
	sub	r5, r5, r0	/* r0 = CONFIG_SYS_TEXT_BASE-1 */
	sub	r5, r5, #4	/* r1 = text base - current */

	/* memory control configuration 1 */
	ldr	r0, =SMRDATA
	ldr	r2, =SMRDATA1
	ldr	r1, _TEXT_BASE
	sub	r0, r0, r1
	sub	r2, r2, r1
	add	r0, r0, r5
	add	r2, r2, r5
0:
	/* the address */
	ldr	r1, [r0], #4
	/* the value */
	ldr	r3, [r0], #4
	str	r3, [r1]
	cmp	r2, r0
	bne	0b

/* ----------------------------------------------------------------------------
 * PMC Init Step 1.
 * ----------------------------------------------------------------------------
 * - Check if the PLL is already initialized
 * ----------------------------------------------------------------------------
 */
	ldr	r1, =(AT91_ASM_PMC_MCKR)
	ldr	r0, [r1]
	and	r0, r0, #3
	cmp	r0, #0
	bne	PLL_setup_end

/* ---------------------------------------------------------------------------
 * - Enable the Main Oscillator
 * ---------------------------------------------------------------------------
 */
	ldr	r1, =(AT91_ASM_PMC_MOR)
	ldr	r2, =(AT91_ASM_PMC_SR)
	/* Main oscillator Enable register PMC_MOR: */
	ldr	r0, =CONFIG_SYS_MOR_VAL
	str	r0, [r1]

	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
	mov	r4, #AT91_PMC_IXR_MOSCS
MOSCS_Loop:
	ldr	r3, [r2]
	and	r3, r4, r3
	cmp	r3, #AT91_PMC_IXR_MOSCS
	bne	MOSCS_Loop

/* ----------------------------------------------------------------------------
 * PMC Init Step 2.
 * ----------------------------------------------------------------------------
 * Setup PLLA
 * ----------------------------------------------------------------------------
 */
	ldr	r1, =(AT91_ASM_PMC_PLLAR)
	ldr	r0, =CONFIG_SYS_PLLAR_VAL
	str	r0, [r1]

	/* Reading the PMC Status register to detect when the PLLA is locked */
	mov	r4, #AT91_PMC_IXR_LOCKA
MOSCS_Loop1:
	ldr	r3, [r2]
	and	r3, r4, r3
	cmp	r3, #AT91_PMC_IXR_LOCKA
	bne	MOSCS_Loop1

/* ----------------------------------------------------------------------------
 * PMC Init Step 3.
 * ----------------------------------------------------------------------------
 * - Switch on the Main Oscillator
 * ----------------------------------------------------------------------------
 */
	ldr	r1, =(AT91_ASM_PMC_MCKR)

	/* -Master Clock Controller register PMC_MCKR */
	ldr	r0, =CONFIG_SYS_MCKR1_VAL
	str	r0, [r1]

	/* Reading the PMC Status to detect when the Master clock is ready */
	mov	r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop:
	ldr	r3, [r2]
	and	r3, r4, r3
	cmp	r3, #AT91_PMC_IXR_MCKRDY
	bne	MCKRDY_Loop

	ldr	r0, =CONFIG_SYS_MCKR2_VAL
	str	r0, [r1]

	/* Reading the PMC Status to detect when the Master clock is ready */
	mov	r4, #AT91_PMC_IXR_MCKRDY
MCKRDY_Loop1:
	ldr	r3, [r2]
	and	r3, r4, r3
	cmp	r3, #AT91_PMC_IXR_MCKRDY
	bne	MCKRDY_Loop1
PLL_setup_end:

/* ----------------------------------------------------------------------------
 * - memory control configuration 2
 * ----------------------------------------------------------------------------
 */
	ldr	r0, =(AT91_ASM_SDRAMC_TR)
	ldr	r1, [r0]
	cmp	r1, #0
	bne	SDRAM_setup_end

	ldr	r0, =SMRDATA1
	ldr	r2, =SMRDATA2
	ldr	r1, _TEXT_BASE
	sub	r0, r0, r1
	sub	r2, r2, r1
	add	r0, r0, r5
	add	r2, r2, r5
2:
	/* the address */
	ldr	r1, [r0], #4
	/* the value */
	ldr	r3, [r0], #4
	str	r3, [r1]
	cmp	r2, r0
	bne	2b

SDRAM_setup_end:
	/* everything is fine now */
	mov	pc, lr

	.ltorg

SMRDATA:
	.word AT91_ASM_WDT_MR
	.word CONFIG_SYS_WDTC_WDMR_VAL
	/* configure PIOx as EBI0 D[16-31] */
#if defined(CONFIG_AT91SAM9263)
	.word AT91_ASM_PIOD_PDR
	.word CONFIG_SYS_PIOD_PDR_VAL1
	.word AT91_ASM_PIOD_PUDR
	.word CONFIG_SYS_PIOD_PPUDR_VAL
	.word AT91_ASM_PIOD_ASR
	.word CONFIG_SYS_PIOD_PPUDR_VAL
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \
	|| defined(CONFIG_AT91SAM9G20)
	.word AT91_ASM_PIOC_PDR
	.word CONFIG_SYS_PIOC_PDR_VAL1
	.word AT91_ASM_PIOC_PUDR
	.word CONFIG_SYS_PIOC_PPUDR_VAL
#endif
	.word AT91_ASM_MATRIX_CSA0
	.word CONFIG_SYS_MATRIX_EBICSA_VAL

	/* flash */
	.word AT91_ASM_SMC_MODE0
	.word CONFIG_SYS_SMC0_MODE0_VAL

	.word AT91_ASM_SMC_CYCLE0
	.word CONFIG_SYS_SMC0_CYCLE0_VAL

	.word AT91_ASM_SMC_PULSE0
	.word CONFIG_SYS_SMC0_PULSE0_VAL

	.word AT91_ASM_SMC_SETUP0
	.word CONFIG_SYS_SMC0_SETUP0_VAL

SMRDATA1:
	.word AT91_ASM_SDRAMC_MR
	.word CONFIG_SYS_SDRC_MR_VAL1
	.word AT91_ASM_SDRAMC_TR
	.word CONFIG_SYS_SDRC_TR_VAL1
	.word AT91_ASM_SDRAMC_CR
	.word CONFIG_SYS_SDRC_CR_VAL
	.word AT91_ASM_SDRAMC_MDR
	.word CONFIG_SYS_SDRC_MDR_VAL
	.word AT91_ASM_SDRAMC_MR
	.word CONFIG_SYS_SDRC_MR_VAL2
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL1
	.word AT91_ASM_SDRAMC_MR
	.word CONFIG_SYS_SDRC_MR_VAL3
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL2
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL3
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL4
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL5
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL6
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL7
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL8
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL9
	.word AT91_ASM_SDRAMC_MR
	.word CONFIG_SYS_SDRC_MR_VAL4
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL10
	.word AT91_ASM_SDRAMC_MR
	.word CONFIG_SYS_SDRC_MR_VAL5
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL11
	.word AT91_ASM_SDRAMC_TR
	.word CONFIG_SYS_SDRC_TR_VAL2
	.word CONFIG_SYS_SDRAM_BASE
	.word CONFIG_SYS_SDRAM_VAL12
	/* User reset enable*/
	.word AT91_ASM_RSTC_MR
	.word CONFIG_SYS_RSTC_RMR_VAL
#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
	/* MATRIX_MCFG - REMAP all masters */
	.word AT91_ASM_MATRIX_MCFG
	.word 0x1FF
#endif
SMRDATA2:
	.word 0
Commit	Line	Data
f0a2c7b4 II	1	/*
	2	* Memory Setup stuff - taken from blob memsetup.S
	3	*
	4	* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
	5	* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
	6	*
	7	* Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
	8	* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
f0a2c7b4 II	11	*/
	12
	13	#include <config.h>
f0a2c7b4 II	14	#include <asm/arch/hardware.h>
f0a2c7b4 II	15	#include <asm/arch/at91_pmc.h>
f0a2c7b4	16	#include <asm/arch/at91_wdt.h>
0cf0b931 JS	17	#include <asm/arch/at91_pio.h>
0cf0b931 JS	18	#include <asm/arch/at91_matrix.h>
f0a2c7b4 II	19	#include <asm/arch/at91sam9_sdramc.h>
f0a2c7b4 II	20	#include <asm/arch/at91sam9_smc.h>
0cf0b931	21	#include <asm/arch/at91_rstc.h>
ffa280fa	22	#ifdef CONFIG_ATMEL_LEGACY
0cf0b931 JS	23	#include <asm/arch/at91sam9_matrix.h>
	24	#endif
	25	#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
	26	#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
	27	#endif
f0a2c7b4 II	28
f0a2c7b4 II	29	_TEXT_BASE:
14d0a02a	30	.word CONFIG_SYS_TEXT_BASE
f0a2c7b4 II	31
	32	.globl lowlevel_init
	33	.type lowlevel_init,function
	34	lowlevel_init:
	35
	36	mov r5, pc /* r5 = POS1 + 4 current */
	37	POS1:
	38	ldr r0, =POS1 /* r0 = POS1 compile */
	39	ldr r2, _TEXT_BASE
	40	sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */
14d0a02a	41	sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */
f0a2c7b4 II	42	sub r5, r5, #4 /* r1 = text base - current */
	43
	44	/* memory control configuration 1 */
	45	ldr r0, =SMRDATA
	46	ldr r2, =SMRDATA1
	47	ldr r1, _TEXT_BASE
	48	sub r0, r0, r1
	49	sub r2, r2, r1
	50	add r0, r0, r5
	51	add r2, r2, r5
	52	0:
	53	/* the address */
	54	ldr r1, [r0], #4
	55	/* the value */
	56	ldr r3, [r0], #4
	57	str r3, [r1]
	58	cmp r2, r0
	59	bne 0b
	60
	61	/* ----------------------------------------------------------------------------
	62	* PMC Init Step 1.
	63	* ----------------------------------------------------------------------------
	64	* - Check if the PLL is already initialized
	65	* ----------------------------------------------------------------------------
	66	*/
0cf0b931	67	ldr r1, =(AT91_ASM_PMC_MCKR)
f0a2c7b4 II	68	ldr r0, [r1]
	69	and r0, r0, #3
	70	cmp r0, #0
	71	bne PLL_setup_end
	72
	73	/* ---------------------------------------------------------------------------
	74	* - Enable the Main Oscillator
	75	* ---------------------------------------------------------------------------
	76	*/
0cf0b931 JS	77	ldr r1, =(AT91_ASM_PMC_MOR)
0cf0b931 JS	78	ldr r2, =(AT91_ASM_PMC_SR)
8096c51f	79	/* Main oscillator Enable register PMC_MOR: */
01550a2b	80	ldr r0, =CONFIG_SYS_MOR_VAL
8096c51f	81	str r0, [r1]
f0a2c7b4 II	82
f0a2c7b4 II	83	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
0cf0b931	84	mov r4, #AT91_PMC_IXR_MOSCS
f0a2c7b4 II	85	MOSCS_Loop:
	86	ldr r3, [r2]
	87	and r3, r4, r3
0cf0b931	88	cmp r3, #AT91_PMC_IXR_MOSCS
f0a2c7b4 II	89	bne MOSCS_Loop
	90
	91	/* ----------------------------------------------------------------------------
	92	* PMC Init Step 2.
	93	* ----------------------------------------------------------------------------
	94	* Setup PLLA
	95	* ----------------------------------------------------------------------------
	96	*/
0cf0b931	97	ldr r1, =(AT91_ASM_PMC_PLLAR)
f0a2c7b4 II	98	ldr r0, =CONFIG_SYS_PLLAR_VAL
	99	str r0, [r1]
	100
	101	/* Reading the PMC Status register to detect when the PLLA is locked */
0cf0b931	102	mov r4, #AT91_PMC_IXR_LOCKA
f0a2c7b4 II	103	MOSCS_Loop1:
	104	ldr r3, [r2]
	105	and r3, r4, r3
0cf0b931	106	cmp r3, #AT91_PMC_IXR_LOCKA
f0a2c7b4 II	107	bne MOSCS_Loop1
	108
	109	/* ----------------------------------------------------------------------------
	110	* PMC Init Step 3.
	111	* ----------------------------------------------------------------------------
8096c51f	112	* - Switch on the Main Oscillator
f0a2c7b4 II	113	* ----------------------------------------------------------------------------
f0a2c7b4 II	114	*/
0cf0b931	115	ldr r1, =(AT91_ASM_PMC_MCKR)
f0a2c7b4 II	116
	117	/* -Master Clock Controller register PMC_MCKR */
	118	ldr r0, =CONFIG_SYS_MCKR1_VAL
	119	str r0, [r1]
	120
	121	/* Reading the PMC Status to detect when the Master clock is ready */
0cf0b931	122	mov r4, #AT91_PMC_IXR_MCKRDY
f0a2c7b4 II	123	MCKRDY_Loop:
	124	ldr r3, [r2]
	125	and r3, r4, r3
0cf0b931	126	cmp r3, #AT91_PMC_IXR_MCKRDY
f0a2c7b4 II	127	bne MCKRDY_Loop
	128
	129	ldr r0, =CONFIG_SYS_MCKR2_VAL
	130	str r0, [r1]
	131
	132	/* Reading the PMC Status to detect when the Master clock is ready */
0cf0b931	133	mov r4, #AT91_PMC_IXR_MCKRDY
f0a2c7b4 II	134	MCKRDY_Loop1:
	135	ldr r3, [r2]
	136	and r3, r4, r3
0cf0b931	137	cmp r3, #AT91_PMC_IXR_MCKRDY
f0a2c7b4	138	bne MCKRDY_Loop1
f0a2c7b4 II	139	PLL_setup_end:
	140
	141	/* ----------------------------------------------------------------------------
	142	* - memory control configuration 2
	143	* ----------------------------------------------------------------------------
	144	*/
0cf0b931	145	ldr r0, =(AT91_ASM_SDRAMC_TR)
f0a2c7b4 II	146	ldr r1, [r0]
	147	cmp r1, #0
	148	bne SDRAM_setup_end
	149
	150	ldr r0, =SMRDATA1
	151	ldr r2, =SMRDATA2
	152	ldr r1, _TEXT_BASE
	153	sub r0, r0, r1
	154	sub r2, r2, r1
	155	add r0, r0, r5
	156	add r2, r2, r5
f0a2c7b4 II	157	2:
	158	/* the address */
	159	ldr r1, [r0], #4
	160	/* the value */
	161	ldr r3, [r0], #4
	162	str r3, [r1]
	163	cmp r2, r0
	164	bne 2b
	165
	166	SDRAM_setup_end:
	167	/* everything is fine now */
	168	mov pc, lr
	169
	170	.ltorg
	171
	172	SMRDATA:
0cf0b931	173	.word AT91_ASM_WDT_MR
f0a2c7b4	174	.word CONFIG_SYS_WDTC_WDMR_VAL
8096c51f JCPV	175	/* configure PIOx as EBI0 D[16-31] */
8096c51f JCPV	176	#if defined(CONFIG_AT91SAM9263)
0cf0b931	177	.word AT91_ASM_PIOD_PDR
f0a2c7b4	178	.word CONFIG_SYS_PIOD_PDR_VAL1
0cf0b931	179	.word AT91_ASM_PIOD_PUDR
f0a2c7b4	180	.word CONFIG_SYS_PIOD_PPUDR_VAL
0cf0b931	181	.word AT91_ASM_PIOD_ASR
f0a2c7b4	182	.word CONFIG_SYS_PIOD_PPUDR_VAL
23b80982 TR	183	#elif defined(CONFIG_AT91SAM9260) \|\| defined(CONFIG_AT91SAM9261) \
23b80982 TR	184	\|\| defined(CONFIG_AT91SAM9G20)
0cf0b931	185	.word AT91_ASM_PIOC_PDR
8096c51f	186	.word CONFIG_SYS_PIOC_PDR_VAL1
0cf0b931	187	.word AT91_ASM_PIOC_PUDR
8096c51f JCPV	188	.word CONFIG_SYS_PIOC_PPUDR_VAL
8096c51f JCPV	189	#endif
0cf0b931	190	.word AT91_ASM_MATRIX_CSA0
8096c51f	191	.word CONFIG_SYS_MATRIX_EBICSA_VAL
f0a2c7b4 II	192
f0a2c7b4 II	193	/* flash */
0cf0b931	194	.word AT91_ASM_SMC_MODE0
7a11c7f9	195	.word CONFIG_SYS_SMC0_MODE0_VAL
f0a2c7b4	196
0cf0b931	197	.word AT91_ASM_SMC_CYCLE0
f0a2c7b4 II	198	.word CONFIG_SYS_SMC0_CYCLE0_VAL
f0a2c7b4 II	199
0cf0b931	200	.word AT91_ASM_SMC_PULSE0
f0a2c7b4 II	201	.word CONFIG_SYS_SMC0_PULSE0_VAL
f0a2c7b4 II	202
0cf0b931	203	.word AT91_ASM_SMC_SETUP0
f0a2c7b4 II	204	.word CONFIG_SYS_SMC0_SETUP0_VAL
f0a2c7b4 II	205
f0a2c7b4	206	SMRDATA1:
0cf0b931	207	.word AT91_ASM_SDRAMC_MR
f0a2c7b4	208	.word CONFIG_SYS_SDRC_MR_VAL1
0cf0b931	209	.word AT91_ASM_SDRAMC_TR
f0a2c7b4	210	.word CONFIG_SYS_SDRC_TR_VAL1
0cf0b931	211	.word AT91_ASM_SDRAMC_CR
f0a2c7b4	212	.word CONFIG_SYS_SDRC_CR_VAL
0cf0b931	213	.word AT91_ASM_SDRAMC_MDR
f0a2c7b4	214	.word CONFIG_SYS_SDRC_MDR_VAL
0cf0b931	215	.word AT91_ASM_SDRAMC_MR
f0a2c7b4	216	.word CONFIG_SYS_SDRC_MR_VAL2
96fd9906	217	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	218	.word CONFIG_SYS_SDRAM_VAL1
0cf0b931	219	.word AT91_ASM_SDRAMC_MR
f0a2c7b4	220	.word CONFIG_SYS_SDRC_MR_VAL3
96fd9906	221	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	222	.word CONFIG_SYS_SDRAM_VAL2
96fd9906	223	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	224	.word CONFIG_SYS_SDRAM_VAL3
96fd9906	225	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	226	.word CONFIG_SYS_SDRAM_VAL4
96fd9906	227	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	228	.word CONFIG_SYS_SDRAM_VAL5
96fd9906	229	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	230	.word CONFIG_SYS_SDRAM_VAL6
96fd9906	231	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	232	.word CONFIG_SYS_SDRAM_VAL7
96fd9906	233	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	234	.word CONFIG_SYS_SDRAM_VAL8
96fd9906	235	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	236	.word CONFIG_SYS_SDRAM_VAL9
0cf0b931	237	.word AT91_ASM_SDRAMC_MR
f0a2c7b4	238	.word CONFIG_SYS_SDRC_MR_VAL4
96fd9906	239	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	240	.word CONFIG_SYS_SDRAM_VAL10
0cf0b931	241	.word AT91_ASM_SDRAMC_MR
f0a2c7b4	242	.word CONFIG_SYS_SDRC_MR_VAL5
96fd9906	243	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4	244	.word CONFIG_SYS_SDRAM_VAL11
0cf0b931	245	.word AT91_ASM_SDRAMC_TR
f0a2c7b4	246	.word CONFIG_SYS_SDRC_TR_VAL2
96fd9906	247	.word CONFIG_SYS_SDRAM_BASE
f0a2c7b4 II	248	.word CONFIG_SYS_SDRAM_VAL12
f0a2c7b4 II	249	/* User reset enable*/
0cf0b931	250	.word AT91_ASM_RSTC_MR
f0a2c7b4 II	251	.word CONFIG_SYS_RSTC_RMR_VAL
	252	#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
	253	/* MATRIX_MCFG - REMAP all masters */
0cf0b931	254	.word AT91_ASM_MATRIX_MCFG
f0a2c7b4 II	255	.word 0x1FF
f0a2c7b4 II	256	#endif
f0a2c7b4 II	257	SMRDATA2:
f0a2c7b4 II	258	.word 0