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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
ba4dfef1 SW |
2 | /* |
3 | * Copyright (c) 2016, NVIDIA CORPORATION. | |
4 | * | |
ba4dfef1 SW |
5 | * Portions based on U-Boot's rtl8169.c. |
6 | */ | |
7 | ||
8 | /* | |
9 | * This driver supports the Synopsys Designware Ethernet QOS (Quality Of | |
10 | * Service) IP block. The IP supports multiple options for bus type, clocking/ | |
11 | * reset structure, and feature list. | |
12 | * | |
13 | * The driver is written such that generic core logic is kept separate from | |
14 | * configuration-specific logic. Code that interacts with configuration- | |
15 | * specific resources is split out into separate functions to avoid polluting | |
16 | * common code. If/when this driver is enhanced to support multiple | |
17 | * configurations, the core code should be adapted to call all configuration- | |
18 | * specific functions through function pointers, with the definition of those | |
19 | * function pointers being supplied by struct udevice_id eqos_ids[]'s .data | |
20 | * field. | |
21 | * | |
22 | * The following configurations are currently supported: | |
23 | * tegra186: | |
24 | * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an | |
25 | * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and | |
26 | * supports a single RGMII PHY. This configuration also has SW control over | |
27 | * all clock and reset signals to the HW block. | |
28 | */ | |
cafaa301 | 29 | |
b547f4bd PD |
30 | #define LOG_CATEGORY UCLASS_ETH |
31 | ||
ba4dfef1 | 32 | #include <clk.h> |
1eb69ae4 | 33 | #include <cpu_func.h> |
ba4dfef1 | 34 | #include <dm.h> |
beabef65 | 35 | #include <dm/device_compat.h> |
ba4dfef1 | 36 | #include <errno.h> |
8a3b69d2 | 37 | #include <eth_phy.h> |
f7ae49fc | 38 | #include <log.h> |
336d4615 | 39 | #include <malloc.h> |
ba4dfef1 SW |
40 | #include <memalign.h> |
41 | #include <miiphy.h> | |
42 | #include <net.h> | |
43 | #include <netdev.h> | |
44 | #include <phy.h> | |
45 | #include <reset.h> | |
46 | #include <wait_bit.h> | |
90526e9f | 47 | #include <asm/cache.h> |
ba4dfef1 SW |
48 | #include <asm/gpio.h> |
49 | #include <asm/io.h> | |
0e9d2394 FD |
50 | #ifdef CONFIG_ARCH_IMX8M |
51 | #include <asm/arch/clock.h> | |
52 | #include <asm/mach-imx/sys_proto.h> | |
53 | #endif | |
151b8857 | 54 | #include <linux/bitfield.h> |
c05ed00a | 55 | #include <linux/delay.h> |
1e94b46f | 56 | #include <linux/printk.h> |
ba4dfef1 | 57 | |
149e80f7 | 58 | #include "dwc_eth_qos.h" |
ba4dfef1 SW |
59 | |
60 | /* | |
61 | * TX and RX descriptors are 16 bytes. This causes problems with the cache | |
62 | * maintenance on CPUs where the cache-line size exceeds the size of these | |
63 | * descriptors. What will happen is that when the driver receives a packet | |
64 | * it will be immediately requeued for the hardware to reuse. The CPU will | |
65 | * therefore need to flush the cache-line containing the descriptor, which | |
66 | * will cause all other descriptors in the same cache-line to be flushed | |
67 | * along with it. If one of those descriptors had been written to by the | |
68 | * device those changes (and the associated packet) will be lost. | |
69 | * | |
70 | * To work around this, we make use of non-cached memory if available. If | |
71 | * descriptors are mapped uncached there's no need to manually flush them | |
72 | * or invalidate them. | |
73 | * | |
74 | * Note that this only applies to descriptors. The packet data buffers do | |
75 | * not have the same constraints since they are 1536 bytes large, so they | |
76 | * are unlikely to share cache-lines. | |
77 | */ | |
6f1e668d | 78 | static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num) |
ba4dfef1 | 79 | { |
e9d3fc7e | 80 | return memalign(ARCH_DMA_MINALIGN, num * eqos->desc_size); |
ba4dfef1 SW |
81 | } |
82 | ||
83 | static void eqos_free_descs(void *descs) | |
84 | { | |
ba4dfef1 | 85 | free(descs); |
ba4dfef1 SW |
86 | } |
87 | ||
6f1e668d MV |
88 | static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos, |
89 | unsigned int num, bool rx) | |
ba4dfef1 | 90 | { |
f94d008a MV |
91 | return (rx ? eqos->rx_descs : eqos->tx_descs) + |
92 | (num * eqos->desc_size); | |
ba4dfef1 SW |
93 | } |
94 | ||
149e80f7 | 95 | void eqos_inval_desc_generic(void *desc) |
ac2d4efb | 96 | { |
e9d3fc7e | 97 | unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); |
6f1e668d MV |
98 | unsigned long end = ALIGN(start + sizeof(struct eqos_desc), |
99 | ARCH_DMA_MINALIGN); | |
ac2d4efb CR |
100 | |
101 | invalidate_dcache_range(start, end); | |
ba4dfef1 SW |
102 | } |
103 | ||
149e80f7 | 104 | void eqos_flush_desc_generic(void *desc) |
ac2d4efb | 105 | { |
e9d3fc7e | 106 | unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1); |
6f1e668d MV |
107 | unsigned long end = ALIGN(start + sizeof(struct eqos_desc), |
108 | ARCH_DMA_MINALIGN); | |
ac2d4efb CR |
109 | |
110 | flush_dcache_range(start, end); | |
ac2d4efb CR |
111 | } |
112 | ||
ac19125f | 113 | static void eqos_inval_buffer_tegra186(void *buf, size_t size) |
ba4dfef1 SW |
114 | { |
115 | unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); | |
116 | unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN); | |
117 | ||
118 | invalidate_dcache_range(start, end); | |
119 | } | |
120 | ||
149e80f7 | 121 | void eqos_inval_buffer_generic(void *buf, size_t size) |
ac2d4efb CR |
122 | { |
123 | unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); | |
124 | unsigned long end = roundup((unsigned long)buf + size, | |
125 | ARCH_DMA_MINALIGN); | |
126 | ||
127 | invalidate_dcache_range(start, end); | |
128 | } | |
129 | ||
130 | static void eqos_flush_buffer_tegra186(void *buf, size_t size) | |
ba4dfef1 SW |
131 | { |
132 | flush_cache((unsigned long)buf, size); | |
133 | } | |
134 | ||
149e80f7 | 135 | void eqos_flush_buffer_generic(void *buf, size_t size) |
ac2d4efb CR |
136 | { |
137 | unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN); | |
138 | unsigned long end = roundup((unsigned long)buf + size, | |
139 | ARCH_DMA_MINALIGN); | |
140 | ||
141 | flush_dcache_range(start, end); | |
142 | } | |
143 | ||
ba4dfef1 SW |
144 | static int eqos_mdio_wait_idle(struct eqos_priv *eqos) |
145 | { | |
48263504 ÁFR |
146 | return wait_for_bit_le32(&eqos->mac_regs->mdio_address, |
147 | EQOS_MAC_MDIO_ADDRESS_GB, false, | |
148 | 1000000, true); | |
ba4dfef1 SW |
149 | } |
150 | ||
151b8857 PO |
151 | /* Bitmask common for mdio_read and mdio_write */ |
152 | #define EQOS_MDIO_BITFIELD(pa, rda, cr) \ | |
153 | FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_PA_MASK, pa) | \ | |
154 | FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_RDA_MASK, rda) | \ | |
155 | FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_CR_MASK, cr) | \ | |
156 | EQOS_MAC_MDIO_ADDRESS_GB | |
157 | ||
158 | static u32 eqos_mdio_bitfield(struct eqos_priv *eqos, int addr, int devad, int reg) | |
159 | { | |
160 | int cr = eqos->config->config_mac_mdio; | |
161 | bool c22 = devad == MDIO_DEVAD_NONE ? true : false; | |
162 | ||
163 | if (c22) | |
164 | return EQOS_MDIO_BITFIELD(addr, reg, cr); | |
165 | else | |
166 | return EQOS_MDIO_BITFIELD(addr, devad, cr) | | |
167 | EQOS_MAC_MDIO_ADDRESS_C45E; | |
168 | } | |
169 | ||
ba4dfef1 SW |
170 | static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad, |
171 | int mdio_reg) | |
172 | { | |
173 | struct eqos_priv *eqos = bus->priv; | |
174 | u32 val; | |
175 | int ret; | |
176 | ||
177 | debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr, | |
178 | mdio_reg); | |
179 | ||
180 | ret = eqos_mdio_wait_idle(eqos); | |
181 | if (ret) { | |
f12001b1 | 182 | pr_err("MDIO not idle at entry\n"); |
ba4dfef1 SW |
183 | return ret; |
184 | } | |
185 | ||
186 | val = readl(&eqos->mac_regs->mdio_address); | |
151b8857 PO |
187 | val &= EQOS_MAC_MDIO_ADDRESS_SKAP; |
188 | ||
189 | val |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | | |
190 | FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, | |
191 | EQOS_MAC_MDIO_ADDRESS_GOC_READ); | |
192 | ||
193 | if (val & EQOS_MAC_MDIO_ADDRESS_C45E) { | |
194 | writel(FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg), | |
195 | &eqos->mac_regs->mdio_data); | |
196 | } | |
197 | ||
ba4dfef1 SW |
198 | writel(val, &eqos->mac_regs->mdio_address); |
199 | ||
ac2d4efb | 200 | udelay(eqos->config->mdio_wait); |
ba4dfef1 SW |
201 | |
202 | ret = eqos_mdio_wait_idle(eqos); | |
203 | if (ret) { | |
f12001b1 | 204 | pr_err("MDIO read didn't complete\n"); |
ba4dfef1 SW |
205 | return ret; |
206 | } | |
207 | ||
208 | val = readl(&eqos->mac_regs->mdio_data); | |
209 | val &= EQOS_MAC_MDIO_DATA_GD_MASK; | |
210 | ||
211 | debug("%s: val=%x\n", __func__, val); | |
212 | ||
213 | return val; | |
214 | } | |
215 | ||
216 | static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad, | |
217 | int mdio_reg, u16 mdio_val) | |
218 | { | |
219 | struct eqos_priv *eqos = bus->priv; | |
151b8857 PO |
220 | u32 v_addr; |
221 | u32 v_data; | |
ba4dfef1 SW |
222 | int ret; |
223 | ||
224 | debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev, | |
225 | mdio_addr, mdio_reg, mdio_val); | |
226 | ||
227 | ret = eqos_mdio_wait_idle(eqos); | |
228 | if (ret) { | |
f12001b1 | 229 | pr_err("MDIO not idle at entry\n"); |
ba4dfef1 SW |
230 | return ret; |
231 | } | |
232 | ||
151b8857 PO |
233 | v_addr = readl(&eqos->mac_regs->mdio_address); |
234 | v_addr &= EQOS_MAC_MDIO_ADDRESS_SKAP; | |
ba4dfef1 | 235 | |
151b8857 PO |
236 | v_addr |= eqos_mdio_bitfield(eqos, mdio_addr, mdio_devad, mdio_reg) | |
237 | FIELD_PREP(EQOS_MAC_MDIO_ADDRESS_GOC_MASK, | |
238 | EQOS_MAC_MDIO_ADDRESS_GOC_WRITE); | |
239 | ||
240 | v_data = mdio_val; | |
241 | if (v_addr & EQOS_MAC_MDIO_ADDRESS_C45E) | |
242 | v_data |= FIELD_PREP(EQOS_MAC_MDIO_DATA_RA_MASK, mdio_reg); | |
ba4dfef1 | 243 | |
151b8857 PO |
244 | writel(v_data, &eqos->mac_regs->mdio_data); |
245 | writel(v_addr, &eqos->mac_regs->mdio_address); | |
ac2d4efb | 246 | udelay(eqos->config->mdio_wait); |
ba4dfef1 SW |
247 | |
248 | ret = eqos_mdio_wait_idle(eqos); | |
249 | if (ret) { | |
f12001b1 | 250 | pr_err("MDIO read didn't complete\n"); |
ba4dfef1 SW |
251 | return ret; |
252 | } | |
253 | ||
254 | return 0; | |
255 | } | |
256 | ||
257 | static int eqos_start_clks_tegra186(struct udevice *dev) | |
258 | { | |
3a97da12 | 259 | #ifdef CONFIG_CLK |
ba4dfef1 SW |
260 | struct eqos_priv *eqos = dev_get_priv(dev); |
261 | int ret; | |
262 | ||
263 | debug("%s(dev=%p):\n", __func__, dev); | |
264 | ||
265 | ret = clk_enable(&eqos->clk_slave_bus); | |
266 | if (ret < 0) { | |
f12001b1 | 267 | pr_err("clk_enable(clk_slave_bus) failed: %d\n", ret); |
ba4dfef1 SW |
268 | goto err; |
269 | } | |
270 | ||
271 | ret = clk_enable(&eqos->clk_master_bus); | |
272 | if (ret < 0) { | |
f12001b1 | 273 | pr_err("clk_enable(clk_master_bus) failed: %d\n", ret); |
ba4dfef1 SW |
274 | goto err_disable_clk_slave_bus; |
275 | } | |
276 | ||
277 | ret = clk_enable(&eqos->clk_rx); | |
278 | if (ret < 0) { | |
f12001b1 | 279 | pr_err("clk_enable(clk_rx) failed: %d\n", ret); |
ba4dfef1 SW |
280 | goto err_disable_clk_master_bus; |
281 | } | |
282 | ||
283 | ret = clk_enable(&eqos->clk_ptp_ref); | |
284 | if (ret < 0) { | |
f12001b1 | 285 | pr_err("clk_enable(clk_ptp_ref) failed: %d\n", ret); |
ba4dfef1 SW |
286 | goto err_disable_clk_rx; |
287 | } | |
288 | ||
289 | ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000); | |
290 | if (ret < 0) { | |
f12001b1 | 291 | pr_err("clk_set_rate(clk_ptp_ref) failed: %d\n", ret); |
ba4dfef1 SW |
292 | goto err_disable_clk_ptp_ref; |
293 | } | |
294 | ||
295 | ret = clk_enable(&eqos->clk_tx); | |
296 | if (ret < 0) { | |
f12001b1 | 297 | pr_err("clk_enable(clk_tx) failed: %d\n", ret); |
ba4dfef1 SW |
298 | goto err_disable_clk_ptp_ref; |
299 | } | |
3a97da12 | 300 | #endif |
ba4dfef1 SW |
301 | |
302 | debug("%s: OK\n", __func__); | |
303 | return 0; | |
304 | ||
3a97da12 | 305 | #ifdef CONFIG_CLK |
ba4dfef1 SW |
306 | err_disable_clk_ptp_ref: |
307 | clk_disable(&eqos->clk_ptp_ref); | |
308 | err_disable_clk_rx: | |
309 | clk_disable(&eqos->clk_rx); | |
310 | err_disable_clk_master_bus: | |
311 | clk_disable(&eqos->clk_master_bus); | |
312 | err_disable_clk_slave_bus: | |
313 | clk_disable(&eqos->clk_slave_bus); | |
314 | err: | |
315 | debug("%s: FAILED: %d\n", __func__, ret); | |
316 | return ret; | |
3a97da12 | 317 | #endif |
ba4dfef1 SW |
318 | } |
319 | ||
c6a0df2d | 320 | static int eqos_stop_clks_tegra186(struct udevice *dev) |
ba4dfef1 | 321 | { |
3a97da12 | 322 | #ifdef CONFIG_CLK |
ba4dfef1 SW |
323 | struct eqos_priv *eqos = dev_get_priv(dev); |
324 | ||
325 | debug("%s(dev=%p):\n", __func__, dev); | |
326 | ||
327 | clk_disable(&eqos->clk_tx); | |
328 | clk_disable(&eqos->clk_ptp_ref); | |
329 | clk_disable(&eqos->clk_rx); | |
330 | clk_disable(&eqos->clk_master_bus); | |
331 | clk_disable(&eqos->clk_slave_bus); | |
3a97da12 | 332 | #endif |
ba4dfef1 SW |
333 | |
334 | debug("%s: OK\n", __func__); | |
c6a0df2d | 335 | return 0; |
ba4dfef1 SW |
336 | } |
337 | ||
338 | static int eqos_start_resets_tegra186(struct udevice *dev) | |
339 | { | |
340 | struct eqos_priv *eqos = dev_get_priv(dev); | |
341 | int ret; | |
342 | ||
343 | debug("%s(dev=%p):\n", __func__, dev); | |
344 | ||
345 | ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1); | |
346 | if (ret < 0) { | |
f12001b1 | 347 | pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d\n", ret); |
ba4dfef1 SW |
348 | return ret; |
349 | } | |
350 | ||
351 | udelay(2); | |
352 | ||
353 | ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); | |
354 | if (ret < 0) { | |
f12001b1 | 355 | pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d\n", ret); |
ba4dfef1 SW |
356 | return ret; |
357 | } | |
358 | ||
359 | ret = reset_assert(&eqos->reset_ctl); | |
360 | if (ret < 0) { | |
f12001b1 | 361 | pr_err("reset_assert() failed: %d\n", ret); |
ba4dfef1 SW |
362 | return ret; |
363 | } | |
364 | ||
365 | udelay(2); | |
366 | ||
367 | ret = reset_deassert(&eqos->reset_ctl); | |
368 | if (ret < 0) { | |
f12001b1 | 369 | pr_err("reset_deassert() failed: %d\n", ret); |
ba4dfef1 SW |
370 | return ret; |
371 | } | |
372 | ||
373 | debug("%s: OK\n", __func__); | |
374 | return 0; | |
375 | } | |
376 | ||
377 | static int eqos_stop_resets_tegra186(struct udevice *dev) | |
378 | { | |
379 | struct eqos_priv *eqos = dev_get_priv(dev); | |
380 | ||
381 | reset_assert(&eqos->reset_ctl); | |
382 | dm_gpio_set_value(&eqos->phy_reset_gpio, 1); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | static int eqos_calibrate_pads_tegra186(struct udevice *dev) | |
388 | { | |
389 | struct eqos_priv *eqos = dev_get_priv(dev); | |
390 | int ret; | |
391 | ||
392 | debug("%s(dev=%p):\n", __func__, dev); | |
393 | ||
394 | setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, | |
395 | EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); | |
396 | ||
397 | udelay(1); | |
398 | ||
399 | setbits_le32(&eqos->tegra186_regs->auto_cal_config, | |
400 | EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE); | |
401 | ||
48263504 ÁFR |
402 | ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, |
403 | EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false); | |
ba4dfef1 | 404 | if (ret) { |
f12001b1 | 405 | pr_err("calibrate didn't start\n"); |
ba4dfef1 SW |
406 | goto failed; |
407 | } | |
408 | ||
48263504 ÁFR |
409 | ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status, |
410 | EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false); | |
ba4dfef1 | 411 | if (ret) { |
f12001b1 | 412 | pr_err("calibrate didn't finish\n"); |
ba4dfef1 SW |
413 | goto failed; |
414 | } | |
415 | ||
416 | ret = 0; | |
417 | ||
418 | failed: | |
419 | clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl, | |
420 | EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD); | |
421 | ||
422 | debug("%s: returns %d\n", __func__, ret); | |
423 | ||
424 | return ret; | |
425 | } | |
426 | ||
427 | static int eqos_disable_calibration_tegra186(struct udevice *dev) | |
428 | { | |
429 | struct eqos_priv *eqos = dev_get_priv(dev); | |
430 | ||
431 | debug("%s(dev=%p):\n", __func__, dev); | |
432 | ||
433 | clrbits_le32(&eqos->tegra186_regs->auto_cal_config, | |
434 | EQOS_AUTO_CAL_CONFIG_ENABLE); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev) | |
440 | { | |
3a97da12 | 441 | #ifdef CONFIG_CLK |
ba4dfef1 SW |
442 | struct eqos_priv *eqos = dev_get_priv(dev); |
443 | ||
444 | return clk_get_rate(&eqos->clk_slave_bus); | |
3a97da12 FD |
445 | #else |
446 | return 0; | |
447 | #endif | |
ba4dfef1 SW |
448 | } |
449 | ||
450 | static int eqos_set_full_duplex(struct udevice *dev) | |
451 | { | |
452 | struct eqos_priv *eqos = dev_get_priv(dev); | |
453 | ||
454 | debug("%s(dev=%p):\n", __func__, dev); | |
455 | ||
456 | setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); | |
457 | ||
458 | return 0; | |
459 | } | |
460 | ||
461 | static int eqos_set_half_duplex(struct udevice *dev) | |
462 | { | |
463 | struct eqos_priv *eqos = dev_get_priv(dev); | |
464 | ||
465 | debug("%s(dev=%p):\n", __func__, dev); | |
466 | ||
467 | clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM); | |
468 | ||
469 | /* WAR: Flush TX queue when switching to half-duplex */ | |
470 | setbits_le32(&eqos->mtl_regs->txq0_operation_mode, | |
471 | EQOS_MTL_TXQ0_OPERATION_MODE_FTQ); | |
472 | ||
473 | return 0; | |
474 | } | |
475 | ||
476 | static int eqos_set_gmii_speed(struct udevice *dev) | |
477 | { | |
478 | struct eqos_priv *eqos = dev_get_priv(dev); | |
479 | ||
480 | debug("%s(dev=%p):\n", __func__, dev); | |
481 | ||
482 | clrbits_le32(&eqos->mac_regs->configuration, | |
483 | EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int eqos_set_mii_speed_100(struct udevice *dev) | |
489 | { | |
490 | struct eqos_priv *eqos = dev_get_priv(dev); | |
491 | ||
492 | debug("%s(dev=%p):\n", __func__, dev); | |
493 | ||
494 | setbits_le32(&eqos->mac_regs->configuration, | |
495 | EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES); | |
496 | ||
497 | return 0; | |
498 | } | |
499 | ||
500 | static int eqos_set_mii_speed_10(struct udevice *dev) | |
501 | { | |
502 | struct eqos_priv *eqos = dev_get_priv(dev); | |
503 | ||
504 | debug("%s(dev=%p):\n", __func__, dev); | |
505 | ||
506 | clrsetbits_le32(&eqos->mac_regs->configuration, | |
507 | EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS); | |
508 | ||
509 | return 0; | |
510 | } | |
511 | ||
512 | static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev) | |
513 | { | |
3a97da12 | 514 | #ifdef CONFIG_CLK |
ba4dfef1 SW |
515 | struct eqos_priv *eqos = dev_get_priv(dev); |
516 | ulong rate; | |
517 | int ret; | |
518 | ||
519 | debug("%s(dev=%p):\n", __func__, dev); | |
520 | ||
521 | switch (eqos->phy->speed) { | |
522 | case SPEED_1000: | |
523 | rate = 125 * 1000 * 1000; | |
524 | break; | |
525 | case SPEED_100: | |
526 | rate = 25 * 1000 * 1000; | |
527 | break; | |
528 | case SPEED_10: | |
529 | rate = 2.5 * 1000 * 1000; | |
530 | break; | |
531 | default: | |
f12001b1 | 532 | pr_err("invalid speed %d\n", eqos->phy->speed); |
ba4dfef1 SW |
533 | return -EINVAL; |
534 | } | |
535 | ||
536 | ret = clk_set_rate(&eqos->clk_tx, rate); | |
537 | if (ret < 0) { | |
f12001b1 | 538 | pr_err("clk_set_rate(tx_clk, %lu) failed: %d\n", rate, ret); |
ba4dfef1 SW |
539 | return ret; |
540 | } | |
3a97da12 | 541 | #endif |
ba4dfef1 SW |
542 | |
543 | return 0; | |
544 | } | |
545 | ||
546 | static int eqos_adjust_link(struct udevice *dev) | |
547 | { | |
548 | struct eqos_priv *eqos = dev_get_priv(dev); | |
549 | int ret; | |
550 | bool en_calibration; | |
551 | ||
552 | debug("%s(dev=%p):\n", __func__, dev); | |
553 | ||
554 | if (eqos->phy->duplex) | |
555 | ret = eqos_set_full_duplex(dev); | |
556 | else | |
557 | ret = eqos_set_half_duplex(dev); | |
558 | if (ret < 0) { | |
f12001b1 | 559 | pr_err("eqos_set_*_duplex() failed: %d\n", ret); |
ba4dfef1 SW |
560 | return ret; |
561 | } | |
562 | ||
563 | switch (eqos->phy->speed) { | |
564 | case SPEED_1000: | |
565 | en_calibration = true; | |
566 | ret = eqos_set_gmii_speed(dev); | |
567 | break; | |
568 | case SPEED_100: | |
569 | en_calibration = true; | |
570 | ret = eqos_set_mii_speed_100(dev); | |
571 | break; | |
572 | case SPEED_10: | |
573 | en_calibration = false; | |
574 | ret = eqos_set_mii_speed_10(dev); | |
575 | break; | |
576 | default: | |
f12001b1 | 577 | pr_err("invalid speed %d\n", eqos->phy->speed); |
ba4dfef1 SW |
578 | return -EINVAL; |
579 | } | |
580 | if (ret < 0) { | |
f12001b1 | 581 | pr_err("eqos_set_*mii_speed*() failed: %d\n", ret); |
ba4dfef1 SW |
582 | return ret; |
583 | } | |
584 | ||
585 | if (en_calibration) { | |
ac2d4efb | 586 | ret = eqos->config->ops->eqos_calibrate_pads(dev); |
ba4dfef1 | 587 | if (ret < 0) { |
f12001b1 | 588 | pr_err("eqos_calibrate_pads() failed: %d\n", |
ac2d4efb | 589 | ret); |
ba4dfef1 SW |
590 | return ret; |
591 | } | |
592 | } else { | |
ac2d4efb | 593 | ret = eqos->config->ops->eqos_disable_calibration(dev); |
ba4dfef1 | 594 | if (ret < 0) { |
f12001b1 | 595 | pr_err("eqos_disable_calibration() failed: %d\n", |
ac2d4efb | 596 | ret); |
ba4dfef1 SW |
597 | return ret; |
598 | } | |
599 | } | |
ac2d4efb | 600 | ret = eqos->config->ops->eqos_set_tx_clk_speed(dev); |
ba4dfef1 | 601 | if (ret < 0) { |
f12001b1 | 602 | pr_err("eqos_set_tx_clk_speed() failed: %d\n", ret); |
ba4dfef1 SW |
603 | return ret; |
604 | } | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
609 | static int eqos_write_hwaddr(struct udevice *dev) | |
610 | { | |
c69cda25 | 611 | struct eth_pdata *plat = dev_get_plat(dev); |
ba4dfef1 SW |
612 | struct eqos_priv *eqos = dev_get_priv(dev); |
613 | uint32_t val; | |
614 | ||
615 | /* | |
616 | * This function may be called before start() or after stop(). At that | |
617 | * time, on at least some configurations of the EQoS HW, all clocks to | |
618 | * the EQoS HW block will be stopped, and a reset signal applied. If | |
619 | * any register access is attempted in this state, bus timeouts or CPU | |
620 | * hangs may occur. This check prevents that. | |
621 | * | |
622 | * A simple solution to this problem would be to not implement | |
623 | * write_hwaddr(), since start() always writes the MAC address into HW | |
624 | * anyway. However, it is desirable to implement write_hwaddr() to | |
625 | * support the case of SW that runs subsequent to U-Boot which expects | |
626 | * the MAC address to already be programmed into the EQoS registers, | |
627 | * which must happen irrespective of whether the U-Boot user (or | |
628 | * scripts) actually made use of the EQoS device, and hence | |
629 | * irrespective of whether start() was ever called. | |
630 | * | |
631 | * Note that this requirement by subsequent SW is not valid for | |
632 | * Tegra186, and is likely not valid for any non-PCI instantiation of | |
633 | * the EQoS HW block. This function is implemented solely as | |
634 | * future-proofing with the expectation the driver will eventually be | |
635 | * ported to some system where the expectation above is true. | |
636 | */ | |
637 | if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok) | |
638 | return 0; | |
639 | ||
640 | /* Update the MAC address */ | |
641 | val = (plat->enetaddr[5] << 8) | | |
642 | (plat->enetaddr[4]); | |
643 | writel(val, &eqos->mac_regs->address0_high); | |
644 | val = (plat->enetaddr[3] << 24) | | |
645 | (plat->enetaddr[2] << 16) | | |
646 | (plat->enetaddr[1] << 8) | | |
647 | (plat->enetaddr[0]); | |
648 | writel(val, &eqos->mac_regs->address0_low); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
580fab4a YL |
653 | static int eqos_read_rom_hwaddr(struct udevice *dev) |
654 | { | |
c69cda25 | 655 | struct eth_pdata *pdata = dev_get_plat(dev); |
a6242514 PF |
656 | struct eqos_priv *eqos = dev_get_priv(dev); |
657 | int ret; | |
658 | ||
659 | ret = eqos->config->ops->eqos_get_enetaddr(dev); | |
660 | if (ret < 0) | |
661 | return ret; | |
580fab4a | 662 | |
580fab4a YL |
663 | return !is_valid_ethaddr(pdata->enetaddr); |
664 | } | |
665 | ||
a6acf955 YL |
666 | static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev) |
667 | { | |
668 | struct ofnode_phandle_args phandle_args; | |
669 | int reg; | |
670 | ||
671 | if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, | |
672 | &phandle_args)) { | |
673 | debug("Failed to find phy-handle"); | |
674 | return -ENODEV; | |
675 | } | |
676 | ||
677 | priv->phy_of_node = phandle_args.node; | |
678 | ||
679 | reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); | |
680 | ||
681 | return reg; | |
682 | } | |
683 | ||
ba4dfef1 SW |
684 | static int eqos_start(struct udevice *dev) |
685 | { | |
686 | struct eqos_priv *eqos = dev_get_priv(dev); | |
687 | int ret, i; | |
688 | ulong rate; | |
689 | u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl; | |
690 | ulong last_rx_desc; | |
6f1e668d | 691 | ulong desc_pad; |
5d260d08 | 692 | ulong addr64; |
ba4dfef1 SW |
693 | |
694 | debug("%s(dev=%p):\n", __func__, dev); | |
695 | ||
696 | eqos->tx_desc_idx = 0; | |
697 | eqos->rx_desc_idx = 0; | |
698 | ||
ac2d4efb | 699 | ret = eqos->config->ops->eqos_start_resets(dev); |
ba4dfef1 | 700 | if (ret < 0) { |
f12001b1 | 701 | pr_err("eqos_start_resets() failed: %d\n", ret); |
3fbd17aa | 702 | goto err; |
ba4dfef1 SW |
703 | } |
704 | ||
705 | udelay(10); | |
706 | ||
707 | eqos->reg_access_ok = true; | |
708 | ||
a79de080 MV |
709 | /* |
710 | * Assert the SWR first, the actually reset the MAC and to latch in | |
711 | * e.g. i.MX8M Plus GPR[1] content, which selects interface mode. | |
712 | */ | |
713 | setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR); | |
714 | ||
48263504 | 715 | ret = wait_for_bit_le32(&eqos->dma_regs->mode, |
ac2d4efb CR |
716 | EQOS_DMA_MODE_SWR, false, |
717 | eqos->config->swr_wait, false); | |
ba4dfef1 | 718 | if (ret) { |
f12001b1 | 719 | pr_err("EQOS_DMA_MODE_SWR stuck\n"); |
ba4dfef1 SW |
720 | goto err_stop_resets; |
721 | } | |
722 | ||
ac2d4efb | 723 | ret = eqos->config->ops->eqos_calibrate_pads(dev); |
ba4dfef1 | 724 | if (ret < 0) { |
f12001b1 | 725 | pr_err("eqos_calibrate_pads() failed: %d\n", ret); |
ba4dfef1 SW |
726 | goto err_stop_resets; |
727 | } | |
728 | ||
9d53f335 SG |
729 | if (eqos->config->ops->eqos_get_tick_clk_rate) { |
730 | rate = eqos->config->ops->eqos_get_tick_clk_rate(dev); | |
731 | ||
732 | val = (rate / 1000000) - 1; | |
733 | writel(val, &eqos->mac_regs->us_tic_counter); | |
734 | } | |
ba4dfef1 | 735 | |
ac2d4efb CR |
736 | /* |
737 | * if PHY was already connected and configured, | |
738 | * don't need to reconnect/reconfigure again | |
739 | */ | |
ba4dfef1 | 740 | if (!eqos->phy) { |
6a895d03 | 741 | int addr = -1; |
96d58eca EP |
742 | ofnode fixed_node; |
743 | ||
744 | if (IS_ENABLED(CONFIG_PHY_FIXED)) { | |
745 | fixed_node = ofnode_find_subnode(dev_ofnode(dev), | |
746 | "fixed-link"); | |
747 | if (ofnode_valid(fixed_node)) | |
748 | eqos->phy = fixed_phy_create(dev_ofnode(dev)); | |
749 | } | |
750 | ||
751 | if (!eqos->phy) { | |
752 | addr = eqos_get_phy_addr(eqos, dev); | |
753 | eqos->phy = phy_connect(eqos->mii, addr, dev, | |
754 | eqos->config->interface(dev)); | |
755 | } | |
756 | ||
ac2d4efb | 757 | if (!eqos->phy) { |
f12001b1 | 758 | pr_err("phy_connect() failed\n"); |
ded6014d | 759 | ret = -ENODEV; |
ac2d4efb CR |
760 | goto err_stop_resets; |
761 | } | |
4f60a51d PD |
762 | |
763 | if (eqos->max_speed) { | |
764 | ret = phy_set_supported(eqos->phy, eqos->max_speed); | |
765 | if (ret) { | |
f12001b1 | 766 | pr_err("phy_set_supported() failed: %d\n", ret); |
4f60a51d PD |
767 | goto err_shutdown_phy; |
768 | } | |
769 | } | |
770 | ||
a6acf955 | 771 | eqos->phy->node = eqos->phy_of_node; |
ac2d4efb CR |
772 | ret = phy_config(eqos->phy); |
773 | if (ret < 0) { | |
f12001b1 | 774 | pr_err("phy_config() failed: %d\n", ret); |
ac2d4efb CR |
775 | goto err_shutdown_phy; |
776 | } | |
ba4dfef1 | 777 | } |
ac2d4efb | 778 | |
ba4dfef1 SW |
779 | ret = phy_startup(eqos->phy); |
780 | if (ret < 0) { | |
f12001b1 | 781 | pr_err("phy_startup() failed: %d\n", ret); |
ba4dfef1 SW |
782 | goto err_shutdown_phy; |
783 | } | |
784 | ||
785 | if (!eqos->phy->link) { | |
f12001b1 | 786 | pr_err("No link\n"); |
ded6014d | 787 | ret = -EAGAIN; |
ba4dfef1 SW |
788 | goto err_shutdown_phy; |
789 | } | |
790 | ||
791 | ret = eqos_adjust_link(dev); | |
792 | if (ret < 0) { | |
f12001b1 | 793 | pr_err("eqos_adjust_link() failed: %d\n", ret); |
ba4dfef1 SW |
794 | goto err_shutdown_phy; |
795 | } | |
796 | ||
797 | /* Configure MTL */ | |
798 | ||
799 | /* Enable Store and Forward mode for TX */ | |
800 | /* Program Tx operating mode */ | |
801 | setbits_le32(&eqos->mtl_regs->txq0_operation_mode, | |
802 | EQOS_MTL_TXQ0_OPERATION_MODE_TSF | | |
803 | (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED << | |
804 | EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)); | |
805 | ||
806 | /* Transmit Queue weight */ | |
807 | writel(0x10, &eqos->mtl_regs->txq0_quantum_weight); | |
808 | ||
809 | /* Enable Store and Forward mode for RX, since no jumbo frame */ | |
810 | setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, | |
f024e0b2 | 811 | EQOS_MTL_RXQ0_OPERATION_MODE_RSF); |
ba4dfef1 SW |
812 | |
813 | /* Transmit/Receive queue fifo size; use all RAM for 1 queue */ | |
814 | val = readl(&eqos->mac_regs->hw_feature1); | |
815 | tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & | |
816 | EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK; | |
817 | rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & | |
818 | EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK; | |
819 | ||
a962b7cf SG |
820 | /* r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting */ |
821 | tx_fifo_sz = 128 << tx_fifo_sz; | |
822 | rx_fifo_sz = 128 << rx_fifo_sz; | |
823 | ||
824 | /* Allow platform to override TX/RX fifo size */ | |
825 | if (eqos->tx_fifo_sz) | |
826 | tx_fifo_sz = eqos->tx_fifo_sz; | |
827 | if (eqos->rx_fifo_sz) | |
828 | rx_fifo_sz = eqos->rx_fifo_sz; | |
829 | ||
830 | /* r/tqs is encoded as (n / 256) - 1 */ | |
831 | tqs = tx_fifo_sz / 256 - 1; | |
832 | rqs = rx_fifo_sz / 256 - 1; | |
ba4dfef1 SW |
833 | |
834 | clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode, | |
835 | EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK << | |
836 | EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT, | |
837 | tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT); | |
838 | clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, | |
839 | EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK << | |
840 | EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT, | |
841 | rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT); | |
842 | ||
843 | /* Flow control used only if each channel gets 4KB or more FIFO */ | |
844 | if (rqs >= ((4096 / 256) - 1)) { | |
845 | u32 rfd, rfa; | |
846 | ||
847 | setbits_le32(&eqos->mtl_regs->rxq0_operation_mode, | |
848 | EQOS_MTL_RXQ0_OPERATION_MODE_EHFC); | |
849 | ||
850 | /* | |
851 | * Set Threshold for Activating Flow Contol space for min 2 | |
852 | * frames ie, (1500 * 1) = 1500 bytes. | |
853 | * | |
854 | * Set Threshold for Deactivating Flow Contol for space of | |
855 | * min 1 frame (frame size 1500bytes) in receive fifo | |
856 | */ | |
857 | if (rqs == ((4096 / 256) - 1)) { | |
858 | /* | |
859 | * This violates the above formula because of FIFO size | |
860 | * limit therefore overflow may occur inspite of this. | |
861 | */ | |
862 | rfd = 0x3; /* Full-3K */ | |
863 | rfa = 0x1; /* Full-1.5K */ | |
864 | } else if (rqs == ((8192 / 256) - 1)) { | |
865 | rfd = 0x6; /* Full-4K */ | |
866 | rfa = 0xa; /* Full-6K */ | |
867 | } else if (rqs == ((16384 / 256) - 1)) { | |
868 | rfd = 0x6; /* Full-4K */ | |
869 | rfa = 0x12; /* Full-10K */ | |
870 | } else { | |
871 | rfd = 0x6; /* Full-4K */ | |
872 | rfa = 0x1E; /* Full-16K */ | |
873 | } | |
874 | ||
875 | clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode, | |
876 | (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK << | |
877 | EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | | |
878 | (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK << | |
879 | EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT), | |
880 | (rfd << | |
881 | EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) | | |
882 | (rfa << | |
883 | EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)); | |
884 | } | |
885 | ||
886 | /* Configure MAC */ | |
887 | ||
888 | clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0, | |
889 | EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK << | |
890 | EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT, | |
ac2d4efb | 891 | eqos->config->config_mac << |
ba4dfef1 SW |
892 | EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT); |
893 | ||
3a97da12 FD |
894 | /* Multicast and Broadcast Queue Enable */ |
895 | setbits_le32(&eqos->mac_regs->unused_0a4, | |
896 | 0x00100000); | |
897 | /* enable promise mode */ | |
898 | setbits_le32(&eqos->mac_regs->unused_004[1], | |
899 | 0x1); | |
900 | ||
ba4dfef1 SW |
901 | /* Set TX flow control parameters */ |
902 | /* Set Pause Time */ | |
903 | setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, | |
904 | 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT); | |
905 | /* Assign priority for TX flow control */ | |
906 | clrbits_le32(&eqos->mac_regs->txq_prty_map0, | |
907 | EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK << | |
908 | EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT); | |
909 | /* Assign priority for RX flow control */ | |
910 | clrbits_le32(&eqos->mac_regs->rxq_ctrl2, | |
911 | EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK << | |
912 | EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT); | |
913 | /* Enable flow control */ | |
914 | setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl, | |
915 | EQOS_MAC_Q0_TX_FLOW_CTRL_TFE); | |
916 | setbits_le32(&eqos->mac_regs->rx_flow_ctrl, | |
917 | EQOS_MAC_RX_FLOW_CTRL_RFE); | |
918 | ||
919 | clrsetbits_le32(&eqos->mac_regs->configuration, | |
920 | EQOS_MAC_CONFIGURATION_GPSLCE | | |
921 | EQOS_MAC_CONFIGURATION_WD | | |
922 | EQOS_MAC_CONFIGURATION_JD | | |
923 | EQOS_MAC_CONFIGURATION_JE, | |
924 | EQOS_MAC_CONFIGURATION_CST | | |
925 | EQOS_MAC_CONFIGURATION_ACS); | |
926 | ||
927 | eqos_write_hwaddr(dev); | |
928 | ||
929 | /* Configure DMA */ | |
930 | ||
931 | /* Enable OSP mode */ | |
932 | setbits_le32(&eqos->dma_regs->ch0_tx_control, | |
933 | EQOS_DMA_CH0_TX_CONTROL_OSP); | |
934 | ||
935 | /* RX buffer size. Must be a multiple of bus width */ | |
936 | clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, | |
937 | EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK << | |
938 | EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT, | |
939 | EQOS_MAX_PACKET_SIZE << | |
940 | EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT); | |
941 | ||
6f1e668d MV |
942 | desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) / |
943 | eqos->config->axi_bus_width; | |
944 | ||
ba4dfef1 | 945 | setbits_le32(&eqos->dma_regs->ch0_control, |
6f1e668d MV |
946 | EQOS_DMA_CH0_CONTROL_PBLX8 | |
947 | (desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT)); | |
ba4dfef1 SW |
948 | |
949 | /* | |
950 | * Burst length must be < 1/2 FIFO size. | |
951 | * FIFO size in tqs is encoded as (n / 256) - 1. | |
952 | * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes. | |
953 | * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1. | |
954 | */ | |
955 | pbl = tqs + 1; | |
956 | if (pbl > 32) | |
957 | pbl = 32; | |
958 | clrsetbits_le32(&eqos->dma_regs->ch0_tx_control, | |
959 | EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK << | |
960 | EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT, | |
961 | pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT); | |
962 | ||
963 | clrsetbits_le32(&eqos->dma_regs->ch0_rx_control, | |
964 | EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK << | |
965 | EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT, | |
966 | 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT); | |
967 | ||
968 | /* DMA performance configuration */ | |
969 | val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) | | |
970 | EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 | | |
971 | EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4; | |
972 | writel(val, &eqos->dma_regs->sysbus_mode); | |
973 | ||
974 | /* Set up descriptors */ | |
975 | ||
f94d008a MV |
976 | memset(eqos->tx_descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_TX); |
977 | memset(eqos->rx_descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_RX); | |
6f1e668d MV |
978 | |
979 | for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) { | |
980 | struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false); | |
981 | eqos->config->ops->eqos_flush_desc(tx_desc); | |
982 | } | |
983 | ||
ba4dfef1 | 984 | for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) { |
6f1e668d | 985 | struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true); |
5d260d08 LFT |
986 | |
987 | addr64 = (ulong)(eqos->rx_dma_buf + (i * EQOS_MAX_PACKET_SIZE)); | |
988 | rx_desc->des0 = lower_32_bits(addr64); | |
989 | rx_desc->des1 = upper_32_bits(addr64); | |
4332d806 | 990 | rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; |
3a97da12 | 991 | mb(); |
dd90c2e1 | 992 | eqos->config->ops->eqos_flush_desc(rx_desc); |
5d260d08 | 993 | eqos->config->ops->eqos_inval_buffer((void *)addr64, EQOS_MAX_PACKET_SIZE); |
ba4dfef1 | 994 | } |
ba4dfef1 | 995 | |
5d260d08 LFT |
996 | addr64 = (ulong)eqos_get_desc(eqos, 0, false); |
997 | writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_haddress); | |
998 | writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_txdesc_list_address); | |
ba4dfef1 SW |
999 | writel(EQOS_DESCRIPTORS_TX - 1, |
1000 | &eqos->dma_regs->ch0_txdesc_ring_length); | |
1001 | ||
5d260d08 LFT |
1002 | addr64 = (ulong)eqos_get_desc(eqos, 0, true); |
1003 | writel(upper_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_haddress); | |
1004 | writel(lower_32_bits(addr64), &eqos->dma_regs->ch0_rxdesc_list_address); | |
ba4dfef1 SW |
1005 | writel(EQOS_DESCRIPTORS_RX - 1, |
1006 | &eqos->dma_regs->ch0_rxdesc_ring_length); | |
1007 | ||
1008 | /* Enable everything */ | |
ba4dfef1 SW |
1009 | setbits_le32(&eqos->dma_regs->ch0_tx_control, |
1010 | EQOS_DMA_CH0_TX_CONTROL_ST); | |
1011 | setbits_le32(&eqos->dma_regs->ch0_rx_control, | |
1012 | EQOS_DMA_CH0_RX_CONTROL_SR); | |
3a97da12 FD |
1013 | setbits_le32(&eqos->mac_regs->configuration, |
1014 | EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); | |
ba4dfef1 SW |
1015 | |
1016 | /* TX tail pointer not written until we need to TX a packet */ | |
1017 | /* | |
1018 | * Point RX tail pointer at last descriptor. Ideally, we'd point at the | |
1019 | * first descriptor, implying all descriptors were available. However, | |
1020 | * that's not distinguishable from none of the descriptors being | |
1021 | * available. | |
1022 | */ | |
6f1e668d | 1023 | last_rx_desc = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true); |
ba4dfef1 SW |
1024 | writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); |
1025 | ||
1026 | eqos->started = true; | |
1027 | ||
1028 | debug("%s: OK\n", __func__); | |
1029 | return 0; | |
1030 | ||
1031 | err_shutdown_phy: | |
1032 | phy_shutdown(eqos->phy); | |
ba4dfef1 | 1033 | err_stop_resets: |
ac2d4efb | 1034 | eqos->config->ops->eqos_stop_resets(dev); |
ba4dfef1 | 1035 | err: |
f12001b1 | 1036 | pr_err("FAILED: %d\n", ret); |
ba4dfef1 SW |
1037 | return ret; |
1038 | } | |
1039 | ||
50d86e55 | 1040 | static void eqos_stop(struct udevice *dev) |
ba4dfef1 SW |
1041 | { |
1042 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1043 | int i; | |
1044 | ||
1045 | debug("%s(dev=%p):\n", __func__, dev); | |
1046 | ||
1047 | if (!eqos->started) | |
1048 | return; | |
1049 | eqos->started = false; | |
1050 | eqos->reg_access_ok = false; | |
1051 | ||
1052 | /* Disable TX DMA */ | |
1053 | clrbits_le32(&eqos->dma_regs->ch0_tx_control, | |
1054 | EQOS_DMA_CH0_TX_CONTROL_ST); | |
1055 | ||
1056 | /* Wait for TX all packets to drain out of MTL */ | |
1057 | for (i = 0; i < 1000000; i++) { | |
1058 | u32 val = readl(&eqos->mtl_regs->txq0_debug); | |
1059 | u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & | |
1060 | EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK; | |
1061 | u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS; | |
1062 | if ((trcsts != 1) && (!txqsts)) | |
1063 | break; | |
1064 | } | |
1065 | ||
1066 | /* Turn off MAC TX and RX */ | |
1067 | clrbits_le32(&eqos->mac_regs->configuration, | |
1068 | EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE); | |
1069 | ||
1070 | /* Wait for all RX packets to drain out of MTL */ | |
1071 | for (i = 0; i < 1000000; i++) { | |
1072 | u32 val = readl(&eqos->mtl_regs->rxq0_debug); | |
1073 | u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & | |
1074 | EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK; | |
1075 | u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & | |
1076 | EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK; | |
1077 | if ((!prxq) && (!rxqsts)) | |
1078 | break; | |
1079 | } | |
1080 | ||
1081 | /* Turn off RX DMA */ | |
1082 | clrbits_le32(&eqos->dma_regs->ch0_rx_control, | |
1083 | EQOS_DMA_CH0_RX_CONTROL_SR); | |
1084 | ||
1085 | if (eqos->phy) { | |
1086 | phy_shutdown(eqos->phy); | |
ba4dfef1 | 1087 | } |
ac2d4efb | 1088 | eqos->config->ops->eqos_stop_resets(dev); |
ba4dfef1 SW |
1089 | |
1090 | debug("%s: OK\n", __func__); | |
1091 | } | |
1092 | ||
50d86e55 | 1093 | static int eqos_send(struct udevice *dev, void *packet, int length) |
ba4dfef1 SW |
1094 | { |
1095 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1096 | struct eqos_desc *tx_desc; | |
1097 | int i; | |
1098 | ||
1099 | debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet, | |
1100 | length); | |
1101 | ||
1102 | memcpy(eqos->tx_dma_buf, packet, length); | |
ac2d4efb | 1103 | eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length); |
ba4dfef1 | 1104 | |
6f1e668d | 1105 | tx_desc = eqos_get_desc(eqos, eqos->tx_desc_idx, false); |
ba4dfef1 SW |
1106 | eqos->tx_desc_idx++; |
1107 | eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX; | |
1108 | ||
5d260d08 LFT |
1109 | tx_desc->des0 = lower_32_bits((ulong)eqos->tx_dma_buf); |
1110 | tx_desc->des1 = upper_32_bits((ulong)eqos->tx_dma_buf); | |
ba4dfef1 SW |
1111 | tx_desc->des2 = length; |
1112 | /* | |
1113 | * Make sure that if HW sees the _OWN write below, it will see all the | |
1114 | * writes to the rest of the descriptor too. | |
1115 | */ | |
1116 | mb(); | |
1117 | tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length; | |
ac2d4efb | 1118 | eqos->config->ops->eqos_flush_desc(tx_desc); |
ba4dfef1 | 1119 | |
6f1e668d | 1120 | writel((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false), |
83858d87 | 1121 | &eqos->dma_regs->ch0_txdesc_tail_pointer); |
ba4dfef1 SW |
1122 | |
1123 | for (i = 0; i < 1000000; i++) { | |
ac2d4efb | 1124 | eqos->config->ops->eqos_inval_desc(tx_desc); |
ba4dfef1 SW |
1125 | if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) |
1126 | return 0; | |
1127 | udelay(1); | |
1128 | } | |
1129 | ||
1130 | debug("%s: TX timeout\n", __func__); | |
1131 | ||
1132 | return -ETIMEDOUT; | |
1133 | } | |
1134 | ||
50d86e55 | 1135 | static int eqos_recv(struct udevice *dev, int flags, uchar **packetp) |
ba4dfef1 SW |
1136 | { |
1137 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1138 | struct eqos_desc *rx_desc; | |
1139 | int length; | |
1140 | ||
6f1e668d | 1141 | rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true); |
738ee270 | 1142 | eqos->config->ops->eqos_inval_desc(rx_desc); |
95446f4a | 1143 | if (rx_desc->des3 & EQOS_DESC3_OWN) |
ba4dfef1 | 1144 | return -EAGAIN; |
95446f4a JK |
1145 | |
1146 | debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags); | |
ba4dfef1 SW |
1147 | |
1148 | *packetp = eqos->rx_dma_buf + | |
1149 | (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); | |
1150 | length = rx_desc->des3 & 0x7fff; | |
1151 | debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length); | |
1152 | ||
ac2d4efb | 1153 | eqos->config->ops->eqos_inval_buffer(*packetp, length); |
ba4dfef1 SW |
1154 | |
1155 | return length; | |
1156 | } | |
1157 | ||
50d86e55 | 1158 | static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length) |
ba4dfef1 SW |
1159 | { |
1160 | struct eqos_priv *eqos = dev_get_priv(dev); | |
e9d3fc7e | 1161 | u32 idx, idx_mask = eqos->desc_per_cacheline - 1; |
ba4dfef1 | 1162 | uchar *packet_expected; |
b4e9b524 | 1163 | struct eqos_desc *rx_desc = NULL; |
ba4dfef1 SW |
1164 | |
1165 | debug("%s(packet=%p, length=%d)\n", __func__, packet, length); | |
1166 | ||
1167 | packet_expected = eqos->rx_dma_buf + | |
1168 | (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE); | |
1169 | if (packet != packet_expected) { | |
1170 | debug("%s: Unexpected packet (expected %p)\n", __func__, | |
1171 | packet_expected); | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | ||
3a97da12 FD |
1175 | eqos->config->ops->eqos_inval_buffer(packet, length); |
1176 | ||
e9d3fc7e MV |
1177 | if ((eqos->rx_desc_idx & idx_mask) == idx_mask) { |
1178 | for (idx = eqos->rx_desc_idx - idx_mask; | |
1179 | idx <= eqos->rx_desc_idx; | |
1180 | idx++) { | |
5d260d08 LFT |
1181 | ulong addr64; |
1182 | ||
e9d3fc7e MV |
1183 | rx_desc = eqos_get_desc(eqos, idx, true); |
1184 | rx_desc->des0 = 0; | |
5d260d08 | 1185 | rx_desc->des1 = 0; |
e9d3fc7e MV |
1186 | mb(); |
1187 | eqos->config->ops->eqos_flush_desc(rx_desc); | |
1188 | eqos->config->ops->eqos_inval_buffer(packet, length); | |
5d260d08 LFT |
1189 | addr64 = (ulong)(eqos->rx_dma_buf + (idx * EQOS_MAX_PACKET_SIZE)); |
1190 | rx_desc->des0 = lower_32_bits(addr64); | |
1191 | rx_desc->des1 = upper_32_bits(addr64); | |
e9d3fc7e MV |
1192 | rx_desc->des2 = 0; |
1193 | /* | |
1194 | * Make sure that if HW sees the _OWN write below, | |
1195 | * it will see all the writes to the rest of the | |
1196 | * descriptor too. | |
1197 | */ | |
1198 | mb(); | |
1199 | rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V; | |
1200 | eqos->config->ops->eqos_flush_desc(rx_desc); | |
1201 | } | |
1202 | writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer); | |
1203 | } | |
ba4dfef1 SW |
1204 | |
1205 | eqos->rx_desc_idx++; | |
1206 | eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX; | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | static int eqos_probe_resources_core(struct udevice *dev) | |
1212 | { | |
1213 | struct eqos_priv *eqos = dev_get_priv(dev); | |
e9d3fc7e | 1214 | unsigned int desc_step; |
ba4dfef1 SW |
1215 | int ret; |
1216 | ||
1217 | debug("%s(dev=%p):\n", __func__, dev); | |
1218 | ||
e9d3fc7e MV |
1219 | /* Maximum distance between neighboring descriptors, in Bytes. */ |
1220 | desc_step = sizeof(struct eqos_desc) + | |
1221 | EQOS_DMA_CH0_CONTROL_DSL_MASK * eqos->config->axi_bus_width; | |
1222 | if (desc_step < ARCH_DMA_MINALIGN) { | |
1223 | /* | |
1224 | * The EQoS hardware implementation cannot place one descriptor | |
1225 | * per cacheline, it is necessary to place multiple descriptors | |
1226 | * per cacheline in memory and do cache management carefully. | |
1227 | */ | |
1228 | eqos->desc_size = BIT(fls(desc_step) - 1); | |
1229 | } else { | |
1230 | eqos->desc_size = ALIGN(sizeof(struct eqos_desc), | |
1231 | (unsigned int)ARCH_DMA_MINALIGN); | |
1232 | } | |
1233 | eqos->desc_per_cacheline = ARCH_DMA_MINALIGN / eqos->desc_size; | |
f94d008a MV |
1234 | |
1235 | eqos->tx_descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_TX); | |
1236 | if (!eqos->tx_descs) { | |
1237 | debug("%s: eqos_alloc_descs(tx) failed\n", __func__); | |
ba4dfef1 SW |
1238 | ret = -ENOMEM; |
1239 | goto err; | |
1240 | } | |
ba4dfef1 | 1241 | |
f94d008a MV |
1242 | eqos->rx_descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_RX); |
1243 | if (!eqos->rx_descs) { | |
1244 | debug("%s: eqos_alloc_descs(rx) failed\n", __func__); | |
1245 | ret = -ENOMEM; | |
1246 | goto err_free_tx_descs; | |
1247 | } | |
1248 | ||
ba4dfef1 SW |
1249 | eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE); |
1250 | if (!eqos->tx_dma_buf) { | |
1251 | debug("%s: memalign(tx_dma_buf) failed\n", __func__); | |
1252 | ret = -ENOMEM; | |
1253 | goto err_free_descs; | |
1254 | } | |
ac2d4efb | 1255 | debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf); |
ba4dfef1 SW |
1256 | |
1257 | eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE); | |
1258 | if (!eqos->rx_dma_buf) { | |
1259 | debug("%s: memalign(rx_dma_buf) failed\n", __func__); | |
1260 | ret = -ENOMEM; | |
1261 | goto err_free_tx_dma_buf; | |
1262 | } | |
ac2d4efb | 1263 | debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf); |
ba4dfef1 | 1264 | |
a83ca0c2 MV |
1265 | eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf, |
1266 | EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX); | |
1267 | ||
ba4dfef1 SW |
1268 | debug("%s: OK\n", __func__); |
1269 | return 0; | |
1270 | ||
ba4dfef1 SW |
1271 | err_free_tx_dma_buf: |
1272 | free(eqos->tx_dma_buf); | |
1273 | err_free_descs: | |
f94d008a MV |
1274 | eqos_free_descs(eqos->rx_descs); |
1275 | err_free_tx_descs: | |
1276 | eqos_free_descs(eqos->tx_descs); | |
ba4dfef1 SW |
1277 | err: |
1278 | ||
1279 | debug("%s: returns %d\n", __func__, ret); | |
1280 | return ret; | |
1281 | } | |
1282 | ||
1283 | static int eqos_remove_resources_core(struct udevice *dev) | |
1284 | { | |
1285 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1286 | ||
1287 | debug("%s(dev=%p):\n", __func__, dev); | |
1288 | ||
ba4dfef1 SW |
1289 | free(eqos->rx_dma_buf); |
1290 | free(eqos->tx_dma_buf); | |
f94d008a MV |
1291 | eqos_free_descs(eqos->rx_descs); |
1292 | eqos_free_descs(eqos->tx_descs); | |
ba4dfef1 SW |
1293 | |
1294 | debug("%s: OK\n", __func__); | |
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | static int eqos_probe_resources_tegra186(struct udevice *dev) | |
1299 | { | |
1300 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1301 | int ret; | |
1302 | ||
1303 | debug("%s(dev=%p):\n", __func__, dev); | |
1304 | ||
beabef65 PO |
1305 | ret = eqos_get_base_addr_dt(dev); |
1306 | if (ret) { | |
1307 | pr_err("eqos_get_base_addr_dt failed: %d\n", ret); | |
1308 | return ret; | |
1309 | } | |
1310 | eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE); | |
1311 | ||
ba4dfef1 SW |
1312 | ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl); |
1313 | if (ret) { | |
f12001b1 | 1314 | pr_err("reset_get_by_name(rst) failed: %d\n", ret); |
ba4dfef1 SW |
1315 | return ret; |
1316 | } | |
1317 | ||
1318 | ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, | |
1319 | &eqos->phy_reset_gpio, | |
1320 | GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); | |
1321 | if (ret) { | |
f12001b1 | 1322 | pr_err("gpio_request_by_name(phy reset) failed: %d\n", ret); |
ba4dfef1 SW |
1323 | goto err_free_reset_eqos; |
1324 | } | |
1325 | ||
1326 | ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus); | |
1327 | if (ret) { | |
f12001b1 | 1328 | pr_err("clk_get_by_name(slave_bus) failed: %d\n", ret); |
ba4dfef1 SW |
1329 | goto err_free_gpio_phy_reset; |
1330 | } | |
1331 | ||
1332 | ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus); | |
1333 | if (ret) { | |
f12001b1 | 1334 | pr_err("clk_get_by_name(master_bus) failed: %d\n", ret); |
c9309f40 | 1335 | goto err_free_gpio_phy_reset; |
ba4dfef1 SW |
1336 | } |
1337 | ||
1338 | ret = clk_get_by_name(dev, "rx", &eqos->clk_rx); | |
1339 | if (ret) { | |
f12001b1 | 1340 | pr_err("clk_get_by_name(rx) failed: %d\n", ret); |
c9309f40 | 1341 | goto err_free_gpio_phy_reset; |
ba4dfef1 SW |
1342 | } |
1343 | ||
1344 | ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref); | |
1345 | if (ret) { | |
f12001b1 | 1346 | pr_err("clk_get_by_name(ptp_ref) failed: %d\n", ret); |
c9309f40 | 1347 | goto err_free_gpio_phy_reset; |
ba4dfef1 SW |
1348 | } |
1349 | ||
1350 | ret = clk_get_by_name(dev, "tx", &eqos->clk_tx); | |
1351 | if (ret) { | |
f12001b1 | 1352 | pr_err("clk_get_by_name(tx) failed: %d\n", ret); |
c9309f40 | 1353 | goto err_free_gpio_phy_reset; |
ba4dfef1 SW |
1354 | } |
1355 | ||
1356 | debug("%s: OK\n", __func__); | |
1357 | return 0; | |
1358 | ||
ba4dfef1 SW |
1359 | err_free_gpio_phy_reset: |
1360 | dm_gpio_free(dev, &eqos->phy_reset_gpio); | |
1361 | err_free_reset_eqos: | |
1362 | reset_free(&eqos->reset_ctl); | |
1363 | ||
1364 | debug("%s: returns %d\n", __func__, ret); | |
1365 | return ret; | |
1366 | } | |
1367 | ||
123ca114 | 1368 | static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev) |
ac2d4efb CR |
1369 | { |
1370 | return PHY_INTERFACE_MODE_MII; | |
1371 | } | |
1372 | ||
ba4dfef1 SW |
1373 | static int eqos_remove_resources_tegra186(struct udevice *dev) |
1374 | { | |
1375 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1376 | ||
1377 | debug("%s(dev=%p):\n", __func__, dev); | |
1378 | ||
ba4dfef1 SW |
1379 | dm_gpio_free(dev, &eqos->phy_reset_gpio); |
1380 | reset_free(&eqos->reset_ctl); | |
1381 | ||
1382 | debug("%s: OK\n", __func__); | |
1383 | return 0; | |
1384 | } | |
1385 | ||
2689b14e PO |
1386 | static int eqos_bind(struct udevice *dev) |
1387 | { | |
1388 | static int dev_num; | |
1389 | const size_t name_sz = 16; | |
1390 | char name[name_sz]; | |
1391 | ||
1392 | /* Device name defaults to DT node name. */ | |
1393 | if (ofnode_valid(dev_ofnode(dev))) | |
1394 | return 0; | |
1395 | ||
1396 | /* Assign unique names in case there is no DT node. */ | |
1397 | snprintf(name, name_sz, "eth_eqos#%d", dev_num++); | |
1398 | return device_set_name(dev, name); | |
1399 | } | |
1400 | ||
beabef65 PO |
1401 | /* |
1402 | * Get driver data based on the device tree. Boards not using a device tree can | |
1403 | * overwrite this function. | |
1404 | */ | |
1405 | __weak void *eqos_get_driver_data(struct udevice *dev) | |
1406 | { | |
1407 | return (void *)dev_get_driver_data(dev); | |
1408 | } | |
1409 | ||
1410 | static fdt_addr_t eqos_get_base_addr_common(struct udevice *dev, fdt_addr_t addr) | |
1411 | { | |
1412 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1413 | ||
1414 | if (addr == FDT_ADDR_T_NONE) { | |
1415 | #if CONFIG_IS_ENABLED(FDT_64BIT) | |
1416 | dev_err(dev, "addr=0x%llx is invalid.\n", addr); | |
1417 | #else | |
1418 | dev_err(dev, "addr=0x%x is invalid.\n", addr); | |
1419 | #endif | |
1420 | return -EINVAL; | |
1421 | } | |
1422 | ||
1423 | eqos->regs = addr; | |
1424 | eqos->mac_regs = (void *)(addr + EQOS_MAC_REGS_BASE); | |
1425 | eqos->mtl_regs = (void *)(addr + EQOS_MTL_REGS_BASE); | |
1426 | eqos->dma_regs = (void *)(addr + EQOS_DMA_REGS_BASE); | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
1431 | int eqos_get_base_addr_dt(struct udevice *dev) | |
1432 | { | |
1433 | fdt_addr_t addr = dev_read_addr(dev); | |
1434 | return eqos_get_base_addr_common(dev, addr); | |
1435 | } | |
1436 | ||
49d8fe07 PO |
1437 | int eqos_get_base_addr_pci(struct udevice *dev) |
1438 | { | |
1439 | fdt_addr_t addr; | |
1440 | void *paddr; | |
1441 | ||
1442 | paddr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE, | |
1443 | PCI_REGION_MEM); | |
1444 | addr = paddr ? (fdt_addr_t)paddr : FDT_ADDR_T_NONE; | |
1445 | ||
1446 | return eqos_get_base_addr_common(dev, addr); | |
1447 | } | |
1448 | ||
ba4dfef1 SW |
1449 | static int eqos_probe(struct udevice *dev) |
1450 | { | |
1451 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1452 | int ret; | |
1453 | ||
1454 | debug("%s(dev=%p):\n", __func__, dev); | |
1455 | ||
1456 | eqos->dev = dev; | |
ba4dfef1 | 1457 | |
beabef65 PO |
1458 | eqos->config = eqos_get_driver_data(dev); |
1459 | if (!eqos->config) { | |
1460 | pr_err("Failed to get driver data.\n"); | |
ba4dfef1 SW |
1461 | return -ENODEV; |
1462 | } | |
ba4dfef1 | 1463 | |
0c999ce9 RV |
1464 | eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0); |
1465 | ||
ba4dfef1 SW |
1466 | ret = eqos_probe_resources_core(dev); |
1467 | if (ret < 0) { | |
f12001b1 | 1468 | pr_err("eqos_probe_resources_core() failed: %d\n", ret); |
ba4dfef1 SW |
1469 | return ret; |
1470 | } | |
1471 | ||
ac2d4efb | 1472 | ret = eqos->config->ops->eqos_probe_resources(dev); |
ba4dfef1 | 1473 | if (ret < 0) { |
f12001b1 | 1474 | pr_err("eqos_probe_resources() failed: %d\n", ret); |
ba4dfef1 SW |
1475 | goto err_remove_resources_core; |
1476 | } | |
1477 | ||
3fbd17aa MV |
1478 | ret = eqos->config->ops->eqos_start_clks(dev); |
1479 | if (ret < 0) { | |
f12001b1 | 1480 | pr_err("eqos_start_clks() failed: %d\n", ret); |
3fbd17aa MV |
1481 | goto err_remove_resources_tegra; |
1482 | } | |
1483 | ||
6a895d03 YL |
1484 | #ifdef CONFIG_DM_ETH_PHY |
1485 | eqos->mii = eth_phy_get_mdio_bus(dev); | |
1486 | #endif | |
ba4dfef1 | 1487 | if (!eqos->mii) { |
6a895d03 YL |
1488 | eqos->mii = mdio_alloc(); |
1489 | if (!eqos->mii) { | |
f12001b1 | 1490 | pr_err("mdio_alloc() failed\n"); |
6a895d03 | 1491 | ret = -ENOMEM; |
3fbd17aa | 1492 | goto err_stop_clks; |
6a895d03 YL |
1493 | } |
1494 | eqos->mii->read = eqos_mdio_read; | |
1495 | eqos->mii->write = eqos_mdio_write; | |
1496 | eqos->mii->priv = eqos; | |
1497 | strcpy(eqos->mii->name, dev->name); | |
ba4dfef1 | 1498 | |
6a895d03 YL |
1499 | ret = mdio_register(eqos->mii); |
1500 | if (ret < 0) { | |
f12001b1 | 1501 | pr_err("mdio_register() failed: %d\n", ret); |
6a895d03 YL |
1502 | goto err_free_mdio; |
1503 | } | |
ba4dfef1 SW |
1504 | } |
1505 | ||
6a895d03 YL |
1506 | #ifdef CONFIG_DM_ETH_PHY |
1507 | eth_phy_set_mdio_bus(dev, eqos->mii); | |
1508 | #endif | |
1509 | ||
ba4dfef1 SW |
1510 | debug("%s: OK\n", __func__); |
1511 | return 0; | |
1512 | ||
1513 | err_free_mdio: | |
1514 | mdio_free(eqos->mii); | |
3fbd17aa MV |
1515 | err_stop_clks: |
1516 | eqos->config->ops->eqos_stop_clks(dev); | |
ba4dfef1 | 1517 | err_remove_resources_tegra: |
ac2d4efb | 1518 | eqos->config->ops->eqos_remove_resources(dev); |
ba4dfef1 SW |
1519 | err_remove_resources_core: |
1520 | eqos_remove_resources_core(dev); | |
1521 | ||
1522 | debug("%s: returns %d\n", __func__, ret); | |
1523 | return ret; | |
1524 | } | |
1525 | ||
1526 | static int eqos_remove(struct udevice *dev) | |
1527 | { | |
1528 | struct eqos_priv *eqos = dev_get_priv(dev); | |
1529 | ||
1530 | debug("%s(dev=%p):\n", __func__, dev); | |
1531 | ||
1532 | mdio_unregister(eqos->mii); | |
1533 | mdio_free(eqos->mii); | |
3fbd17aa | 1534 | eqos->config->ops->eqos_stop_clks(dev); |
ac2d4efb CR |
1535 | eqos->config->ops->eqos_remove_resources(dev); |
1536 | ||
4a7c9dbf | 1537 | eqos_remove_resources_core(dev); |
ba4dfef1 SW |
1538 | |
1539 | debug("%s: OK\n", __func__); | |
1540 | return 0; | |
1541 | } | |
1542 | ||
149e80f7 | 1543 | int eqos_null_ops(struct udevice *dev) |
c6a0df2d PD |
1544 | { |
1545 | return 0; | |
1546 | } | |
1547 | ||
ba4dfef1 SW |
1548 | static const struct eth_ops eqos_ops = { |
1549 | .start = eqos_start, | |
1550 | .stop = eqos_stop, | |
1551 | .send = eqos_send, | |
1552 | .recv = eqos_recv, | |
1553 | .free_pkt = eqos_free_pkt, | |
1554 | .write_hwaddr = eqos_write_hwaddr, | |
580fab4a | 1555 | .read_rom_hwaddr = eqos_read_rom_hwaddr, |
ba4dfef1 SW |
1556 | }; |
1557 | ||
ac2d4efb | 1558 | static struct eqos_ops eqos_tegra186_ops = { |
6f1e668d MV |
1559 | .eqos_inval_desc = eqos_inval_desc_generic, |
1560 | .eqos_flush_desc = eqos_flush_desc_generic, | |
ac2d4efb CR |
1561 | .eqos_inval_buffer = eqos_inval_buffer_tegra186, |
1562 | .eqos_flush_buffer = eqos_flush_buffer_tegra186, | |
1563 | .eqos_probe_resources = eqos_probe_resources_tegra186, | |
1564 | .eqos_remove_resources = eqos_remove_resources_tegra186, | |
1565 | .eqos_stop_resets = eqos_stop_resets_tegra186, | |
1566 | .eqos_start_resets = eqos_start_resets_tegra186, | |
1567 | .eqos_stop_clks = eqos_stop_clks_tegra186, | |
1568 | .eqos_start_clks = eqos_start_clks_tegra186, | |
1569 | .eqos_calibrate_pads = eqos_calibrate_pads_tegra186, | |
1570 | .eqos_disable_calibration = eqos_disable_calibration_tegra186, | |
1571 | .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186, | |
acce23b8 | 1572 | .eqos_get_enetaddr = eqos_null_ops, |
ac2d4efb CR |
1573 | .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186 |
1574 | }; | |
1575 | ||
a08f2f7b | 1576 | static const struct eqos_config __maybe_unused eqos_tegra186_config = { |
ba4dfef1 | 1577 | .reg_access_always_ok = false, |
ac2d4efb CR |
1578 | .mdio_wait = 10, |
1579 | .swr_wait = 10, | |
1580 | .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB, | |
1581 | .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35, | |
6f1e668d | 1582 | .axi_bus_width = EQOS_AXI_WIDTH_128, |
ac2d4efb CR |
1583 | .interface = eqos_get_interface_tegra186, |
1584 | .ops = &eqos_tegra186_ops | |
1585 | }; | |
1586 | ||
ba4dfef1 | 1587 | static const struct udevice_id eqos_ids[] = { |
a08f2f7b | 1588 | #if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186) |
ba4dfef1 SW |
1589 | { |
1590 | .compatible = "nvidia,tegra186-eqos", | |
1591 | .data = (ulong)&eqos_tegra186_config | |
1592 | }, | |
a08f2f7b PD |
1593 | #endif |
1594 | #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32) | |
882b2287 CR |
1595 | { |
1596 | .compatible = "st,stm32mp13-dwmac", | |
1597 | .data = (ulong)&eqos_stm32mp13_config | |
1598 | }, | |
ac2d4efb | 1599 | { |
a718a5d0 | 1600 | .compatible = "st,stm32mp1-dwmac", |
85d1de9a | 1601 | .data = (ulong)&eqos_stm32mp15_config |
ac2d4efb | 1602 | }, |
a08f2f7b PD |
1603 | #endif |
1604 | #if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX) | |
3a97da12 | 1605 | { |
3fa3f23d | 1606 | .compatible = "nxp,imx8mp-dwmac-eqos", |
3a97da12 FD |
1607 | .data = (ulong)&eqos_imx_config |
1608 | }, | |
9e1f79bd SS |
1609 | { |
1610 | .compatible = "nxp,imx93-dwmac-eqos", | |
1611 | .data = (ulong)&eqos_imx_config | |
1612 | }, | |
a08f2f7b | 1613 | #endif |
8e76ff61 JK |
1614 | #if IS_ENABLED(CONFIG_DWC_ETH_QOS_ROCKCHIP) |
1615 | { | |
1616 | .compatible = "rockchip,rk3568-gmac", | |
1617 | .data = (ulong)&eqos_rockchip_config | |
1618 | }, | |
01b8ed47 JK |
1619 | { |
1620 | .compatible = "rockchip,rk3588-gmac", | |
1621 | .data = (ulong)&eqos_rockchip_config | |
1622 | }, | |
8e76ff61 | 1623 | #endif |
d382025d SG |
1624 | #if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM) |
1625 | { | |
1626 | .compatible = "qcom,qcs404-ethqos", | |
1627 | .data = (ulong)&eqos_qcom_config | |
1628 | }, | |
1629 | #endif | |
736733b4 YW |
1630 | #if IS_ENABLED(CONFIG_DWC_ETH_QOS_STARFIVE) |
1631 | { | |
1632 | .compatible = "starfive,jh7110-dwmac", | |
1633 | .data = (ulong)&eqos_jh7110_config | |
1634 | }, | |
1635 | #endif | |
ba4dfef1 SW |
1636 | { } |
1637 | }; | |
1638 | ||
1639 | U_BOOT_DRIVER(eth_eqos) = { | |
1640 | .name = "eth_eqos", | |
1641 | .id = UCLASS_ETH, | |
3a97da12 | 1642 | .of_match = of_match_ptr(eqos_ids), |
2689b14e | 1643 | .bind = eqos_bind, |
ba4dfef1 SW |
1644 | .probe = eqos_probe, |
1645 | .remove = eqos_remove, | |
1646 | .ops = &eqos_ops, | |
41575d8e | 1647 | .priv_auto = sizeof(struct eqos_priv), |
caa4daa2 | 1648 | .plat_auto = sizeof(struct eth_pdata), |
ba4dfef1 | 1649 | }; |