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120b5ef2 AM |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * ENETC ethernet controller driver | |
4 | * Copyright 2017-2019 NXP | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <dm.h> | |
9 | #include <errno.h> | |
336d4615 | 10 | #include <malloc.h> |
120b5ef2 AM |
11 | #include <memalign.h> |
12 | #include <asm/io.h> | |
13 | #include <pci.h> | |
1d99534b | 14 | #include <miiphy.h> |
120b5ef2 AM |
15 | |
16 | #include "fsl_enetc.h" | |
17 | ||
9c2aee1b AM |
18 | #define ENETC_DRIVER_NAME "enetc_eth" |
19 | ||
20 | /* | |
21 | * sets the MAC address in IERB registers, this setting is persistent and | |
22 | * carried over to Linux. | |
23 | */ | |
24 | static void enetc_set_ierb_primary_mac(struct udevice *dev, int devfn, | |
25 | const u8 *enetaddr) | |
26 | { | |
27 | #ifdef CONFIG_ARCH_LS1028A | |
28 | /* | |
29 | * LS1028A is the only part with IERB at this time and there are plans to change | |
30 | * its structure, keep this LS1028A specific for now | |
31 | */ | |
32 | #define IERB_BASE 0x1f0800000ULL | |
33 | #define IERB_PFMAC(pf, vf, n) (IERB_BASE + 0x8000 + (pf) * 0x100 + (vf) * 8 \ | |
34 | + (n) * 4) | |
35 | ||
36 | static int ierb_fn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; | |
37 | ||
38 | u16 lower = *(const u16 *)(enetaddr + 4); | |
39 | u32 upper = *(const u32 *)enetaddr; | |
40 | ||
41 | if (ierb_fn_to_pf[devfn] < 0) | |
42 | return; | |
43 | ||
44 | out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 0), upper); | |
45 | out_le32(IERB_PFMAC(ierb_fn_to_pf[devfn], 0, 1), (u32)lower); | |
46 | #endif | |
47 | } | |
48 | ||
49 | /* sets up primary MAC addresses in DT/IERB */ | |
50 | void fdt_fixup_enetc_mac(void *blob) | |
51 | { | |
52 | struct pci_child_platdata *ppdata; | |
53 | struct eth_pdata *pdata; | |
54 | struct udevice *dev; | |
55 | struct uclass *uc; | |
56 | char path[256]; | |
57 | int offset; | |
58 | int devfn; | |
59 | ||
60 | uclass_get(UCLASS_ETH, &uc); | |
61 | uclass_foreach_dev(dev, uc) { | |
62 | if (!dev->driver || !dev->driver->name || | |
63 | strcmp(dev->driver->name, ENETC_DRIVER_NAME)) | |
64 | continue; | |
65 | ||
66 | pdata = dev_get_platdata(dev); | |
67 | ppdata = dev_get_parent_platdata(dev); | |
68 | devfn = PCI_FUNC(ppdata->devfn); | |
69 | ||
70 | enetc_set_ierb_primary_mac(dev, devfn, pdata->enetaddr); | |
71 | ||
72 | snprintf(path, 256, "/soc/pcie@1f0000000/ethernet@%x,%x", | |
73 | PCI_DEV(ppdata->devfn), PCI_FUNC(ppdata->devfn)); | |
74 | offset = fdt_path_offset(blob, path); | |
75 | if (offset < 0) | |
76 | continue; | |
77 | fdt_setprop(blob, offset, "mac-address", pdata->enetaddr, 6); | |
78 | } | |
79 | } | |
80 | ||
120b5ef2 AM |
81 | /* |
82 | * Bind the device: | |
83 | * - set a more explicit name on the interface | |
84 | */ | |
85 | static int enetc_bind(struct udevice *dev) | |
86 | { | |
87 | char name[16]; | |
88 | static int eth_num_devices; | |
89 | ||
90 | /* | |
91 | * prefer using PCI function numbers to number interfaces, but these | |
92 | * are only available if dts nodes are present. For PCI they are | |
93 | * optional, handle that case too. Just in case some nodes are present | |
94 | * and some are not, use different naming scheme - enetc-N based on | |
95 | * PCI function # and enetc#N based on interface count | |
96 | */ | |
97 | if (ofnode_valid(dev->node)) | |
98 | sprintf(name, "enetc-%u", PCI_FUNC(pci_get_devfn(dev))); | |
99 | else | |
100 | sprintf(name, "enetc#%u", eth_num_devices++); | |
101 | device_set_name(dev, name); | |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
e4aafd5c AM |
106 | /* MDIO wrappers, we're using these to drive internal MDIO to get to serdes */ |
107 | static int enetc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) | |
108 | { | |
109 | struct enetc_mdio_priv priv; | |
110 | ||
111 | priv.regs_base = bus->priv; | |
112 | return enetc_mdio_read_priv(&priv, addr, devad, reg); | |
113 | } | |
114 | ||
115 | static int enetc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, | |
116 | u16 val) | |
117 | { | |
118 | struct enetc_mdio_priv priv; | |
119 | ||
120 | priv.regs_base = bus->priv; | |
121 | return enetc_mdio_write_priv(&priv, addr, devad, reg, val); | |
122 | } | |
123 | ||
124 | /* only interfaces that can pin out through serdes have internal MDIO */ | |
125 | static bool enetc_has_imdio(struct udevice *dev) | |
126 | { | |
127 | struct enetc_priv *priv = dev_get_priv(dev); | |
128 | ||
129 | return !!(priv->imdio.priv); | |
130 | } | |
131 | ||
132 | /* set up serdes for SGMII */ | |
133 | static int enetc_init_sgmii(struct udevice *dev) | |
134 | { | |
135 | struct enetc_priv *priv = dev_get_priv(dev); | |
9bc07e81 AM |
136 | bool is2500 = false; |
137 | u16 reg; | |
e4aafd5c AM |
138 | |
139 | if (!enetc_has_imdio(dev)) | |
140 | return 0; | |
141 | ||
9bc07e81 AM |
142 | if (priv->if_type == PHY_INTERFACE_MODE_SGMII_2500) |
143 | is2500 = true; | |
144 | ||
145 | /* | |
146 | * Set to SGMII mode, for 1Gbps enable AN, for 2.5Gbps set fixed speed. | |
147 | * Although fixed speed is 1Gbps, we could be running at 2.5Gbps based | |
148 | * on PLL configuration. Setting 1G for 2.5G here is counter intuitive | |
149 | * but intentional. | |
150 | */ | |
151 | reg = ENETC_PCS_IF_MODE_SGMII; | |
152 | reg |= is2500 ? ENETC_PCS_IF_MODE_SPEED_1G : ENETC_PCS_IF_MODE_SGMII_AN; | |
e4aafd5c | 153 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, |
9bc07e81 | 154 | ENETC_PCS_IF_MODE, reg); |
e4aafd5c AM |
155 | |
156 | /* Dev ability - SGMII */ | |
157 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
158 | ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SGMII); | |
159 | ||
160 | /* Adjust link timer for SGMII */ | |
161 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
162 | ENETC_PCS_LINK_TIMER1, ENETC_PCS_LINK_TIMER1_VAL); | |
163 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
164 | ENETC_PCS_LINK_TIMER2, ENETC_PCS_LINK_TIMER2_VAL); | |
165 | ||
9bc07e81 AM |
166 | reg = ENETC_PCS_CR_DEF_VAL; |
167 | reg |= is2500 ? ENETC_PCS_CR_RST : ENETC_PCS_CR_RESET_AN; | |
e4aafd5c AM |
168 | /* restart PCS AN */ |
169 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, MDIO_DEVAD_NONE, | |
9bc07e81 | 170 | ENETC_PCS_CR, reg); |
e4aafd5c AM |
171 | |
172 | return 0; | |
173 | } | |
174 | ||
175 | /* set up MAC for RGMII */ | |
176 | static int enetc_init_rgmii(struct udevice *dev) | |
177 | { | |
178 | struct enetc_priv *priv = dev_get_priv(dev); | |
179 | u32 if_mode; | |
180 | ||
181 | /* enable RGMII AN */ | |
182 | if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); | |
183 | if_mode |= ENETC_PM_IF_MODE_AN_ENA; | |
184 | enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
b8e4eec7 AM |
189 | /* set up MAC configuration for the given interface type */ |
190 | static void enetc_setup_mac_iface(struct udevice *dev) | |
e4aafd5c AM |
191 | { |
192 | struct enetc_priv *priv = dev_get_priv(dev); | |
193 | u32 if_mode; | |
194 | ||
b8e4eec7 AM |
195 | switch (priv->if_type) { |
196 | case PHY_INTERFACE_MODE_RGMII: | |
197 | case PHY_INTERFACE_MODE_RGMII_ID: | |
198 | case PHY_INTERFACE_MODE_RGMII_RXID: | |
199 | case PHY_INTERFACE_MODE_RGMII_TXID: | |
200 | enetc_init_rgmii(dev); | |
201 | break; | |
202 | case PHY_INTERFACE_MODE_XGMII: | |
203 | case PHY_INTERFACE_MODE_USXGMII: | |
204 | case PHY_INTERFACE_MODE_XFI: | |
205 | /* set ifmode to (US)XGMII */ | |
206 | if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); | |
207 | if_mode &= ~ENETC_PM_IF_IFMODE_MASK; | |
208 | enetc_write_port(priv, ENETC_PM_IF_MODE, if_mode); | |
209 | break; | |
210 | }; | |
211 | } | |
212 | ||
213 | /* set up serdes for SXGMII */ | |
214 | static int enetc_init_sxgmii(struct udevice *dev) | |
215 | { | |
216 | struct enetc_priv *priv = dev_get_priv(dev); | |
e4aafd5c AM |
217 | |
218 | if (!enetc_has_imdio(dev)) | |
219 | return 0; | |
220 | ||
221 | /* Dev ability - SXGMII */ | |
222 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, | |
223 | ENETC_PCS_DEV_ABILITY, ENETC_PCS_DEV_ABILITY_SXGMII); | |
224 | ||
225 | /* Restart PCS AN */ | |
226 | enetc_mdio_write(&priv->imdio, ENETC_PCS_PHY_ADDR, ENETC_PCS_DEVAD_REPL, | |
227 | ENETC_PCS_CR, | |
9bc07e81 | 228 | ENETC_PCS_CR_RST | ENETC_PCS_CR_RESET_AN); |
e4aafd5c AM |
229 | |
230 | return 0; | |
231 | } | |
232 | ||
233 | /* Apply protocol specific configuration to MAC, serdes as needed */ | |
234 | static void enetc_start_pcs(struct udevice *dev) | |
235 | { | |
236 | struct enetc_priv *priv = dev_get_priv(dev); | |
237 | const char *if_str; | |
238 | ||
239 | priv->if_type = PHY_INTERFACE_MODE_NONE; | |
240 | ||
1e354cb3 | 241 | /* register internal MDIO for debug purposes */ |
e4aafd5c | 242 | if (enetc_read_port(priv, ENETC_PCAPR0) & ENETC_PCAPRO_MDIO) { |
e4aafd5c AM |
243 | priv->imdio.read = enetc_mdio_read; |
244 | priv->imdio.write = enetc_mdio_write; | |
245 | priv->imdio.priv = priv->port_regs + ENETC_PM_IMDIO_BASE; | |
246 | strncpy(priv->imdio.name, dev->name, MDIO_NAME_LEN); | |
1e354cb3 AM |
247 | if (!miiphy_get_dev_by_name(priv->imdio.name)) |
248 | mdio_register(&priv->imdio); | |
e4aafd5c AM |
249 | } |
250 | ||
251 | if (!ofnode_valid(dev->node)) { | |
252 | enetc_dbg(dev, "no enetc ofnode found, skipping PCS set-up\n"); | |
253 | return; | |
254 | } | |
255 | ||
256 | if_str = ofnode_read_string(dev->node, "phy-mode"); | |
257 | if (if_str) | |
258 | priv->if_type = phy_get_interface_by_name(if_str); | |
259 | else | |
260 | enetc_dbg(dev, | |
261 | "phy-mode property not found, defaulting to SGMII\n"); | |
262 | if (priv->if_type < 0) | |
263 | priv->if_type = PHY_INTERFACE_MODE_NONE; | |
264 | ||
265 | switch (priv->if_type) { | |
266 | case PHY_INTERFACE_MODE_SGMII: | |
9bc07e81 | 267 | case PHY_INTERFACE_MODE_SGMII_2500: |
e4aafd5c AM |
268 | enetc_init_sgmii(dev); |
269 | break; | |
e4aafd5c | 270 | case PHY_INTERFACE_MODE_XGMII: |
e22e3aff AM |
271 | case PHY_INTERFACE_MODE_USXGMII: |
272 | case PHY_INTERFACE_MODE_XFI: | |
e4aafd5c AM |
273 | enetc_init_sxgmii(dev); |
274 | break; | |
275 | }; | |
276 | } | |
277 | ||
1d99534b | 278 | /* Configure the actual/external ethernet PHY, if one is found */ |
17bd7eae | 279 | static void enetc_config_phy(struct udevice *dev) |
1d99534b AM |
280 | { |
281 | struct enetc_priv *priv = dev_get_priv(dev); | |
1d99534b AM |
282 | int supported; |
283 | ||
17bd7eae | 284 | priv->phy = dm_eth_phy_connect(dev); |
1d99534b | 285 | |
17bd7eae | 286 | if (!priv->phy) |
1d99534b | 287 | return; |
1d99534b | 288 | |
307f8a6d AM |
289 | supported = PHY_GBIT_FEATURES | SUPPORTED_2500baseX_Full; |
290 | priv->phy->supported &= supported; | |
291 | priv->phy->advertising &= supported; | |
17bd7eae AM |
292 | |
293 | phy_config(priv->phy); | |
1d99534b AM |
294 | } |
295 | ||
120b5ef2 AM |
296 | /* |
297 | * Probe ENETC driver: | |
298 | * - initialize port and station interface BARs | |
299 | */ | |
300 | static int enetc_probe(struct udevice *dev) | |
301 | { | |
302 | struct enetc_priv *priv = dev_get_priv(dev); | |
303 | ||
304 | if (ofnode_valid(dev->node) && !ofnode_is_available(dev->node)) { | |
305 | enetc_dbg(dev, "interface disabled\n"); | |
306 | return -ENODEV; | |
307 | } | |
308 | ||
309 | priv->enetc_txbd = memalign(ENETC_BD_ALIGN, | |
310 | sizeof(struct enetc_tx_bd) * ENETC_BD_CNT); | |
311 | priv->enetc_rxbd = memalign(ENETC_BD_ALIGN, | |
312 | sizeof(union enetc_rx_bd) * ENETC_BD_CNT); | |
313 | ||
314 | if (!priv->enetc_txbd || !priv->enetc_rxbd) { | |
315 | /* free should be able to handle NULL, just free all pointers */ | |
316 | free(priv->enetc_txbd); | |
317 | free(priv->enetc_rxbd); | |
318 | ||
319 | return -ENOMEM; | |
320 | } | |
321 | ||
322 | /* initialize register */ | |
323 | priv->regs_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0); | |
324 | if (!priv->regs_base) { | |
325 | enetc_dbg(dev, "failed to map BAR0\n"); | |
326 | return -EINVAL; | |
327 | } | |
328 | priv->port_regs = priv->regs_base + ENETC_PORT_REGS_OFF; | |
329 | ||
330 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); | |
331 | ||
a931f783 AM |
332 | enetc_start_pcs(dev); |
333 | enetc_config_phy(dev); | |
334 | ||
120b5ef2 AM |
335 | return 0; |
336 | } | |
337 | ||
338 | /* | |
339 | * Remove the driver from an interface: | |
340 | * - free up allocated memory | |
341 | */ | |
342 | static int enetc_remove(struct udevice *dev) | |
343 | { | |
344 | struct enetc_priv *priv = dev_get_priv(dev); | |
345 | ||
346 | free(priv->enetc_txbd); | |
347 | free(priv->enetc_rxbd); | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
42c66f05 MW |
352 | /* |
353 | * LS1028A is the only part with IERB at this time and there are plans to | |
354 | * change its structure, keep this LS1028A specific for now. | |
355 | */ | |
356 | #define LS1028A_IERB_BASE 0x1f0800000ULL | |
357 | #define LS1028A_IERB_PSIPMAR0(pf, vf) (LS1028A_IERB_BASE + 0x8000 \ | |
358 | + (pf) * 0x100 + (vf) * 8) | |
359 | #define LS1028A_IERB_PSIPMAR1(pf, vf) (LS1028A_IERB_PSIPMAR0(pf, vf) + 4) | |
360 | ||
361 | static int enetc_ls1028a_write_hwaddr(struct udevice *dev) | |
362 | { | |
363 | struct pci_child_platdata *ppdata = dev_get_parent_platdata(dev); | |
364 | const int devfn_to_pf[] = {0, 1, 2, -1, -1, -1, 3}; | |
365 | struct eth_pdata *plat = dev_get_platdata(dev); | |
366 | int devfn = PCI_FUNC(ppdata->devfn); | |
367 | u8 *addr = plat->enetaddr; | |
368 | u32 lower, upper; | |
369 | int pf; | |
370 | ||
371 | if (devfn >= ARRAY_SIZE(devfn_to_pf)) | |
372 | return 0; | |
373 | ||
374 | pf = devfn_to_pf[devfn]; | |
375 | if (pf < 0) | |
376 | return 0; | |
377 | ||
378 | lower = *(const u16 *)(addr + 4); | |
379 | upper = *(const u32 *)addr; | |
380 | ||
381 | out_le32(LS1028A_IERB_PSIPMAR0(pf, 0), upper); | |
382 | out_le32(LS1028A_IERB_PSIPMAR1(pf, 0), lower); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
ee5c70b8 | 387 | static int enetc_write_hwaddr(struct udevice *dev) |
120b5ef2 | 388 | { |
ee5c70b8 MW |
389 | struct eth_pdata *plat = dev_get_platdata(dev); |
390 | struct enetc_priv *priv = dev_get_priv(dev); | |
391 | u8 *addr = plat->enetaddr; | |
392 | ||
42c66f05 MW |
393 | if (IS_ENABLED(CONFIG_ARCH_LS1028A)) |
394 | return enetc_ls1028a_write_hwaddr(dev); | |
395 | ||
120b5ef2 AM |
396 | u16 lower = *(const u16 *)(addr + 4); |
397 | u32 upper = *(const u32 *)addr; | |
398 | ||
399 | enetc_write_port(priv, ENETC_PSIPMAR0, upper); | |
400 | enetc_write_port(priv, ENETC_PSIPMAR1, lower); | |
ee5c70b8 MW |
401 | |
402 | return 0; | |
120b5ef2 AM |
403 | } |
404 | ||
405 | /* Configure port parameters (# of rings, frame size, enable port) */ | |
406 | static void enetc_enable_si_port(struct enetc_priv *priv) | |
407 | { | |
408 | u32 val; | |
409 | ||
410 | /* set Rx/Tx BDR count */ | |
411 | val = ENETC_PSICFGR_SET_TXBDR(ENETC_TX_BDR_CNT); | |
412 | val |= ENETC_PSICFGR_SET_RXBDR(ENETC_RX_BDR_CNT); | |
413 | enetc_write_port(priv, ENETC_PSICFGR(0), val); | |
414 | /* set Rx max frame size */ | |
415 | enetc_write_port(priv, ENETC_PM_MAXFRM, ENETC_RX_MAXFRM_SIZE); | |
416 | /* enable MAC port */ | |
417 | enetc_write_port(priv, ENETC_PM_CC, ENETC_PM_CC_RX_TX_EN); | |
418 | /* enable port */ | |
419 | enetc_write_port(priv, ENETC_PMR, ENETC_PMR_SI0_EN); | |
420 | /* set SI cache policy */ | |
421 | enetc_write(priv, ENETC_SICAR0, | |
422 | ENETC_SICAR_RD_CFG | ENETC_SICAR_WR_CFG); | |
423 | /* enable SI */ | |
424 | enetc_write(priv, ENETC_SIMR, ENETC_SIMR_EN); | |
425 | } | |
426 | ||
427 | /* returns DMA address for a given buffer index */ | |
428 | static inline u64 enetc_rxb_address(struct udevice *dev, int i) | |
429 | { | |
430 | return cpu_to_le64(dm_pci_virt_to_mem(dev, net_rx_packets[i])); | |
431 | } | |
432 | ||
433 | /* | |
434 | * Setup a single Tx BD Ring (ID = 0): | |
435 | * - set Tx buffer descriptor address | |
436 | * - set the BD count | |
437 | * - initialize the producer and consumer index | |
438 | */ | |
439 | static void enetc_setup_tx_bdr(struct udevice *dev) | |
440 | { | |
441 | struct enetc_priv *priv = dev_get_priv(dev); | |
442 | struct bd_ring *tx_bdr = &priv->tx_bdr; | |
443 | u64 tx_bd_add = (u64)priv->enetc_txbd; | |
444 | ||
445 | /* used later to advance to the next Tx BD */ | |
446 | tx_bdr->bd_count = ENETC_BD_CNT; | |
447 | tx_bdr->next_prod_idx = 0; | |
448 | tx_bdr->next_cons_idx = 0; | |
449 | tx_bdr->cons_idx = priv->regs_base + | |
450 | ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBCIR); | |
451 | tx_bdr->prod_idx = priv->regs_base + | |
452 | ENETC_BDR(TX, ENETC_TX_BDR_ID, ENETC_TBPIR); | |
453 | ||
454 | /* set Tx BD address */ | |
455 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR0, | |
456 | lower_32_bits(tx_bd_add)); | |
457 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBBAR1, | |
458 | upper_32_bits(tx_bd_add)); | |
459 | /* set Tx 8 BD count */ | |
460 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBLENR, | |
461 | tx_bdr->bd_count); | |
462 | ||
463 | /* reset both producer/consumer indexes */ | |
464 | enetc_write_reg(tx_bdr->cons_idx, tx_bdr->next_cons_idx); | |
465 | enetc_write_reg(tx_bdr->prod_idx, tx_bdr->next_prod_idx); | |
466 | ||
467 | /* enable TX ring */ | |
468 | enetc_bdr_write(priv, TX, ENETC_TX_BDR_ID, ENETC_TBMR, ENETC_TBMR_EN); | |
469 | } | |
470 | ||
471 | /* | |
472 | * Setup a single Rx BD Ring (ID = 0): | |
473 | * - set Rx buffer descriptors address (one descriptor per buffer) | |
474 | * - set buffer size as max frame size | |
475 | * - enable Rx ring | |
476 | * - reset consumer and producer indexes | |
477 | * - set buffer for each descriptor | |
478 | */ | |
479 | static void enetc_setup_rx_bdr(struct udevice *dev) | |
480 | { | |
481 | struct enetc_priv *priv = dev_get_priv(dev); | |
482 | struct bd_ring *rx_bdr = &priv->rx_bdr; | |
483 | u64 rx_bd_add = (u64)priv->enetc_rxbd; | |
484 | int i; | |
485 | ||
486 | /* used later to advance to the next BD produced by ENETC HW */ | |
487 | rx_bdr->bd_count = ENETC_BD_CNT; | |
488 | rx_bdr->next_prod_idx = 0; | |
489 | rx_bdr->next_cons_idx = 0; | |
490 | rx_bdr->cons_idx = priv->regs_base + | |
491 | ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBCIR); | |
492 | rx_bdr->prod_idx = priv->regs_base + | |
493 | ENETC_BDR(RX, ENETC_RX_BDR_ID, ENETC_RBPIR); | |
494 | ||
495 | /* set Rx BD address */ | |
496 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR0, | |
497 | lower_32_bits(rx_bd_add)); | |
498 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBAR1, | |
499 | upper_32_bits(rx_bd_add)); | |
500 | /* set Rx BD count (multiple of 8) */ | |
501 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBLENR, | |
502 | rx_bdr->bd_count); | |
503 | /* set Rx buffer size */ | |
504 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBBSR, PKTSIZE_ALIGN); | |
505 | ||
506 | /* fill Rx BD */ | |
507 | memset(priv->enetc_rxbd, 0, | |
508 | rx_bdr->bd_count * sizeof(union enetc_rx_bd)); | |
509 | for (i = 0; i < rx_bdr->bd_count; i++) { | |
510 | priv->enetc_rxbd[i].w.addr = enetc_rxb_address(dev, i); | |
511 | /* each RX buffer must be aligned to 64B */ | |
512 | WARN_ON(priv->enetc_rxbd[i].w.addr & (ARCH_DMA_MINALIGN - 1)); | |
513 | } | |
514 | ||
515 | /* reset producer (ENETC owned) and consumer (SW owned) index */ | |
516 | enetc_write_reg(rx_bdr->cons_idx, rx_bdr->next_cons_idx); | |
517 | enetc_write_reg(rx_bdr->prod_idx, rx_bdr->next_prod_idx); | |
518 | ||
519 | /* enable Rx ring */ | |
520 | enetc_bdr_write(priv, RX, ENETC_RX_BDR_ID, ENETC_RBMR, ENETC_RBMR_EN); | |
521 | } | |
522 | ||
523 | /* | |
524 | * Start ENETC interface: | |
525 | * - perform FLR | |
526 | * - enable access to port and SI registers | |
527 | * - set mac address | |
528 | * - setup TX/RX buffer descriptors | |
529 | * - enable Tx/Rx rings | |
530 | */ | |
531 | static int enetc_start(struct udevice *dev) | |
532 | { | |
120b5ef2 AM |
533 | struct enetc_priv *priv = dev_get_priv(dev); |
534 | ||
535 | /* reset and enable the PCI device */ | |
536 | dm_pci_flr(dev); | |
537 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, | |
538 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
539 | ||
120b5ef2 AM |
540 | enetc_enable_si_port(priv); |
541 | ||
542 | /* setup Tx/Rx buffer descriptors */ | |
543 | enetc_setup_tx_bdr(dev); | |
544 | enetc_setup_rx_bdr(dev); | |
545 | ||
b8e4eec7 | 546 | enetc_setup_mac_iface(dev); |
a931f783 | 547 | |
17bd7eae AM |
548 | if (priv->phy) |
549 | phy_startup(priv->phy); | |
1d99534b | 550 | |
120b5ef2 AM |
551 | return 0; |
552 | } | |
553 | ||
554 | /* | |
555 | * Stop the network interface: | |
556 | * - just quiesce it, we can wipe all configuration as _start starts from | |
557 | * scratch each time | |
558 | */ | |
559 | static void enetc_stop(struct udevice *dev) | |
560 | { | |
561 | /* FLR is sufficient to quiesce the device */ | |
562 | dm_pci_flr(dev); | |
1e354cb3 AM |
563 | /* leave the BARs accessible after we stop, this is needed to use |
564 | * internal MDIO in command line. | |
565 | */ | |
566 | dm_pci_clrset_config16(dev, PCI_COMMAND, 0, PCI_COMMAND_MEMORY); | |
120b5ef2 AM |
567 | } |
568 | ||
569 | /* | |
570 | * ENETC transmit packet: | |
571 | * - check if Tx BD ring is full | |
572 | * - set buffer/packet address (dma address) | |
573 | * - set final fragment flag | |
574 | * - try while producer index equals consumer index or timeout | |
575 | */ | |
576 | static int enetc_send(struct udevice *dev, void *packet, int length) | |
577 | { | |
578 | struct enetc_priv *priv = dev_get_priv(dev); | |
579 | struct bd_ring *txr = &priv->tx_bdr; | |
580 | void *nv_packet = (void *)packet; | |
581 | int tries = ENETC_POLL_TRIES; | |
582 | u32 pi, ci; | |
583 | ||
584 | pi = txr->next_prod_idx; | |
585 | ci = enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK; | |
586 | /* Tx ring is full when */ | |
587 | if (((pi + 1) % txr->bd_count) == ci) { | |
588 | enetc_dbg(dev, "Tx BDR full\n"); | |
589 | return -ETIMEDOUT; | |
590 | } | |
591 | enetc_dbg(dev, "TxBD[%d]send: pkt_len=%d, buff @0x%x%08x\n", pi, length, | |
592 | upper_32_bits((u64)nv_packet), lower_32_bits((u64)nv_packet)); | |
593 | ||
594 | /* prepare Tx BD */ | |
595 | memset(&priv->enetc_txbd[pi], 0x0, sizeof(struct enetc_tx_bd)); | |
596 | priv->enetc_txbd[pi].addr = | |
597 | cpu_to_le64(dm_pci_virt_to_mem(dev, nv_packet)); | |
598 | priv->enetc_txbd[pi].buf_len = cpu_to_le16(length); | |
599 | priv->enetc_txbd[pi].frm_len = cpu_to_le16(length); | |
600 | priv->enetc_txbd[pi].flags = cpu_to_le16(ENETC_TXBD_FLAGS_F); | |
601 | dmb(); | |
602 | /* send frame: increment producer index */ | |
603 | pi = (pi + 1) % txr->bd_count; | |
604 | txr->next_prod_idx = pi; | |
605 | enetc_write_reg(txr->prod_idx, pi); | |
606 | while ((--tries >= 0) && | |
607 | (pi != (enetc_read_reg(txr->cons_idx) & ENETC_BDR_IDX_MASK))) | |
608 | udelay(10); | |
609 | ||
610 | return tries > 0 ? 0 : -ETIMEDOUT; | |
611 | } | |
612 | ||
613 | /* | |
614 | * Receive frame: | |
615 | * - wait for the next BD to get ready bit set | |
616 | * - clean up the descriptor | |
617 | * - move on and indicate to HW that the cleaned BD is available for Rx | |
618 | */ | |
619 | static int enetc_recv(struct udevice *dev, int flags, uchar **packetp) | |
620 | { | |
621 | struct enetc_priv *priv = dev_get_priv(dev); | |
622 | struct bd_ring *rxr = &priv->rx_bdr; | |
623 | int tries = ENETC_POLL_TRIES; | |
624 | int pi = rxr->next_prod_idx; | |
625 | int ci = rxr->next_cons_idx; | |
626 | u32 status; | |
627 | int len; | |
628 | u8 rdy; | |
629 | ||
630 | do { | |
631 | dmb(); | |
632 | status = le32_to_cpu(priv->enetc_rxbd[pi].r.lstatus); | |
633 | /* check if current BD is ready to be consumed */ | |
634 | rdy = ENETC_RXBD_STATUS_R(status); | |
635 | } while (--tries >= 0 && !rdy); | |
636 | ||
637 | if (!rdy) | |
638 | return -EAGAIN; | |
639 | ||
640 | dmb(); | |
641 | len = le16_to_cpu(priv->enetc_rxbd[pi].r.buf_len); | |
642 | *packetp = (uchar *)enetc_rxb_address(dev, pi); | |
643 | enetc_dbg(dev, "RxBD[%d]: len=%d err=%d pkt=0x%x%08x\n", pi, len, | |
644 | ENETC_RXBD_STATUS_ERRORS(status), | |
645 | upper_32_bits((u64)*packetp), lower_32_bits((u64)*packetp)); | |
646 | ||
647 | /* BD clean up and advance to next in ring */ | |
648 | memset(&priv->enetc_rxbd[pi], 0, sizeof(union enetc_rx_bd)); | |
649 | priv->enetc_rxbd[pi].w.addr = enetc_rxb_address(dev, pi); | |
650 | rxr->next_prod_idx = (pi + 1) % rxr->bd_count; | |
651 | ci = (ci + 1) % rxr->bd_count; | |
652 | rxr->next_cons_idx = ci; | |
653 | dmb(); | |
654 | /* free up the slot in the ring for HW */ | |
655 | enetc_write_reg(rxr->cons_idx, ci); | |
656 | ||
657 | return len; | |
658 | } | |
659 | ||
660 | static const struct eth_ops enetc_ops = { | |
661 | .start = enetc_start, | |
662 | .send = enetc_send, | |
663 | .recv = enetc_recv, | |
664 | .stop = enetc_stop, | |
ee5c70b8 | 665 | .write_hwaddr = enetc_write_hwaddr, |
120b5ef2 AM |
666 | }; |
667 | ||
668 | U_BOOT_DRIVER(eth_enetc) = { | |
9c2aee1b | 669 | .name = ENETC_DRIVER_NAME, |
120b5ef2 AM |
670 | .id = UCLASS_ETH, |
671 | .bind = enetc_bind, | |
672 | .probe = enetc_probe, | |
673 | .remove = enetc_remove, | |
674 | .ops = &enetc_ops, | |
675 | .priv_auto_alloc_size = sizeof(struct enetc_priv), | |
676 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
677 | }; | |
678 | ||
679 | static struct pci_device_id enetc_ids[] = { | |
680 | { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_ENETC_ETH) }, | |
681 | {} | |
682 | }; | |
683 | ||
684 | U_BOOT_PCI_DEVICE(eth_enetc, enetc_ids); |