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f1a22522 AY |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | *Copyright (c) 2018 Rockchip Electronics Co., Ltd | |
4 | */ | |
5 | #include <common.h> | |
336d4615 | 6 | #include <malloc.h> |
f1a22522 AY |
7 | #include <asm/io.h> |
8 | #include <asm/arch/grf_rk3308.h> | |
9 | #include <asm/arch-rockchip/hardware.h> | |
10 | #include <asm/gpio.h> | |
11 | #include <debug_uart.h> | |
12 | ||
13 | DECLARE_GLOBAL_DATA_PTR; | |
14 | ||
15 | #include <asm/armv8/mmu.h> | |
16 | static struct mm_region rk3308_mem_map[] = { | |
17 | { | |
18 | .virt = 0x0UL, | |
19 | .phys = 0x0UL, | |
20 | .size = 0xff000000UL, | |
21 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | | |
22 | PTE_BLOCK_INNER_SHARE | |
23 | }, { | |
24 | .virt = 0xff000000UL, | |
25 | .phys = 0xff000000UL, | |
26 | .size = 0x01000000UL, | |
27 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | | |
28 | PTE_BLOCK_NON_SHARE | | |
29 | PTE_BLOCK_PXN | PTE_BLOCK_UXN | |
30 | }, { | |
31 | /* List terminator */ | |
32 | 0, | |
33 | } | |
34 | }; | |
35 | ||
36 | struct mm_region *mem_map = rk3308_mem_map; | |
37 | ||
38 | #define GRF_BASE 0xff000000 | |
39 | #define SGRF_BASE 0xff2b0000 | |
40 | ||
41 | enum { | |
42 | GPIO1C7_SHIFT = 8, | |
43 | GPIO1C7_MASK = GENMASK(11, 8), | |
44 | GPIO1C7_GPIO = 0, | |
45 | GPIO1C7_UART1_RTSN, | |
46 | GPIO1C7_UART2_TX_M0, | |
47 | GPIO1C7_SPI2_MOSI, | |
48 | GPIO1C7_JTAG_TMS, | |
49 | ||
50 | GPIO1C6_SHIFT = 4, | |
51 | GPIO1C6_MASK = GENMASK(7, 4), | |
52 | GPIO1C6_GPIO = 0, | |
53 | GPIO1C6_UART1_CTSN, | |
54 | GPIO1C6_UART2_RX_M0, | |
55 | GPIO1C6_SPI2_MISO, | |
56 | GPIO1C6_JTAG_TCLK, | |
57 | ||
58 | GPIO4D3_SHIFT = 6, | |
59 | GPIO4D3_MASK = GENMASK(7, 6), | |
60 | GPIO4D3_GPIO = 0, | |
61 | GPIO4D3_SDMMC_D3, | |
62 | GPIO4D3_UART2_TX_M1, | |
63 | ||
64 | GPIO4D2_SHIFT = 4, | |
65 | GPIO4D2_MASK = GENMASK(5, 4), | |
66 | GPIO4D2_GPIO = 0, | |
67 | GPIO4D2_SDMMC_D2, | |
68 | GPIO4D2_UART2_RX_M1, | |
69 | ||
70 | UART2_IO_SEL_SHIFT = 2, | |
71 | UART2_IO_SEL_MASK = GENMASK(3, 2), | |
72 | UART2_IO_SEL_M0 = 0, | |
73 | UART2_IO_SEL_M1, | |
74 | UART2_IO_SEL_USB, | |
75 | ||
e0e6c96a DW |
76 | GPIO2C0_SEL_SRC_CTRL_SHIFT = 11, |
77 | GPIO2C0_SEL_SRC_CTRL_MASK = BIT(11), | |
78 | GPIO2C0_SEL_SRC_CTRL_IOMUX = 0, | |
79 | GPIO2C0_SEL_SRC_CTRL_SEL_PLUS, | |
80 | ||
f1a22522 AY |
81 | GPIO3B3_SEL_SRC_CTRL_SHIFT = 7, |
82 | GPIO3B3_SEL_SRC_CTRL_MASK = BIT(7), | |
83 | GPIO3B3_SEL_SRC_CTRL_IOMUX = 0, | |
84 | GPIO3B3_SEL_SRC_CTRL_SEL_PLUS, | |
85 | ||
86 | GPIO3B3_SEL_PLUS_SHIFT = 4, | |
87 | GPIO3B3_SEL_PLUS_MASK = GENMASK(6, 4), | |
88 | GPIO3B3_SEL_PLUS_GPIO3_B3 = 0, | |
89 | GPIO3B3_SEL_PLUS_FLASH_ALE, | |
90 | GPIO3B3_SEL_PLUS_EMMC_PWREN, | |
91 | GPIO3B3_SEL_PLUS_SPI1_CLK, | |
92 | GPIO3B3_SEL_PLUS_LCDC_D23_M1, | |
93 | ||
94 | GPIO3B2_SEL_SRC_CTRL_SHIFT = 3, | |
95 | GPIO3B2_SEL_SRC_CTRL_MASK = BIT(3), | |
96 | GPIO3B2_SEL_SRC_CTRL_IOMUX = 0, | |
97 | GPIO3B2_SEL_SRC_CTRL_SEL_PLUS, | |
98 | ||
99 | GPIO3B2_SEL_PLUS_SHIFT = 0, | |
100 | GPIO3B2_SEL_PLUS_MASK = GENMASK(2, 0), | |
101 | GPIO3B2_SEL_PLUS_GPIO3_B2 = 0, | |
102 | GPIO3B2_SEL_PLUS_FLASH_RDN, | |
103 | GPIO3B2_SEL_PLUS_EMMC_RSTN, | |
104 | GPIO3B2_SEL_PLUS_SPI1_MISO, | |
105 | GPIO3B2_SEL_PLUS_LCDC_D22_M1, | |
e0e6c96a DW |
106 | |
107 | I2C3_IOFUNC_SRC_CTRL_SHIFT = 10, | |
108 | I2C3_IOFUNC_SRC_CTRL_MASK = BIT(10), | |
109 | I2C3_IOFUNC_SRC_CTRL_SEL_PLUS = 1, | |
110 | ||
111 | GPIO2A3_SEL_SRC_CTRL_SHIFT = 7, | |
112 | GPIO2A3_SEL_SRC_CTRL_MASK = BIT(7), | |
113 | GPIO2A3_SEL_SRC_CTRL_SEL_PLUS = 1, | |
114 | ||
115 | GPIO2A2_SEL_SRC_CTRL_SHIFT = 3, | |
116 | GPIO2A2_SEL_SRC_CTRL_MASK = BIT(3), | |
117 | GPIO2A2_SEL_SRC_CTRL_SEL_PLUS = 1, | |
f1a22522 AY |
118 | }; |
119 | ||
120 | enum { | |
121 | IOVSEL3_CTRL_SHIFT = 8, | |
122 | IOVSEL3_CTRL_MASK = BIT(8), | |
123 | VCCIO3_SEL_BY_GPIO = 0, | |
124 | VCCIO3_SEL_BY_IOVSEL3, | |
125 | ||
126 | IOVSEL3_SHIFT = 3, | |
127 | IOVSEL3_MASK = BIT(3), | |
128 | VCCIO3_3V3 = 0, | |
129 | VCCIO3_1V8, | |
130 | }; | |
131 | ||
132 | /* | |
133 | * The voltage of VCCIO3(which is the voltage domain of emmc/flash/sfc | |
134 | * interface) can indicated by GPIO0_A4 or io_vsel3. The SOC defaults | |
135 | * use GPIO0_A4 to indicate power supply voltage for VCCIO3 by hardware, | |
136 | * then we can switch to io_vsel3 after system power on, and release GPIO0_A4 | |
137 | * for other usage. | |
138 | */ | |
139 | ||
140 | #define GPIO0_A4 4 | |
141 | ||
142 | int rk_board_init(void) | |
143 | { | |
144 | static struct rk3308_grf * const grf = (void *)GRF_BASE; | |
145 | u32 val; | |
146 | int ret; | |
147 | ||
148 | ret = gpio_request(GPIO0_A4, "gpio0_a4"); | |
149 | if (ret < 0) { | |
150 | printf("request for gpio0_a4 failed:%d\n", ret); | |
151 | return 0; | |
152 | } | |
153 | ||
154 | gpio_direction_input(GPIO0_A4); | |
155 | ||
156 | if (gpio_get_value(GPIO0_A4)) | |
157 | val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | | |
158 | VCCIO3_1V8 << IOVSEL3_SHIFT; | |
159 | else | |
160 | val = VCCIO3_SEL_BY_IOVSEL3 << IOVSEL3_CTRL_SHIFT | | |
161 | VCCIO3_3V3 << IOVSEL3_SHIFT; | |
162 | rk_clrsetreg(&grf->soc_con0, IOVSEL3_CTRL_MASK | IOVSEL3_MASK, val); | |
163 | ||
164 | gpio_free(GPIO0_A4); | |
165 | return 0; | |
166 | } | |
167 | ||
168 | #if defined(CONFIG_DEBUG_UART) | |
169 | __weak void board_debug_uart_init(void) | |
170 | { | |
171 | static struct rk3308_grf * const grf = (void *)GRF_BASE; | |
172 | ||
173 | /* Enable early UART2 channel m1 on the rk3308 */ | |
174 | rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK, | |
175 | UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT); | |
176 | rk_clrsetreg(&grf->gpio4d_iomux, | |
177 | GPIO4D3_MASK | GPIO4D2_MASK, | |
178 | GPIO4D2_UART2_RX_M1 << GPIO4D2_SHIFT | | |
179 | GPIO4D3_UART2_TX_M1 << GPIO4D3_SHIFT); | |
180 | } | |
181 | #endif | |
182 | ||
183 | #if defined(CONFIG_SPL_BUILD) | |
184 | int arch_cpu_init(void) | |
185 | { | |
186 | static struct rk3308_sgrf * const sgrf = (void *)SGRF_BASE; | |
e0e6c96a | 187 | static struct rk3308_grf * const grf = (void *)GRF_BASE; |
f1a22522 AY |
188 | |
189 | /* Set CRYPTO SDMMC EMMC NAND SFC USB master bus to be secure access */ | |
190 | rk_clrreg(&sgrf->con_secure0, 0x2b83); | |
191 | ||
e0e6c96a DW |
192 | /* |
193 | * Enable plus options to use more pinctrl functions, including | |
194 | * GPIO2A2_PLUS, GPIO2A3_PLUS and I2C3_MULTI_SRC_PLUS. | |
195 | */ | |
196 | rk_clrsetreg(&grf->soc_con13, | |
197 | I2C3_IOFUNC_SRC_CTRL_MASK | GPIO2A3_SEL_SRC_CTRL_MASK | | |
198 | GPIO2A2_SEL_SRC_CTRL_MASK, | |
199 | I2C3_IOFUNC_SRC_CTRL_SEL_PLUS << I2C3_IOFUNC_SRC_CTRL_SHIFT | | |
200 | GPIO2A3_SEL_SRC_CTRL_SEL_PLUS << GPIO2A3_SEL_SRC_CTRL_SHIFT | | |
201 | GPIO2A2_SEL_SRC_CTRL_SEL_PLUS << GPIO2A2_SEL_SRC_CTRL_SHIFT); | |
202 | ||
203 | /* Plus options about GPIO3B2_PLUS, GPIO3B3_PLUS and GPIO2C0_PLUS. */ | |
204 | rk_clrsetreg(&grf->soc_con15, | |
205 | GPIO2C0_SEL_SRC_CTRL_MASK | GPIO3B3_SEL_SRC_CTRL_MASK | | |
206 | GPIO3B2_SEL_SRC_CTRL_MASK, | |
207 | GPIO2C0_SEL_SRC_CTRL_SEL_PLUS << GPIO2C0_SEL_SRC_CTRL_SHIFT | | |
208 | GPIO3B3_SEL_SRC_CTRL_SEL_PLUS << GPIO3B3_SEL_SRC_CTRL_SHIFT | | |
209 | GPIO3B2_SEL_SRC_CTRL_SEL_PLUS << GPIO3B2_SEL_SRC_CTRL_SHIFT); | |
210 | ||
f1a22522 AY |
211 | return 0; |
212 | } | |
213 | #endif |