[J-u-boot.git] / include / configs / omap3_overo.h

/*
 * Configuration settings for the Gumstix Overo board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP				/* in a TI OMAP core */
#define CONFIG_OMAP34XX				/* which is a 34XX */
#define CONFIG_OMAP3_OVERO			/* working with overo */
#define CONFIG_OMAP_GPIO

#define CONFIG_SDRC				/* The chip has SDRC controller */

#include <asm/arch/cpu.h>			/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG

#define CONFIG_OF_LIBFDT

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB */
						/* Sector */
#define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK		48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
					115200}
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/
#undef CONFIG_CMD_NFS		/* NFS support			*/
#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_DRIVER_OMAP34XX_I2C

/*
 * TWL4030
 */
#define CONFIG_TWL4030_POWER
#define CONFIG_TWL4030_LED

/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_QUIET_TEST
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access nand */
							/* at CS0 */
#define GPMC_NAND_ECC_LP_x16_LAYOUT

#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */
						/* devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* size of jffs2 */
							/* partition */

/* Environment information */
#define CONFIG_BOOTDELAY		5

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mpurate=500\0" \
	"optargs=\0" \
	"vram=12M\0" \
	"dvimode=1024x768MR-16@60\0" \
	"defaultdisplay=dvi\0" \
	"mmcdev=0\0" \
	"mmcroot=/dev/mmcblk0p2 rw\0" \
	"mmcrootfstype=ext3 rootwait\0" \
	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
	"nandrootfstype=ubifs\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${mmcroot} " \
		"rootfstype=${mmcrootfstype}\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"mpurate=${mpurate} " \
		"vram=${vram} " \
		"omapfb.mode=dvi:${dvimode} " \
		"omapdss.def_disp=${defaultdisplay} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"Overo # "
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */
/*
 * OMAP3 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP

#define CONFIG_ENV_IS_IN_NAND
#define ONENAND_ENV_OFFSET		0x240000 /* environment starts here */
#define SMNAND_ENV_OFFSET		0x240000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

#if defined(CONFIG_CMD_NET)
/*----------------------------------------------------------------------------
 * SMSC9211 Ethernet from SMSC9118 family
 *----------------------------------------------------------------------------
 */

#define CONFIG_SMC911X
#define CONFIG_SMC911X_32_BIT
#define CONFIG_SMC911X_BASE		0x2C000000

#endif /* (CONFIG_CMD_NET) */

/*
 * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
 * and older u-boot.bin with the new U-Boot SPL.
 */
#define CONFIG_SYS_TEXT_BASE		0x80008000
#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_CACHELINE_SIZE	64

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

/* move malloc and bss high to prevent clashing with the main image */
#define CONFIG_SYS_SPL_MALLOC_START	0x87000000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
#define CONFIG_SPL_BSS_START_ADDR	0x87080000	/* end of minimum RAM */
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

#endif				/* __CONFIG_H */
Commit	Line	Data
9d0fc811 DB	1	/*
	2	* Configuration settings for the Gumstix Overo board.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
9d0fc811 DB	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
9d0fc811 DB	9
	10	/*
	11	* High Level Configuration Options
	12	*/
0f8d3eb9 AM	13	#define CONFIG_OMAP /* in a TI OMAP core */
	14	#define CONFIG_OMAP34XX /* which is a 34XX */
	15	#define CONFIG_OMAP3_OVERO /* working with overo */
308252ad	16	#define CONFIG_OMAP_GPIO
9d0fc811	17
0f8d3eb9	18	#define CONFIG_SDRC /* The chip has SDRC controller */
cae377b5	19
0f8d3eb9	20	#include <asm/arch/cpu.h> /* get chip and board defs */
9d0fc811 DB	21	#include <asm/arch/omap3.h>
9d0fc811 DB	22
6a6b62e3 SP	23	/*
	24	* Display CPU and Board information
	25	*/
0f8d3eb9 AM	26	#define CONFIG_DISPLAY_CPUINFO
0f8d3eb9 AM	27	#define CONFIG_DISPLAY_BOARDINFO
6a6b62e3	28
9d0fc811 DB	29	/* Clock Defines */
	30	#define V_OSCK 26000000 /* Clock output from T2 */
	31	#define V_SCLK (V_OSCK >> 1)
	32
9d0fc811 DB	33	#define CONFIG_MISC_INIT_R
9d0fc811 DB	34
0f8d3eb9 AM	35	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	36	#define CONFIG_SETUP_MEMORY_TAGS
	37	#define CONFIG_INITRD_TAG
	38	#define CONFIG_REVISION_TAG
9d0fc811	39
0f8d3eb9	40	#define CONFIG_OF_LIBFDT
2fa8ca98	41
9d0fc811 DB	42	/*
	43	* Size of malloc() pool
	44	*/
0f8d3eb9	45	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
9d0fc811	46	/* Sector */
0f8d3eb9	47	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
9d0fc811 DB	48
	49	/*
	50	* Hardware drivers
	51	*/
	52
	53	/*
	54	* NS16550 Configuration
	55	*/
0f8d3eb9	56	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
9d0fc811 DB	57
	58	#define CONFIG_SYS_NS16550
	59	#define CONFIG_SYS_NS16550_SERIAL
	60	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	61	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	62
	63	/*
	64	* select serial console configuration
	65	*/
	66	#define CONFIG_CONS_INDEX 3
	67	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	68	#define CONFIG_SERIAL3 3
	69
	70	/* allow to overwrite serial and ethaddr */
	71	#define CONFIG_ENV_OVERWRITE
	72	#define CONFIG_BAUDRATE 115200
	73	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \
	74	115200}
0f8d3eb9 AM	75	#define CONFIG_GENERIC_MMC
	76	#define CONFIG_MMC
	77	#define CONFIG_OMAP_HSMMC
	78	#define CONFIG_DOS_PARTITION
9d0fc811 DB	79
	80	/* commands to include */
	81	#include <config_cmd_default.h>
	82
68b0fbf0	83	#define CONFIG_CMD_CACHE
9d0fc811 DB	84	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	85	#define CONFIG_CMD_FAT /* FAT support */
	86	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	87
	88	#define CONFIG_CMD_I2C /* I2C serial bus support */
	89	#define CONFIG_CMD_MMC /* MMC support */
	90	#define CONFIG_CMD_NAND /* NAND support */
	91
	92	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	93	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	94	#undef CONFIG_CMD_IMI /* iminfo */
	95	#undef CONFIG_CMD_IMLS /* List all found images */
9d0fc811	96	#undef CONFIG_CMD_NFS /* NFS support */
df382626	97	#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
9d0fc811 DB	98
9d0fc811 DB	99	#define CONFIG_SYS_NO_FLASH
0f8d3eb9	100	#define CONFIG_HARD_I2C
9d0fc811 DB	101	#define CONFIG_SYS_I2C_SPEED 100000
9d0fc811 DB	102	#define CONFIG_SYS_I2C_SLAVE 1
0f8d3eb9 AM	103	#define CONFIG_I2C_MULTI_BUS
0f8d3eb9 AM	104	#define CONFIG_DRIVER_OMAP34XX_I2C
9d0fc811	105
2c155130 TR	106	/*
	107	* TWL4030
	108	*/
0f8d3eb9 AM	109	#define CONFIG_TWL4030_POWER
0f8d3eb9 AM	110	#define CONFIG_TWL4030_LED
2c155130	111
9d0fc811 DB	112	/*
	113	* Board NAND Info.
	114	*/
0f8d3eb9	115	#define CONFIG_SYS_NAND_QUIET_TEST
9d0fc811 DB	116	#define CONFIG_NAND_OMAP_GPMC
	117	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	118	/* to access nand */
	119	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	120	/* to access nand */
	121	/* at CS0 */
0f8d3eb9	122	#define GPMC_NAND_ECC_LP_x16_LAYOUT
9d0fc811 DB	123
	124	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
	125	/* devices */
9d0fc811 DB	126	#define CONFIG_JFFS2_NAND
	127	/* nand device jffs2 lives on */
	128	#define CONFIG_JFFS2_DEV "nand0"
	129	/* start of jffs2 partition */
	130	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	131	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
	132	/* partition */
	133
	134	/* Environment information */
	135	#define CONFIG_BOOTDELAY 5
	136
	137	#define CONFIG_EXTRA_ENV_SETTINGS \
	138	"loadaddr=0x82000000\0" \
75b988a2	139	"console=ttyO2,115200n8\0" \
5af32460	140	"mpurate=500\0" \
e6847dba	141	"optargs=\0" \
13d2cb98 SS	142	"vram=12M\0" \
	143	"dvimode=1024x768MR-16@60\0" \
	144	"defaultdisplay=dvi\0" \
cd7c5726	145	"mmcdev=0\0" \
13d2cb98 SS	146	"mmcroot=/dev/mmcblk0p2 rw\0" \
13d2cb98 SS	147	"mmcrootfstype=ext3 rootwait\0" \
254973e6 SS	148	"nandroot=ubi0:rootfs ubi.mtd=4\0" \
254973e6 SS	149	"nandrootfstype=ubifs\0" \
9d0fc811	150	"mmcargs=setenv bootargs console=${console} " \
e6847dba	151	"${optargs} " \
5af32460	152	"mpurate=${mpurate} " \
13d2cb98 SS	153	"vram=${vram} " \
13d2cb98 SS	154	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	155	"omapdss.def_disp=${defaultdisplay} " \
	156	"root=${mmcroot} " \
	157	"rootfstype=${mmcrootfstype}\0" \
9d0fc811	158	"nandargs=setenv bootargs console=${console} " \
e6847dba	159	"${optargs} " \
5af32460	160	"mpurate=${mpurate} " \
13d2cb98 SS	161	"vram=${vram} " \
13d2cb98 SS	162	"omapfb.mode=dvi:${dvimode} " \
13d2cb98 SS	163	"omapdss.def_disp=${defaultdisplay} " \
	164	"root=${nandroot} " \
	165	"rootfstype=${nandrootfstype}\0" \
cd7c5726	166	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
9d0fc811	167	"bootscript=echo Running bootscript from mmc ...; " \
74de7aef	168	"source ${loadaddr}\0" \
cd7c5726	169	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
9d0fc811 DB	170	"mmcboot=echo Booting from mmc ...; " \
	171	"run mmcargs; " \
	172	"bootm ${loadaddr}\0" \
	173	"nandboot=echo Booting from nand ...; " \
	174	"run nandargs; " \
	175	"nand read ${loadaddr} 280000 400000; " \
	176	"bootm ${loadaddr}\0" \
	177
	178	#define CONFIG_BOOTCOMMAND \
66968110	179	"mmc dev ${mmcdev}; if mmc rescan; then " \
9d0fc811 DB	180	"if run loadbootscript; then " \
	181	"run bootscript; " \
	182	"else " \
	183	"if run loaduimage; then " \
	184	"run mmcboot; " \
	185	"else run nandboot; " \
	186	"fi; " \
	187	"fi; " \
	188	"else run nandboot; fi"
	189
	190	#define CONFIG_AUTO_COMPLETE 1
	191	/*
	192	* Miscellaneous configurable options
	193	*/
9d0fc811 DB	194	#define CONFIG_SYS_LONGHELP /* undef to save memory */
9d0fc811 DB	195	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
1270ec13	196	#define CONFIG_SYS_PROMPT "Overo # "
f62b1257	197	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
9d0fc811 DB	198	/* Print Buffer Size */
	199	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	200	sizeof(CONFIG_SYS_PROMPT) + 16)
	201	#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	202	/* args */
	203	/* Boot Argument Buffer Size */
	204	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	205	/* memtest works on */
	206	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	207	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	208	0x01F00000) /* 31MB */
	209
9d0fc811 DB	210	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
9d0fc811 DB	211	/* address */
9d0fc811	212	/*
d3a513c2 MP	213	* OMAP3 has 12 GP timers, they can be driven by the system clock
	214	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	215	* This rate is divided by a local divisor.
9d0fc811	216	*/
d3a513c2 MP	217	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	218	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	219	#define CONFIG_SYS_HZ 1000
9d0fc811	220
9d0fc811 DB	221	/*-----------------------------------------------------------------------
	222	* Physical Memory Map
	223	*/
	224	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	225	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
9d0fc811 DB	226	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
9d0fc811 DB	227
9d0fc811 DB	228	/*-----------------------------------------------------------------------
	229	* FLASH and environment organization
	230	*/
	231
	232	/* ** PISMO SUPPORT * */
	233
	234	/* Configure the PISMO */
	235	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	236	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	237
9c44ddcc	238	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
9d0fc811	239
6cbec7b3 LC	240	#if defined(CONFIG_CMD_NAND)
	241	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	242	#endif
9d0fc811 DB	243
	244	/* Monitor at start of flash */
	245	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	246	#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
	247
0f8d3eb9	248	#define CONFIG_ENV_IS_IN_NAND
9d0fc811 DB	249	#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
	250	#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */
	251
6cbec7b3 LC	252	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
6cbec7b3 LC	253	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
9d0fc811 DB	254	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
9d0fc811 DB	255
df382626 OJ	256	#if defined(CONFIG_CMD_NET)
	257	/*----------------------------------------------------------------------------
	258	* SMSC9211 Ethernet from SMSC9118 family
	259	*----------------------------------------------------------------------------
	260	*/
	261
0f8d3eb9	262	#define CONFIG_SMC911X
df382626	263	#define CONFIG_SMC911X_32_BIT
0f8d3eb9	264	#define CONFIG_SMC911X_BASE 0x2C000000
df382626 OJ	265
	266	#endif /* (CONFIG_CMD_NET) */
	267
137703b8 AM	268	/*
	269	* Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	270	* and older u-boot.bin with the new U-Boot SPL.
	271	*/
	272	#define CONFIG_SYS_TEXT_BASE 0x80008000
4d7d7bc3	273	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
31bfcf1c SS	274	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	275	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	276	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	277	CONFIG_SYS_INIT_RAM_SIZE - \
	278	GENERATED_GBL_DATA_SIZE)
4d7d7bc3	279
8e40852f A	280	#define CONFIG_SYS_CACHELINE_SIZE 64
8e40852f A	281
137703b8 AM	282	/* Defines for SPL */
137703b8 AM	283	#define CONFIG_SPL
47f7bcae	284	#define CONFIG_SPL_FRAMEWORK
137703b8 AM	285	#define CONFIG_SPL_NAND_SIMPLE
137703b8 AM	286	#define CONFIG_SPL_TEXT_BASE 0x40200800
e0820ccc	287	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
137703b8 AM	288	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	289
	290	/* move malloc and bss high to prevent clashing with the main image */
	291	#define CONFIG_SYS_SPL_MALLOC_START 0x87000000
	292	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	293	#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */
	294	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	295
	296	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	297	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
	298	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	299	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	300
49175c49	301	#define CONFIG_SPL_BOARD_INIT
137703b8 AM	302	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	303	#define CONFIG_SPL_LIBDISK_SUPPORT
	304	#define CONFIG_SPL_I2C_SUPPORT
	305	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	306	#define CONFIG_SPL_MMC_SUPPORT
	307	#define CONFIG_SPL_FAT_SUPPORT
	308	#define CONFIG_SPL_SERIAL_SUPPORT
	309	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	310	#define CONFIG_SPL_NAND_BASE
	311	#define CONFIG_SPL_NAND_DRIVERS
	312	#define CONFIG_SPL_NAND_ECC
16e41c85	313	#define CONFIG_SPL_GPIO_SUPPORT
137703b8 AM	314	#define CONFIG_SPL_POWER_SUPPORT
	315	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	316
	317	/* NAND boot config */
	318	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	319	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	320	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	321	#define CONFIG_SYS_NAND_OOBSIZE 64
	322	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	323	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	324	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	325	10, 11, 12, 13}
	326	#define CONFIG_SYS_NAND_ECCSIZE 512
	327	#define CONFIG_SYS_NAND_ECCBYTES 3
137703b8 AM	328	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	329	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	330
9d0fc811	331	#endif /* __CONFIG_H */